JP2002033774A - Device and method for controlling bus termination - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for controlling bus termination, with which the reduction of power consumption is attained in a signal- transmitting state, a load to a device is reduced just after a transition to a standby state and the reduction in leakage current can be attained in the standby state. SOLUTION: This device is provided with control circuits 101, 105 and 107 for connecting a terminal resistor 102 with a DC power source 103, only at waveform transition in the signal transmitting state, disconnecting the terminal resistor 102 from the DC power source 103 in a state immediately after a standby transition transiting all devices connected to a bus 109 into receiving waiting state, performing switching to pull-down resistors 104 and 106 of low resistance, and switching the pull-down resistor 104 of low resistance to the pull-down resistor 106 of high resistance in the standby state, after level-fix transiting all the devices which are connected to the bus 109 into receiving waiting state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus termination adjusting device and a bus termination adjusting method.

[0002]

2. Description of the Related Art Conventionally, there has been an automatic bus termination adjusting circuit for automatically adjusting a bus termination condition in a transmission circuit. The bus termination automatic adjustment circuit is particularly suitable for reducing power consumption, preventing device destruction, and reducing leakage current in a bus using a burst data signal.

[0003] As a conventional example of the above-mentioned automatic bus termination adjusting circuit, for example, a technique described in Japanese Patent Application Laid-Open No. H11-308251 has been proposed. The publication discloses a data transmission circuit having a pull-up / pull-down resistor and a differential line receiver at a data reception 2 input terminal portion from a balanced two-wire bus line, wherein each of the data reception 2 input terminal portions has A data transmission circuit is disclosed which includes a detecting means for detecting a voltage and a potential difference thereof, and a control means for variably controlling the resistance values of the pull-up and pull-down resistors according to the detection outputs. .

[0004]

However, the above-described prior art has the following problems.

In the above-mentioned conventional example, in a bus using a burst-like data signal, the bus and the ground are generally connected via a pull-down resistor having a high resistance and power consumption generated in operating the bus. In this case, the discharge of the charge does not proceed, and the determination to the L level is delayed. For this reason,
Load on the device due to continued uncertain state (CMO that does not allow input of signals whose H level and L level are undefined)
When a device such as an S logic LSI is connected to the bus, this phenomenon may damage the device), and by using a small resistor to quickly determine the level after shifting to high impedance. There has been a concern that power consumption will increase and that a leak current will occur in a high impedance state.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce power consumption by operating a bus only at a bus change timing in a signal transmission state by using a clock and a state detection signal.
Immediately after the transition to the standby state, a low-resistance pull-down or pull-up resistor is connected to quickly determine the L level or the H level from the high impedance, thereby reducing the load on the device. It is an object of the present invention to provide a bus termination adjusting device and a bus termination adjusting method capable of reducing a leak current by connecting a high-resistance pull-down or pull-up resistor.

[0007]

According to the present invention, there is provided a bus termination adjusting apparatus for adjusting a bus termination circuit in a transmission circuit, wherein a control for connecting a termination resistor and a DC power supply only at the time of a waveform transition in a signal transmission state. Means is provided.

The present invention also relates to a bus termination adjusting device for adjusting a bus termination circuit in a transmission circuit, wherein a termination resistor is set in a state immediately after a transition to a standby state in which all devices connected to the bus transition to a reception waiting state. It is characterized by comprising control means for disconnecting from the DC power supply and switching to a pull-down resistor or a pull-up resistor having a low resistance value.

The present invention also relates to a bus termination adjusting device for adjusting a bus termination circuit in a transmission circuit, wherein all devices connected to the bus enter a reception waiting state, and when a standby state is established after a level is determined, a pull-down operation is performed. It is characterized by comprising control means for switching the resistance or pull-up resistance from low resistance to high resistance.

The present invention also relates to a bus termination adjusting device for adjusting a bus termination circuit in a transmission circuit, wherein a termination resistor and a DC power supply are connected only to a waveform transition in a signal transmission state and connected to the bus. In the state immediately after the transition to the standby state in which all of the connected devices have shifted to the reception waiting state, the terminating resistor is disconnected from the DC power supply and switched to a low-resistance pull-down resistor or pull-up resistor, and all devices connected to the bus receive. In a standby state after a transition to a waiting state and a level determination, a control means for switching the pull-down resistor or the pull-up resistor from a low resistance to a high resistance is provided.

Further, the bus termination adjusting device of the present invention
This will be described with reference to FIG.
A bus termination adjusting device (10) for adjusting the termination circuit of (9)
In 8), the terminating resistor (102) is connected to the DC power supply (103) only at the time of the waveform transition in the signal transmission state, and immediately after the transition to the standby state in which all the devices connected to the bus transition to the reception waiting state. , The terminating resistor is disconnected from the DC power supply, and a low-resistance pull-down resistor (10
4) Or switch to a pull-up resistor, and when all the devices connected to the bus enter a reception waiting state and are in a standby state after the level is determined, the pull-down resistor or the pull-up resistor is changed from a low resistance to a high resistance (106). Control means (101, 105, 107) for switching are provided.

[Operation] The bus termination adjusting device of the present invention installs a termination resistor on the bus and connects the termination resistor and the DC power supply only at the time of waveform transition. Therefore, it is possible to reduce the reflection noise and the power consumed by the terminating resistor. Further, when all devices on the bus are in a high impedance state, the level is quickly determined, thereby preventing a failure of a circuit connected to the bus. Further, after the level determination is completed, a pull-down resistor or a pull-up resistor having a high resistance value is electrically connected automatically. for that reason,
It is possible to reduce the leak current flowing into the input / output device connected to the bus and the leak current flowing out of the input / output device.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing the first and second embodiments of the present invention, the features and basic structure of the present invention will be described.

According to the present invention, when a signal is transmitted on a bus, a termination resistor is connected only at the time of a waveform transition using a signal such as a clock capable of recognizing a transition state of a transmission waveform as a trigger, thereby reducing reflection noise and power consumption. The first feature is to reduce the amount. In addition, the present invention disconnects the terminating resistor and immediately pulls down (or pulls down) a low resistance value when all devices connected to the bus shift to an electrical high impedance state immediately after shifting to a reception waiting state (standby state). A second feature is that the resistance is quickly settled to the L level (or the H level) by switching to the (up) resistor, thereby preventing the destruction of the device.

Further, according to the present invention, by switching the pull-down (or pull-up resistance) from a low resistance to a high resistance after a transition to the standby state and the level is determined, the leakage flowing into or out of the device can be achieved. The third feature is to reduce the current.

The bus termination automatic adjustment circuit according to the present invention comprises control circuits 101, 105, 10 as shown in FIG.
7, a termination resistor 102, a DC power supply 103, pull-down resistors 104 and 106, a control signal generation circuit 108, a bus 109, and a data input / output device 110. In the figure, reference numerals 111, 112 and 113 indicate control signals.

The control signal generation circuit 108
The control circuit 111 generates a control signal 111 generated by using a clock or a state signal capable of recording a transition state of a waveform as a trigger.
01, and only at the transition of the waveform in the signal transmission state, by connecting the terminating resistor 102, the reflection of the waveform is prevented,
In addition, the power consumption is reduced. At this time, the control signal 112 and the control signal 113 from the control signal generation circuit 108
Is transmitted, and the pull-down resistor 104 and the pull-down resistor 106 are electrically disconnected by the operation of the control circuit 105 and the control circuit 107 (first feature).

Immediately after shifting to the standby state,
A control signal 112 and a control signal 113 output from the control signal generation circuit 108 are transmitted, and the operation of the control circuit 105 and the control circuit 107 causes the pull-down resistor 104 having a low resistance value and the pull-down resistor 106 having a high resistance value to be electrically connected. By making the connection, the L level is quickly determined and the destruction of the device is prevented (second feature).

After a transition to the standby state and the level is determined, a control signal 112 from the control signal generation circuit 108 is transmitted, and the pull-down resistor 104 is electrically disconnected by the operation of the control circuit 105 to be connected to the bus. By using only the high-resistance pull-down resistor 106 as a resistor, leakage current flowing into or out of the device is reduced (third feature).

According to the present invention, according to the first to third features, an optimal termination circuit is formed in each of the signal transmission state, the state immediately after the transition to the standby state, and the standby state.

[First Embodiment] Next, a first embodiment of the present invention will be described in detail with reference to the drawings.

(1) Description of Configuration The automatic bus termination adjusting circuit according to the first embodiment of the present invention is shown in FIG.
As shown in the figure, the control circuits 201, 205, 20
7, a termination resistor 202, a DC power supply 203, pull-down resistors 204 and 206, a control signal generation circuit 208, a bus 209, and a data input / output device 210. Further, the control signal generating circuit 208 includes a differentiating circuit 215, a low-pass filter 217, an AND gate 218, an inverter gate 219, and a transistor 22.
0, 221. In the figure, 211, 212, 21
3 indicates a control signal, 214 indicates a clock input, and 216 indicates a state detection input.

According to the first embodiment of the present invention, in a bus configuration in which a plurality of data input / output devices 210 are connected to a bus 209, the bus 209 has three states: a signal transmission state, a state immediately after transition to standby, and a standby state. Divided into states,
The automatic adjustment is made to a termination circuit configuration suitable for each state.

The above configuration will be described in detail. In the differentiating circuit 215 of the control signal generating circuit 208, the clock input 21
4. Differentiate the clock input from 4. Next, the output of the differential signal output from the differentiating circuit 215 is controlled by the AND gate 218 of the control signal generating circuit 208 using the state signal input from the state detection input 216. As a result, the control signal 21
1 is output. The control circuit 201 controls the electrical connection between the terminating resistor 202 and the DC power supply 203 using the control signal 211.

In the low-pass filter 217 of the control signal generation circuit 208, the state signal waveform input from the state detection input 216 is blunted. The transistor 220 controls the output of the dull signal output by the low-pass filter 217 using a signal obtained by inverting the status signal input from the status detection input 216 by the inverter gate 219. In addition, the transistor 221 uses the state signal input from the state detection input 216 to change the output of the transistor 220 except for the state immediately after the transition to standby.
The state of the control signal 212 is controlled by fixing the signal to the L level. As a result, the control signal generation circuit 20
8, a control signal 212 is output. The control circuit 205 controls the electrical connection between the pull-down resistor 204 and the ground using the control signal 212.

Inverter gate 219 of control signal generation circuit 208 inverts the state signal input from state detection input 216 and outputs the inverted signal as control signal 213. The control circuit 207 controls the electrical connection between the pull-down resistor 206 and the ground using the control signal 213.

As the pull-down resistor 204, a resistor having a lower resistance value than the pull-down resistor 206 is used.

(2) Description of Operation Next, the operation of the first embodiment of the present invention will be described with reference to FIGS.
This will be described in detail with reference to FIG.

The automatic adjustment of the termination circuit configuration according to the state of the bus, which is a feature of the present invention, is performed by the control signal generation circuit 20.
8, control signal 212, control signal 2
In 13, this is realized by controlling the electrical connection between the terminating resistor 202, the pull-down resistor 204, the pull-down resistor 206 and the DC power supply 203 or the ground.

First, in the signal transmission state, the control circuit 201 is controlled by the control signal 211 output from the control signal generation circuit 208, so that the terminating resistor 202 and the DC power supply 203 are electrically intermittently connected. Further, the pull-down resistor 204 and the pull-down resistor 206
The control signal 205 and the control signal 213 output from the control signal generation circuit 208 are used to control the control circuit 205.
And the control circuit 207 is electrically disconnected from the ground.

The operation is shown in the time chart of FIG.
As shown in FIG. 3, the clock input from the clock input 214 is differentiated by the differentiating circuit 215 of the control signal generating circuit 208. The output of the differentiated signal output from the differentiating circuit 215 is controlled by the AND gate 218 of the control signal generating circuit 208 using the state detection signal input from the state detection input 216.

As shown in FIG. 3, in the signal transmission state, the state detection signal input from the state detection input 216 becomes H level, so that the differentiated signal is output to the control circuit 201 as the control signal 211. Control circuit 201
Is turned on for the time during which the control signal 211 is at the H level, and the terminal resistor 202 and the DC power supply 203 are electrically intermittently connected.

As shown in FIG. 3, in the signal transmission state, the state detection signal input from the state detection input 216 is transmitted to the inverter gate 21 of the control signal generation circuit 208.
When the control signal 213 generated by inverting in step 9 goes low, the control circuit 207 is turned off, and the pull-down resistor 206 is electrically disconnected from the ground.

Further, the transistor 221 is turned on by the state detection signal input from the state detection input 216, and the control signal 212 is set to L level. Control signal 212
Becomes L level, the control circuit 205
The state becomes the FF state, and the pull-up resistor 205 is also electrically disconnected from the ground.

Since the control signal 211 is generated by differentiating the clock input from the clock input 214, the control signal 211 has a pulse width of １ ／ or less of the clock cycle. Bus 209
Assuming that the transition of the signal waveform transmitted between the data input / output devices 210 connected to the terminal is performed in synchronization with the clock, the termination resistor 202 is connected to the DC power supply 203 only at the time of the transition of the signal waveform by the control signal 211. Will be done.

When a signal is transmitted between the data input / output devices 210, the signal reflection occurs at the transition of the signal waveform, so that a sufficient signal reflection countermeasure can be taken with this configuration. In addition, since the time during which the terminating resistor 202 is connected to the DC power supply 203 is equal to or less than の of the clock cycle, compared to the power consumption when the terminating resistor is always connected to the DC power supply, the configuration of the present invention reduces the power consumption. It is possible to reduce it to 1/2 or less.

Next, immediately after the transition to the standby state, the control signal 21 output from the control signal generation circuit 208 is used.
In step 1, by controlling the control circuit 201,
The terminating resistor 202 and the DC power supply 203 are electrically disconnected. The pull-down resistor 204 having a low resistance value controls the control signal generation circuit 208 immediately after the transition to the standby mode.
Control signal 212 output from the
05 is electrically connected to the ground.

When the pull-down resistor 204 is connected to the ground, the level of the bus 209 is quickly determined to the L level. The pull-down resistor 206 is a control signal 213 output from the control signal generation circuit 208,
By controlling the control circuit 207, it is electrically connected to the ground.

The operation is shown in the time chart of FIG.
As shown in FIG. 3, when the state detection signal input from the state detection input 216 becomes L level, the control signal 21
1 is fixed at the L level. When the control signal 211 becomes L level, the control circuit 201 is turned off, and the terminating resistor 202 and the DC power supply 203 are electrically disconnected.

The low-pass filter 217 of the control signal generation circuit 208 slows down the state detection signal input from the state detection input 216. This is shown in the output (217) of the low-pass filter in FIG. At the same time, the transistor 221 is turned off when the state detection signal input from the state detection input 216 becomes L level, and is electrically disconnected from the ground.

On the other hand, the transistor 220 is turned on by inputting a signal obtained by inverting the state detection signal input from the state detection input 216 by the inverter gate 219, and outputs the signal input from the low-pass filter 217 as the control signal 212. I do. The state is shown by control signal 2 in FIG.
FIG. In the control circuit 205, the control signal 2
The pull-down resistor 204 is electrically connected to the ground according to the waveform of FIG.

The inverter gate 219 of the control signal generation circuit 208 inverts the state detection signal input from the state detection input 216 and outputs the inverted signal as a control signal 213. As shown in FIG. 3, the control circuit 207 is turned on when the control signal 213 becomes H level, and electrically connects the pull-down resistor 206 to the ground.

When the data input / output device 210 shifts to a standby state in which all the data input / output devices 210 are in a high impedance state (a state immediately after the shift to the standby state), the bus 209 and the ground are temporarily connected via the pull-down resistor 204 having a low resistance value. In this way, the effect of discharging the electric charge stored in the bus is promoted, and the L level is quickly settled.
The load on the device can be reduced.

Finally, in the standby state, only the pull-up resistor 206 having a high resistance value is connected to the ground. In the standby state, as shown in FIG. 3, the control signal 213 output from the control signal generation circuit 208 is fixed at the H level, so that the control circuit 207 is turned on. As a result, the pull-down resistor 206
Electrically connected to ground.

As shown in FIG. 3, when the control signal 211 output from the control signal generation circuit 208 becomes L level as shown in FIG.
1 is turned off, the terminating resistor 202 and the DC power
3 are electrically disconnected.

The pull-down resistor 204 having a low resistance value is
As shown in FIG. 3, when the control signal 212 output from the control signal generation circuit 208 settles at the L level, the control circuit 205 is turned off and is electrically disconnected from the ground.

When all of the data input / output devices 210 connected to the bus 209 are in a high impedance state, only the pull-down resistor 206 having a high resistance value is enabled, and the data output from the data input / output device 210 is enabled. Leakage current can be minimized.

Second Embodiment Next, a second embodiment of the present invention will be described in detail with reference to the drawings.

(1) Description of Configuration The automatic bus termination adjusting circuit according to the second embodiment of the present invention is shown in FIG.
As shown in the figure, the control circuits 301, 305, 30
7, a termination resistor 302, a DC power supply 303, pull-down resistors 304 and 306, a control signal generation circuit 308, a bus 309, and a data input / output device 310. Further, the control signal generation circuit 308
LL (Delay Locked Loop) 15, counter 317, A
ND gates 318, 320, 323, inverter gates 319, 325, and a decoder 324 are provided. In the figure, 311, 312, and 313 indicate control signals, 316 indicates a state detection input, 321 indicates a base tone clock, and 322 indicates a 90-degree clock.

In the second embodiment of the present invention, in a bus configuration in which a plurality of data input / output devices 310 are connected to a bus 309, the status of the bus 309 is divided into a signal transmission status, a status immediately after transition to standby, and a standby status. Divided into states,
The automatic adjustment is made to a termination circuit configuration suitable for each state.

More specifically, the DLL 315 of the control signal generation circuit 308 uses the clock input 314
Based on the input clock, a base tone clock 321 and a 90-degree clock 322 are generated and output.

Next, the AND gate 323 of the control signal generation circuit 308 takes an AND logic by using the base clock 321 and a signal obtained by inverting the 90-degree clock 322 by the inverter gate 325, and controls the output of the AND gate 323. This is performed based on the state signal input from the state detection input 316. As a result, the control signal generation circuit 308
The control signal 311 is output. Control circuit 3
In 01, the control signal 311 is used to control the electrical connection between the terminating resistor 302 and the DC power supply 303.

The counter 317 of the control signal generation circuit 308 performs a count-up operation by the clock input 314 only when the state signal input from the state detection input 316 is at the L level, and inputs the value to the decoder 324. When the count value is '0' to '2', a signal which becomes H level is output.

The output of the signal output from the decoder 324 is controlled using the signal obtained by inverting the state signal input from the state detection input 316 by the inverter gate 319. As a result, the control signal generation circuit 308
As a result, a control signal 312 is output. The control circuit 305 uses the control signal 312 to control the pull-down resistor 3
The electrical connection between the terminal 04 and the ground is controlled.

An inverter gate 319 of the control signal generation circuit 308 inverts the state signal input from the state detection input 316 and outputs the inverted signal as a control signal 313. The control circuit 307 controls the electrical connection between the pull-down resistor 306 and the ground using the control signal 313.

As the pull-down resistor 304, a resistor having a lower resistance value than the pull-down resistor 306 is used.

(2) Description of Operation Next, the operation of the second embodiment of the present invention will be described with reference to FIGS.
This will be described in detail with reference to FIG.

The automatic adjustment of the termination circuit configuration based on the bus state, which is a feature of the present invention, is performed by the control signal generation circuit 30.
8, control signal 312, control signal 312
At 13, the control is realized by controlling the electrical connection between the terminating resistor 302, the pull-down resistor 304, the pull-down resistor 306 and the DC power supply 303 or the ground.

First, in the signal transmission state, the control circuit 301 is controlled by the control signal 311 output from the control signal generation circuit 308, so that the terminating resistor 302 and the DC power supply 303 are electrically intermittently connected. The pull-down resistor 304 and the pull-down resistor 306
The control signal 312 and the control signal 313 output from the control signal generation circuit 308 form the control circuit 305.
And the control circuit 307 is electrically disconnected from the ground.

The operation is shown in the time chart of FIG.
As shown in FIG. 5, based on the clock input from the clock input 314, the DL of the control signal
Keynote clock 321 and 90 degree clock 32 from L315
Output as 2. The 90-degree clock 322 output from the DLL 315 is inverted by the inverter gate 325, takes an AND logic at the base clock 321 and the AND gate 323, and outputs a Du to the clock input 314.
A ty25% signal is output, and the output is controlled as a control signal 311 in FIG. 5 by the AND gate 318 using the state detection signal input from the state detection input 316.

As shown in FIG. 5, in the signal transmission state, the state detection signal input from the state detection input 316 becomes H level, and is output from the AND gate 318 to the control circuit 301 as the control signal 311. The control circuit 301 is turned ON for the time during which the control signal 311 is at the H level, and electrically connects and disconnects the terminating resistor 302 and the DC power supply 303.

As shown in FIG. 5, in the signal transmission state, the state detection signal input from the state detection input 316 is applied to the inverter gate 31 of the control signal generation circuit 308.
9, the control signal 313 generated by inversion at L
Level, the control circuit 307 becomes O
The state becomes the FF state, and the pull-down resistor 306 is electrically disconnected from the ground.

The control signal 311 is obtained by ANDing the clock input from the clock input 314 with the base clock 321 and the 90-degree clock 322 by the AND gate 323. Become. Data input / output device 31 connected to bus 309
Assuming that the transition of the signal waveform transmitted between 0 is performed in synchronization with the clock, the terminating resistor 302 is connected to the DC power supply 303 only at the time of the transition of the signal waveform by the control signal 311.

When a signal is transmitted between the data input / output devices 310, signal reflection occurs at the time of transition of the signal waveform, so that a sufficient signal reflection countermeasure can be taken with this configuration. Further, since the time during which the terminating resistor 302 is connected to the DC power supply 303 is 1/4 or less of the clock cycle, the power consumption of the configuration of the present invention is 1 in comparison with the power consumption when the terminating resistor 302 is always connected to the DC power supply. / 8 or less.

Next, immediately after the transition to the standby state, the control signal 31 output from the control signal generation circuit 308 is used.
By controlling the control circuit 301 in step 1, the terminating resistor 302 and the DC power supply 303 are electrically disconnected. In the state immediately after the transition to the standby mode, the pull-down resistor 304 having a low resistance value is connected to the control signal generation circuit 308.
Control signal 312 output from the
05 is electrically connected to the ground.

When the pull-down resistor 304 is connected to the ground, the level of the bus 309 is quickly determined to the L level. The pull-down resistor 306 is a control signal 313 output from the control signal generation circuit 308,
By controlling the control circuit 307, it is electrically connected to the ground.

The operation is shown in the time chart of FIG.
As shown in FIG. 5, when the state detection signal input from the state detection input 316 becomes L level, the control signal 31
1 is fixed at the L level. When the control signal 311 becomes L level, the control circuit 301 is turned off, and the terminating resistor 302 and the DC power supply 303 are electrically disconnected.

In the counter 317 of the control signal generation circuit 308, the count-up operation is started by the clock input 314 only when the state detection signal input from the state detection input 316 is at the L level, and the count value becomes "0" to "2". '
A signal which becomes H level only at the time of is output from the decoder 324. This is shown in the waveform of the decoder (324) in FIG.

On the other hand, the AND gate 320 performs output control by inputting a signal obtained by inverting the state detection signal input from the state detection input 316 by the inverter gate 319, and outputs the signal output from the decoder 324 to the control signal 31.
Output as 2. This is shown by the control signal 312 in FIG. In the control circuit 305, the pull-down resistor 304 is electrically connected to the ground according to the waveform of the control signal 312.

The inverter gate 319 of the control signal generation circuit 308 inverts the state detection signal input from the state detection input 316 and outputs the inverted signal as a control signal 313. As shown in FIG. 5, the control circuit 307 is turned on when the control signal 313 becomes H level, and electrically connects the pull-down resistor 306 to the ground.

When the data input / output device 310 shifts to the standby state in which all the data input / output devices 310 are in the high impedance state (the state immediately after the shift to the standby state), the bus 309 and the ground are temporarily connected via the pull-down resistor 304 having a low resistance value. In this way, the effect of discharging the electric charge stored in the bus is promoted, and the L level is quickly settled.
The load on the device can be reduced.

Finally, in the standby state, only the pull-up resistor 306 having a high resistance value is connected to the ground. In the standby state, as shown in FIG. 5, the control signal 313 output from the control signal generation circuit 308 is fixed at the H level, so that the control circuit 307 is controlled.
Is turned on. As a result, the pull-down resistor 306
Are electrically connected to ground.

As shown in FIG. 5, when the control signal 311 output from the control signal generating circuit 308 becomes L level, the terminating resistor 302
1 is turned off, the terminating resistor 302 and the DC power supply 30
3 are electrically disconnected.

The pull-down resistor 304 having a low resistance value is
As shown in FIG. 5, by fixing the control signal 312 output from the control signal generation circuit 308 to L level, the control circuit 305 is turned off, and is electrically disconnected from the ground.

When all of the data input / output devices 310 connected to the bus 309 are in the high impedance state, only the pull-down resistor 306 having a high resistance value is enabled, and the data output from the data input / output device 310 is output. Leakage current can be minimized.

[0076]

As described above, according to the present invention,
By installing a terminating resistor on the bus and connecting the terminating resistor and the DC power supply only at the time of waveform transition, it is possible to reduce reflected noise and power consumed by the terminating resistor. Further, when all devices on the bus are in a high impedance state, the level is quickly determined, thereby preventing a failure of a circuit connected to the bus. Further, after the level determination is completed, a pull-down resistor or a pull-up resistor having a high resistance value is electrically automatically connected, so that a leak current flowing into the input / output device connected to the bus or a current flowing from the input / output device can be reduced. Outflow leak current can be reduced.

According to the present invention, an optimal termination circuit can be connected during signal transmission by automatically adjusting the termination circuit configuration in the signal transmission state and in other states.
In the signal transmission state, it is optimal to connect the terminating resistor with a DC power supply having a half of the signal amplitude. With this termination circuit configuration, the signal amplitude is not biased to either the H level or the L level, and a noise margin between the H level and the L level can be secured. On the other hand, in the standby state where the input / output devices do not transmit signals on the bus, it is necessary to determine the level to the H level or the L level in order to prevent device destruction. Therefore, the termination circuit configuration in the signal transmission state cannot be applied in the standby state. In the present invention,
This problem can be solved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a bus termination automatic adjustment circuit of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a bus termination automatic adjustment circuit according to the first embodiment of the present invention.

FIG. 3 is a timing chart showing various signal waveforms in the automatic bus termination adjusting circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a bus termination automatic adjustment circuit according to a second embodiment of the present invention.

FIG. 5 is a timing chart showing various signal waveforms in a bus termination automatic adjustment circuit according to a second embodiment of the present invention.

[Explanation of symbols]

101, 105, 107, 201, 205, 207, 3
01, 305, 307 Control circuit 102, 202, 302 Termination resistor 103, 203, 303 DC power supply 104, 106, 204, 206, 304, 306 Pull down resistor 108, 208, 308 Control signal generation circuit 109, 209, 309 Bus

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ideo No. 1-403 Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside of NEC Corporation (72) Inventor Kenji Shito Koichi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa No. 403, NEC Corporation (72) Inventor Masaki Sato 1-403, Kosugi-cho, Nakahara-ku, Nakazaki-ku, Kawasaki-shi, Kanagawa Prefecture Within NEC Telecom System Corporation (72) Inventor Kazuhiko Niizuma, Nakahara, Kawasaki-shi, Kanagawa 1-403 Kosugi-cho, Tokyo-ku Inside the NEC Telecom Systems Co., Ltd. (72) Inventor Akira Saito 1-403 Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa F-term (reference) 5B011 EA09 EB03 HH02 LL01 MA06 5J056 AA05 AA40 BB17 BB22 BB49 BB60 DD27 GG11 5K029 AA02 DD04 DD13 DD23 EE05 JJ08 5K046 AA01 BA07 BB05 CC14 CC22

Claims (6)

[Claims] 1. A bus termination adjusting device for adjusting a bus termination circuit in a transmission circuit, comprising a control means for connecting a termination resistor and a DC power supply only at the time of a waveform transition in a signal transmission state. Bus termination adjuster. 2. A bus termination adjusting device for adjusting a bus termination circuit in a transmission circuit, wherein a termination resistor is disconnected from a DC power supply in a state immediately after a transition to a standby state in which all devices connected to the bus transition to a reception wait state. And a control unit for switching to a pull-down resistor or a pull-up resistor having a low resistance value. 3. A bus termination adjusting device for adjusting a bus termination circuit in a transmission circuit, wherein all devices connected to the bus shift to a reception waiting state and a pull-down resistor or a pull-up is set in a standby state after a level is determined. A bus termination adjusting device comprising control means for switching a resistance from a low resistance to a high resistance. 4. A bus termination adjusting device for adjusting a termination circuit of a bus in a transmission circuit, wherein a termination resistor and a DC power supply are connected only at the time of a waveform transition in a signal transmission state, and a device connected to the bus is connected. In the state immediately after the transition to the standby state in which all of the devices have transitioned to the reception waiting state, the terminating resistor is disconnected from the DC power supply, switched to a low-resistance pull-down resistor or a pull-up resistor, and all devices connected to the bus transition to the reception waiting state. A bus termination adjusting device comprising: a control unit that switches the pull-down resistor or the pull-up resistor from a low resistance to a high resistance in a standby state after a level is determined. 5. A control signal generating means for generating a control signal such as a clock or a state signal capable of recognizing a transition state of the transmission waveform, wherein the control means only performs a waveform transition in the signal transmission state. The bus termination adjusting device according to any one of claims 1 to 4, wherein the termination resistor and the DC power supply are connected by using the control signal transmitted from the control signal generation unit as a trigger. 6. A bus termination adjusting method for adjusting a bus termination circuit in a transmission circuit, comprising: connecting a termination resistor and a DC power supply only at the time of a waveform transition in a signal transmission state; In the state immediately after the transition to the standby state in which all of the devices have transitioned to the reception waiting state, the terminating resistor is disconnected from the DC power supply, switched to a low-resistance pull-down resistor or a pull-up resistor, and all devices connected to the bus transition to the reception waiting state. A bus termination adjustment method, wherein the pull-down resistor or the pull-up resistor is switched from a low resistance to a high resistance in a standby state after a level is determined.