JP2002032324A - PCI bus device connection control method - Google Patents

Abstract

(57) Abstract: In an information processing system including a PCI bus, a combination of an on-board PCI bus and a PCI slot can be selected as required by a user while observing restrictions on the electrical load of the bus. Provide system. A device exceeding a maximum number of devices determined in advance by an operating frequency of a PCI bus is mounted,
It is connected to a PCI bus via a bus switch, and is connected to the PCI bus according to the implementation of a specific function device such as operating frequency and encryption processing.
Select a device and a PCI slot to connect to the PCI bus.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PCI (Peripheral Component Interface) which is an I / O bus that is standardly employed in personal computers and server systems.
rconnect (hereinafter abbreviated as PCI). Regarding a bus system, the number of PCI devices and the number of PCs are generally determined while observing electrical load constraints determined by the operating frequency of the PCI bus.
The present invention relates to a control system for selecting an I slot according to a user's needs and connecting the I slot to a PCI bus.

[0002]

2. Description of the Related Art In recent years, in an information processing apparatus such as a personal computer, as the arithmetic processing performance of a processor has been improved, the data transfer performance of an I / O bus has been improved.
There is a demand for higher system performance and higher reliability, such as the realization of a hot-swap function for adapter cards.

FIG. 3 shows a system configuration of a conventional server. In FIG. 3, a CPU 101 is connected to a system control unit 102 via a front side bus 100.
In a multiprocessor system having a plurality of CPUs, a plurality of CPUs are generally connected to the front side bus 100. The system control unit 102 is composed of one or a plurality of chips, and is connected via a main memory 103 and I / O system buses 123 and 124 to a PCI bus bridge (33 MHz) 102 and a PCI bus bridge (6
6MHz). In recent years, high-performance server systems often include not only a CPU but also a plurality of I / O buses. In this case, the system control unit 102 connects a plurality of high-speed I / O system buses 123 and 124. In general, a method of connecting a plurality of I / O bus bridges by using a possible configuration is adopted.

In the system shown in FIG. 3, a first PCI bus 110 operating at 33 MHz is mainly controlled by a PCI bus bridge (33 MHz) 104 and has four P buses.
It comprises CI slots 111, 112, 113, 114, an on-board PCI device 106 directly connected to the PCI bus 110 without going through a slot, and a basic I / O controller 107. Basic I / O controller 1
07 denotes a keyboard 131, a mouse 132, a hard disk drive (hereinafter abbreviated as HDD) 133, and a basic input / output firmware (Basic Input Output System: B)
And a peripheral I / O device at a low speed such as an IOS. Next, the second PCI bus 120 operating at 66 MHz
Are mainly controlled by a PCI bus bridge (66 MHz) 105 and are connected to two PCI slots 121 and 122.

In the conventional system shown in FIG. 3, when a user uses a PCI device other than the on-board PCI device 106, a P
A CI card is used by attaching it to one of the PCI slots. In that case, the first PCI bus 110 or the second PCI bus 1 may be used depending on the operable frequency of the PCI card.
20 and assign P to the PCI slot on each bus.
It is necessary to install a CI card. The types of PCI cards that a user can add to the system include a graphics card and a SCSI (Small Computer System Interface).
e) and other general-purpose PCI cards such as an external I / O connection interface card and a network interface card, and a specific-purpose PCI card having an encryption processing function and the like. The general operation of the system shown in FIG. 3 is the same as that generally known as a normal personal computer system or server system, and a detailed description thereof will be omitted here.

In the conventional example shown in FIG. 3, the first PCI bus 110 and the second PCI bus 120 differ in the number of PCI slots provided in the bus. The first PCI bus 110 has four PCI slots 111 and 11
2, 113, 114 and on-board PCI device 106
Are connected, the second PCI bus 120
Only connects the two PCI slots 121 and 122. This is the first PCI bus and the second PC
This is because there is a difference in the operating frequency of the I bus. That is, the maximum number of electrical loads that can be connected to the PCI bus is different at each PCI bus operating frequency in order to satisfy the timing specification defined in the PCI bus specification. Strictly speaking, the number of PCI devices and PCI slots that can be connected in accordance with the operating frequency of each PCI bus depends on the electrical model of the I / O buffer of the PCI bus bridges 104 and 105, the line length and board impedance of the PCI bus, and the PCI bus. It is necessary to perform transmission line waveform simulation using parameters such as the load capacitance of each signal pin of the slot, and to design each slot or PCI device so as to satisfy the operation timing specification defined in the PCI bus specification. . As a method for simply determining the suitability of the electrical load of the PCI bus by omitting such a complicated simulation, a method using the number of converted loads as described below is widely used by those skilled in the art. ing.

More specifically, the load of an on-board PCI device directly connected to the PCI bus is converted into one load (the load is a conversion unit for easily counting the electric load), and is converted via a PCI slot. When connecting to a PCI bus by installing a PCI card,
In this method, two loads are set in consideration of the slot load, and the total number of converted loads of the on-board PCI devices or PCI slots connected to the PCI bus is set to a certain value or less according to the operating frequency of the PCI bus. Table 1 and Table 2
The converted load number generally used in a computer system having a current PCI bus (hereinafter abbreviated as a PCI bus system) will be described with reference to FIG.

[0008]

[Table 1]

[0009]

[Table 2]

For example, the total number of converted loads of a PCI bus operating at 33 MHz is usually 10 loads or less.
PCI slot connectable to I bus and on-board PC
The number of I devices is six combinations as shown in Table 1. Similarly, the maximum value of the reduced load number of the PCI bus system operating at 66 MHz is 4 loads, and Table 2 shows combinations of the number of PCI slots and the number of connected on-board PCI devices that can be realized at that time. When designing a computer system having a PCI bus, the on-board PCI
In general, the number of devices and the number of PCI slots are selected, and then detailed packaging design is performed by the above-described transmission line waveform simulation or the like.

The specification of the bus operating specifications including the operating frequency of the PCI bus, the electrical load necessary for the mounting design, the timing margin, and the like described in the above conventional example are described in PCI Specia.
l Interest Group PCI Local Bus Specification Revi
sion 2.2 (issued December 18, 1998).

Next, a second conventional example having a PCI bus system having a hot-swap function of a PCI card will be described with reference to FIG. In FIG. 4, the PCI bus bridge 2
10 electrically connects the PCI slots 206 and 207 to the PCI slots.
It has a hot plug controller 202 for controlling insulation from the bus 203. The hot plug controller 202 controls the PCI slot disconnection control units 204 and 205 in accordance with an instruction of a user who uses the system or an application program.
06 and 207 are electrically disconnected from the PCI bus 203. Such electrical disconnection of the PCI slot
By making it possible to hot-swap a PCI card while the system unit is operating, it is possible to replace a failed PCI card, and in recent years it has been adopted mainly by high-end servers for the purpose of increasing the system operation rate. Is coming.
The operation of the other parts of FIG. 4 is the same as that of the first conventional example shown in FIG.

The hot-swap function of the PCI slot described in FIG. 4 is generally called a hot plug function, and its specification is described in PCI Special Interest Groove.
up issued PCI Hot-Plug Specification Revision
1.0 (issued October 6, 1997).

[0014]

By the way, as described in the prior art, the first PCI bus 110 and the second PCI bus 120 shown in FIG. 3 are connected to respective PCI buses. The number of PCI slots and onboard PCI devices are different. Specifically, four PCI slots 111, 112, 113, and 114, an on-board PCI device 106, and a basic I / O controller 107 are connected to the first PCI bus 110 in FIG. Only two PCI slots 121 and 122 are connected to the two PCI buses 120.
This is because the first P
The CI bus 110 operates at a frequency of 33 MHz, whereas the second PCI bus 120 operates at a frequency of 66 MHz. Therefore, the second PCI bus has stricter operational restrictions such as a timing margin of a PCI bus signal. is there.

Specifically, it is as follows. When a large number of PCI slots and on-board PCI devices are connected to the PCI bus, an electrical load such as a capacitive load of each slot or a signal pin of the device is connected to the PCI bus.
This leads to each signal line of the bus, and the device that drives the PCI bus needs to drive more electrical loads. Generally, TTL (Transistor-Transistor Logi)
c) When compared by the same bus drive method such as GTL (Gunning Transfer Logic), etc., when the electrical load increases, the rising waveform of each bus signal line deteriorates, and the bus operation timing specification can be satisfied. It becomes more difficult and the maximum operating frequency of the bus becomes lower. The same applies to the PCI bus, and when designing a PCI bus system, the PC
It is necessary to design so as to satisfy the electrical specifications and timing specifications described in the I bus specification (PCI Bus Specification Rev2.2). As described in the conventional example, for example, in a PCI bus system operating at 33 MHz,
Generally, a maximum of 5 PCI slots can be connected to the PCI bus.
It is said to be a slot, 66MHz operation PC
It is said that the I bus has a maximum of two slots. When this is converted by the on-board PCI device, 33
On-board PCI device 1
0 onboard PCI bus with 66MHz operation
This is equivalent to four devices.

As described above, the number of PCI devices connectable to the PCI bus differs depending on the respective operating frequencies, and the number of PCI devices connectable to the PCI bus depends on whether the device is a PCI slot or an on-board PCI device.
The number of CI devices is different.

Specifically, P operating at a maximum of 66 MHz
Taking a CI bus as an example, up to two PCI slots can be connected, and only two PCI devices can be used even when a PCI card is installed in each PCI slot.
Individual. On the other hand, up to four on-board PCI devices can be connected, so that up to four usable PCI devices can be used. However, when the PCI slot is adopted, the user can mount a PCI card having a necessary function according to the application. On the other hand, in the case of the on-board PCI device, the PCI device is connected to the board of the system device when the system is manufactured. Since it needs to be mounted on the upper part, the user cannot select the function of the PCI device according to the application.

As described above, in the conventional PCI bus system, when a PCI device is installed via a PCI slot, only half of the maximum number of PCI devices that can be connected according to the operating frequency of the PCI bus is limited. There was a problem that connection was not possible. Further, when an on-board PCI device is directly connected to a PCI bus on a system board without going through a PCI slot, there is a problem that a user cannot select a PCI device according to a required function. .

A first object of the present invention is to provide a PCI bus system having a PCI slot and an on-board PCI device, wherein the on-board PCI device and the PCI slot are flexibly mixed according to a function required by a user,
An object of the present invention is to enable a maximum number of connectable PCI device configurations according to the operating frequency of the PCI bus.

As a specification for increasing the operating frequency of the PCI bus, a high-speed operation specification of a PCI bus called a PCI-X bus has been defined mainly by Compa Corporation in the United States. The PCI-X bus uses the conventional P
While the CI bus operates at a maximum of 66 MHz, the maximum operating frequency is set to 133 MHz.
New PC with bus protocol change etc. to ease bus signal timing design conditions for CI-X devices
An I-bus specification, which is defined as a specification appendix (Addendum) to the conventional PCI bus specification. For details of the PCI-X bus specifications, see the PCI-X Addendum to the PCI Local B specification issued by the PCI Special Interest Group.
It is specified in detail in the us Specification (issued on September 22, 1999). Also, in the PCI-X bus specification, as in the conventional PCI bus specification, the P
The number of PCI-X devices that can be connected to the CI-X bus can be easily calculated by using the reduced load number. The method is the same as that of the PCI bus described in the conventional example, and is directly mounted on the system board.
The number of loads of the on-board PCI-X device connected to the CI-X bus is assumed to be one load, and the PCI-X slot is assumed to be two loads including the load of the PCI-X device on the attached PCI-X card. Tables 3, 4, and 5 show combinations of the main operating frequencies of the PCI-X bus specifications and the number of connectable on-board PCI-X devices and PCI-X slots.

[0021]

[Table 3]

[0022]

[Table 4]

[0023]

[Table 5]

As shown in Tables 3, 4 and 5, generally 66 MH
The maximum conversion load number of the PCI-X bus operating at z is 8 loads, 4 loads at 100 MHz operation, and 2 loads at 133 MHz operation.

The above-described PCI-X bus system has the following problems similarly to the conventional PCI bus. That is, the PCI-X slot
When an X device is mounted, the electrical load added to the PCI bus is twice as large as that of the on-board PCI-X device, so the maximum PCI that can be connected according to the operating frequency of the PCI-X bus There is a problem that only half of the number of PCI devices can be connected. Also, P
PCI on system board without going through CI-X slot
When the on-board PCI-X device is directly connected to the -X bus, there is a problem that the user cannot select the PCI-X device according to a required function.

A second object of the present invention is to provide a PCI-X slot having a PCI-X slot and an on-board PCI-X device.
In a bus system, a combination of the number of on-board PCI-X devices and the number of PCI-X slots can be selected according to a function required by a user.
An object of the present invention is to enable the configuration of the maximum number of connectable PCI devices according to the operating frequency of the bus.

Further, in the above-described PCI bus system, when an on-board PCI device or a PCI card having an encryption processing function is used, the following problem occurs.

That is, in the cryptographic processing system,
Generally, it is important to protect the confidentiality of the data to be processed for that purpose, but in particular, data related to cryptographic processing algorithms can be used to decrypt encrypted data, so confidentiality is maintained It is especially important. In the conventional system shown in FIG.
When a PCI card having a cryptographic processing function (hereinafter abbreviated as a cryptographic processing PCI card) is mounted in the slot 121, an analyzer card for analyzing a PCI bus signal is mounted in the PCI slot 122 to collect data on the PCI bus. It is possible to Since data flowing through the signal on the PCI bus is not encrypted, the PCI bus system equipped with a PCI card having an encryption processing function or an on-board PCI device has an empty P.
There is a problem in that data related to encryption processing can be collected from the CI slot, and confidentiality of data related to encryption processing cannot be maintained.

A third object of the present invention is to provide a PCI bus system having a PCI slot and an on-board PCI device, when a PCI card having an encryption function or an on-board PCI device is used, data related to encryption processing. Is to provide a means for maintaining confidentiality.

It should be understood by those skilled in the art that a system using the PCI-X bus has the same problem as in the PCI bus system regarding the security of the data for the above-described encryption processing.

A fourth object of the present invention is to provide a PCI-X slot having a PCI-X slot and an on-board PCI-X device.
In a bus system, a PCI-
An object of the present invention is to provide a means for maintaining the confidentiality of data related to cryptographic processing when using an X card or an on-board PCI-X device.

[0032]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides an arbitrary number of combinations of PCI slots and on-board PCI devices that can be connected in accordance with the operating frequency of a PCI bus. On-board PC
A PCI bus system having an I device and a PCI slot, wherein the on-board PCI device and
An electrical disconnecting means between the CI slot and the PCI bus, wherein a PCI device connection control means provided in a PCI bus bridge for controlling the PCI bus controls the electrical disconnecting means, so that the on-board P
The CI device and the PCI slot can be freely connected to the PCI bus. The above PCI
The device connection control means controls each of the above-mentioned electrical disconnecting means in accordance with system configuration information set in the basic input / output firmware of the system and hardware setting information of the system. Further PCI-X
The same control is performed in the bus system.

In order to solve the above-mentioned problems, the present invention provides an arbitrary number of on-board PCI devices and PCI devices.
A PCI bus system having a slot, wherein said on-board PCI device is electrically disconnected from said PCI slot and said PCI bus, and said PCI device is provided on a PCI bus bridge for controlling said PCI bus. A PC on an on-board PCI device or a PCI card mounted in the PCI slot.
When it is detected that the I device is a cryptographic processing device, the connection control means of the PCI device electrically disconnects the PCI slot where no PCI card is mounted from the PCI bus. Further P
The same control is performed in the CI-X bus system.

The present invention also relates to a system provided with an arbitrary number of PCI slots and on-board PCI devices. In a PCI device initialization work at the time of system startup, the number of PCI slots and PCI devices is determined based on the number of detected PCI slots and PCI devices. The number of electrical loads on each signal line is calculated as a converted load number, and the number of PCI slots and the number of on-board PCI devices are set so as not to exceed the maximum value of the converted load number predetermined by the operating frequency of the PCI bus. The combination is selected. More PC
The same control is performed in the IX bus system.

[0035]

Embodiments of the present invention will be specifically described with reference to the drawings. The present invention is not limited by the following description.

The configuration of the PCI bus system according to the first embodiment of the present invention will be described with reference to FIG. 1, and the operation procedure of the first embodiment will be described first with reference to FIG. In the PCI bus system of FIG. 1, parts corresponding to those of FIG. 3 will be described using the same symbols.

A feature of the present invention is that the PCI bus 160 operating at 66 MHz shown in FIG. 1 has the largest PCI device and P which can be connected to a normal PCI bus operating at 66 MHz.
More onboard PCI devices 142 and 143 and PCI slots 146 and 14 than the total number of CI slots
7 is connected, and the PCI device connection control unit 141
Controls the bus switches 152, 153, 156, and 157 so that the total number of the on-board PCI devices and the PCI slots is equal to or less than the maximum number of connections generally determined by the operating frequency of the PCI bus. is there. Specifically, when the converted load number of the electrical load number of the PCI bus described in the conventional example is obtained,
The total number of converted loads of the two PCI slots 146 and 147 and the two on-board PCI bus devices 142 and 143 is 6 loads, which is the maximum converted load of the conventional 66-MHz PCI bus shown in Table 2. More than 4 roads. The PCI bus connection control unit 141 controls the bus switch 1
52, 153, 156, 157 to control the PCI bus 1
By controlling the number of PCI slots and the number of on-board PCI devices electrically connected to the control unit 60, the total of the converted loads is reduced to 4 loads or less.

In FIG. 1, the PCI bus 160 is a PCI bus.
Mainly controlled by the bus bridge (66 MHz) 140, the two PCI slots 146 and 147 and the indicators 161 and 16 corresponding to the respective PCI slots
2 and two on-board PCI devices 142, 143
Are connected. Each PCI slot and onboard PC
The I device is provided with bus switches 152, 153, 156, and 157 as means for electrically disconnecting from the PCI bus. PCI device connection control unit 141
When the CPU 101 executes the firmware of the BIOS 134 and performs the initialization of the entire system in FIG.
The bus switches 152, 153, 156, and 157 are controlled, and the converted load number of the electrical load by the PCI device connected to the PCI bus 160 is 4 loads or less, which is the maximum value when operating at 66 MHz, which is the bus operating frequency. The connection control of each PCI slot or on-board PCI device is performed so that At this time, the system configuration information 135 stored in the BIOS 134 is referred to as to which PCI slot or on-board PCI device is to be disconnected. The PCI device connection control unit 141
Controls the indicators 161 and 162 when the connection control of the PCI device is performed, and notifies the user of the slot which is electrically disconnected and invalidated. The operation of the other parts of FIG. 1 is the same as that of the conventional example described with reference to FIG. 3, and therefore detailed description is omitted here.

Next, the operation of the first embodiment of the present invention shown in FIG. 1 will be described with reference to the flowchart shown in FIG. First, when the system is started, an initialization operation of the entire system is started (step 101), and the CPU 101 executes the BIOS program 134, and stores the stored system configuration information 1
35 is referred to (step 102). Next, the first PCI
A device connected to the bus 110 is detected (step 103), and initialization is performed (step 104). P
The CI bus device detection method can be executed by reading the contents of the configuration space of each device,
The device initialization is also performed by setting registers in the configuration space. The details of the detection and initialization work of the PCI device are the same as those of the PCI bus of the conventional generally adopted personal computer system.
Those skilled in the art can easily understand by referring to ication Rev2.2, so that detailed description is omitted here. Subsequently, a PCI device connected to the second PCI bus 160 is detected (step 105). It is determined whether a PCI device is detected (step 106). If the on-board PCI devices 142 and 143 are mounted,
If the PCI devices on the PCI card are mounted via the PCI slots 146 and 147, the electrical load of the PCI bus is calculated as the converted load number in accordance with the respective numbers (step 107). Next, a PCI slot or an on-board PCI device to be disconnected from the PCI bus 160 is determined based on the system configuration information 135 read out in step 102. In this case, the calculated load number of the on-board PCI device calculated above is taken into consideration. Then, the combination of the number of the PCI slots and the number of on-board PCI devices is selected so as not to exceed the maximum value of 4 electrical conversion loads of the PCI bus 160. Specifically, the PCI bus 160 operating at 66 MHz corresponds to item 2 in Table 2, and when connecting two on-board PCI devices, only one PCI slot can be connected. Therefore, when using the on-board PCI devices 142 and 143 according to the setting contents of the system configuration information 135, the PCI slot 1
Since it is necessary to electrically separate the book, which PCI slot is to be disconnected is determined (step 109), and one of the bus switches 152 and 153 is controlled to electrically disconnect one of the PCI slots 146 and 147 (step 109). 209). Since the electrically disconnected slot becomes unusable, the indicator 161 or 162 corresponding to the PCI slot concerned is controlled to notify the user of invalidation of the unusable slot. The notification by the indicator may light the indicator of the available PCI slot, or may light the indicator corresponding to the disabled PCI slot. Alternatively, the lighting color of the indicator may be changed (step 110).
If the on-board PCI devices 142 and 143 are not mounted on the system board, the two PCs
Since the I slots 146 and 147 can be connected, a valid slot may be notified by an indicator (step 111). Subsequently, an operation of initializing valid PCI devices connected to the PCI bus 160 (step 112) is performed so that the contents of the initialization operation of each PCI device performed in the last step 112 are consistent. By performing the setting of the PCI bus bridge 140 (step 113), the initialization of the second PCI bus 160 is completed.

According to the first embodiment of the present invention described above, the PCI devices and the PCI slots exceed the total number of the maximum connectable PCI devices and the PCI slots generally determined by the operating frequency of the PCI bus. And the PC according to the system configuration information.
I-devices and PCI slots can be electrically connected or isolated to the PCI bus in any combination. At this time, the electrical load of the bus signal line of the PCI bus is calculated as the converted load number from the number of connected PCI devices and PCI slots, and the calculated load is always greater than the maximum value of the converted load number determined by the operating frequency of the PCI bus. So that the PCI device and the PCI slot
Control the electrical connection to the bus. From the above, P
According to the operating frequency of the CI bus, a combination of an on-board PCI device and a PCI slot can be selected as necessary and used by connecting to the PCI bus.

The setting means of the system configuration information 135 described in the first embodiment shown in FIG. 1 is not limited to the method of storing the information in the BIOS 134, but may be realized by hardware setting means such as a dip switch or a jumper pin. Means for notifying the basic I / O controller may be used.

Also, the on-board PCI device 142 and the on-board PCI device 143 shown in FIG. 1 are mounted as devices having the same function, and the PCI device connection control unit 141 controls the bus switches 142 and 143 so that one of them is connected. It is always connected to the PCI bus 160 and the other is always disconnected, and when the always connected PCI device fails, the bus switch is controlled to disconnect the device from the PCI bus, and the other device that has been always disconnected is disconnected. PCI
The control as a backup device may be performed by connecting to a bus.

Further, the PCI bus connection control section 141 shown in FIG. 1 may be controlled by using the hot plug controller 202 shown in FIG.

Next, as a second embodiment of the present invention, FIG. 5 shows a case where a PCI-X bus which is an additional specification enabling a higher-speed operation of the PCI bus described in the first embodiment is used. This will be described with reference to FIG. In FIG. 5, the CPU and the front side bus are the same as those in the first embodiment shown in FIG. 1, and thus are omitted, and the system operation of the system control unit 102 and thereafter will be described. In FIG. 5, a PCI-X bus 601 is mainly controlled by a PCI-X bridge 609 and includes four on-board PCI-X devices 602 and 6.
03,604,605 and 2 PCI-X slots 6
06,607. As in the first embodiment, each on-board PCI-X device and PCI-X slot is connected to a bus switch 152, 153, 154, 155, 156, 1
57 to the PCI-X bus 601 and
The CI-X device connection control unit 610 controls each bus switch, so that any on-board PCI-X device and PCI-X slot can be assigned to the PCI-X bus 601.
And can be electrically disconnected or connected to it. The PCI-X device connection control unit 610 controls the corresponding indicators 161 and 162 according to the control state of the bus switches 156 and 157, and notifies the user of the connection status of the PCI-X slots 606 and 607, respectively.

In FIG. 5, the operating frequency of the PCI-X bus 601 is 100 MHz, and as shown in FIG.
On-board PCI-X connectable to CI-X bus 601
The number of devices and the number of PCI-X slots are a maximum of four converted loads as described in the conventional example. The PCI-X bus 601 already has two PCI-X slots 606 and 607 respectively.
57, the converted load number of the PCI-X slot is 4 loads in total.
The converted load total number at the time of MHz operation has been reached. On the other hand, the PCI-X bus 601 has four on-board PCI-X buses.
Since the devices 602, 603, 604, and 605 are connected via the bus switches, the reduced load numbers of these devices are 4 in total. The simple total of the converted loads of all the PCI-X slots and the on-board PCI-X devices is 8 loads, which exceeds the total converted loads at the time of 100 MHz operation shown in Table 4. In order to solve this problem, in the second embodiment of the present invention shown in FIG. 5, the PCI-X bus system is initialized as follows. The initialization procedure is the same as the PCI bus system initialization procedure of the first embodiment described with reference to the flowchart of FIG. That is, step 105 in the flowchart of FIG.
Performs device detection of the PCI-X bus 601 at
The following steps 107, 108, 109, and 110 are executed to control the PCI-X device connection so that the PCI-X bus 601 satisfies 4 loads, which is the reduced number of loads that can be logically operated when operating at 100 MHz. The unit 610 is provided with the bus switches 152, 153, 154, 155, 1
56, 157 to control each PCI-X device and on-board PCI-X device by the PCI-X bus 601.
Electrical connection or insulation. Specifically, based on the system configuration information 135, three types of on-board PCI-X devices and PCI-
Any one of the combinations of the number of X slots may be selected.
Then, in step 112, an operation of initializing a valid PCI-X device is performed. The operation of the other parts shown in FIG. 5 is the same as that of the first embodiment shown in FIG. 1, and therefore detailed description is omitted.

According to the above-described second embodiment of the present invention, the PCI-X bus exceeds the total number of PCI-X devices and PCI-X slots that can be connected and is generally determined by the operating frequency of the PCI-X bus. X device and PC
The I-X slot can be mounted on the system, and the PCI device and the PCI slot can be electrically connected or insulated to the PCI bus in a free configuration according to system configuration information. Further, at this time, the electrical load of the bus signal line of the PCI bus is calculated as a converted load from the number of connected PCI-X devices and PCI-X slots, and the converted load of the converted load determined by the operating frequency of the PCI-X bus is always calculated. The electrical connection of the PCI device and the PCI slot to the PCI bus is controlled so as not to exceed the maximum number. From the above, the combination of the on-board PCI-X device and the PCI-X slot is selected as necessary according to the operating frequency of the PCI-X bus, and the PCI-X
It can be used by connecting to a bus.

The setting means of the system configuration information 135 described in the first embodiment shown in FIG. 1 is not limited to the method of storing the information in the BIOS 134, but may be realized by hardware setting means such as a dip switch or a jumper pin. Means for notifying the basic I / O controller may be used.

Also, at least two of the on-board PCI-X devices 602, 603, 604, and 605 shown in FIG.
The CI-X device connection control unit 610 switches the bus switch 15
2, 153, 154, and 155, one is always connected to the PCI-X bus 601 and the other is always disconnected, and the bus switch is used when the always-connected PCI-X device fails. To disconnect the device from the PCI-X bus, and disconnect the other device that has always been disconnected from the PCI-X bus.
The connection to the X bus may be controlled as a backup device.

The PCI-X device connection control unit 610 shown in FIG. 5 may be controlled by using the hot plug controller 202 shown in FIG.

Next, as a third embodiment of the present invention, 133
A case where a PCI-X bus operating at MHz is used will be described with reference to FIG. In FIG. 6, the CPU and the front side bus are the same as those in the first embodiment shown in FIG. 1, and therefore are omitted, and the system operation of the system control unit 102 and thereafter will be described. In FIG. 6, a PCI-X bus 601 is mainly controlled by a PCI-X bridge 609 and operates at 133 MHz. The PCI-X bus 60
1 has two on-board PCI-X devices 602, 6
03 and one PCI-X slot 606.
As in the first embodiment, each on-board PCI-X device and PCI-X slot are connected to a bus switch 152, 153,
156 and a PCI-X bus 601,
The PCI-X device connection control unit 610 controls each bus switch, so that any on-board PCI-X devices 602 and 603 and a PCI-X slot 606 are electrically insulated or connected to the PCI-X bus 601. You can do it. The PCI-X device connection control unit 610
Controls the corresponding indicator 161 in accordance with the control state of the bus switch 156 to control the PCI-X slot 606
Notify the user of the connection status.

In FIG. 6, since the operating frequency of the PCI-X bus 601 is 133 MHz, the PCI-X bus 6
01 and the number of on-board PCI-X devices that can be connected to
As shown in Table 5, the number of CI-X slots is a maximum of two converted loads. The PCI-X bus 601 already has one PCI-X slot 606 for the bus switch 156.
, The converted load number of the PCI-X slot is 2 loads, and reaches the total converted load number at the time of 133 MHz operation shown in Table 5. Meanwhile, the PCI-
Since two on-board PCI-X devices 602 and 603 are connected to the X bus 601 via the bus switches, the converted load number is two. The simple sum of the converted loads of all the PCI-X slots and the onboard PCI-X devices described above is 4 loads, and Table 5
Exceeds the total number of converted loads during 133 MHz operation. The PCI-X bus system initialization procedure of the third embodiment shown in FIG. 6 is the same as the PCI bus system initialization procedure of the first embodiment shown in the flowchart of FIG. That is, the device of the PCI-X bus is detected in step 105 of the flowchart of FIG.
When the I-X bus 601 operates at 133 MHz, the PCI-X device connection control unit 610 controls the bus switches 152, 153, and 156 so as to satisfy 2 loads, which is the reduced number of loads that can be logically operated. Each PCI-X device and on-board PCI-X device
-It may be electrically connected to or insulated from the X bus 601. Specifically, one of the two combinations of the on-board PCI-X device and the number of PCI-X slots shown in Table 5 may be selected based on the system configuration information 135. Then, in step 112, each PC
Initialize the IX device. The operation of the other parts shown in FIG. 6 is the same as that of the first embodiment shown in FIG. 1, and therefore detailed description is omitted.

Further, as a fourth embodiment of the present invention, 10
PCI-X bus operating at 0 MHz and on-board PCI
A case where a cryptographic processing device is used as the -X device will be described with reference to the flowcharts of FIGS. 7 and 8.
In FIG. 7, the CPU and the front side bus are shown in FIG.
The description is omitted because it is the same as the first embodiment shown in FIG. In FIG. 7, a PCI-X bus 6 operating at 100 MHz
01 is mainly controlled by the PCI-X bridge 609 and is controlled by two on-board cryptographic processing devices 402 and 40.
3 and one PCI-X slot 606.
The on-board cryptographic processing devices 402 and 403 are on-board PCI-X devices each having a cryptographic processing function, and it is possible to select whether or not the device is mounted on a system board at the time of board manufacture. Each on-board cryptographic processing device and PCI
The -X slot is connected to the PCI-X bus 601 via the bus switches 152, 153 and 156, and the PCI-
The X device connection control unit 610 controls each bus switch, so that any on-board cryptographic processing device 60 can be controlled.
2, 603, and a PCI-X slot 606
It can be electrically insulated or connected to the IX bus 601. The PCI-X device connection control unit 610 includes:
Indicator 1 according to the control state of the bus switch 156
61 to notify the user of the connection status of the corresponding PCI-X slot 606 to the PCI-X bus 601.

In FIG. 7, since the operating frequency of the PCI-X bus 601 is 100 MHz, the PCI-X bus 6
01 and the number of on-board cryptographic processing devices connectable to PC 01
The number of IX slots is the same as that described in the second embodiment of the present invention, and as shown in Table 5, the maximum number of converted loads is four. Since one PCI-X slot 606 is connected to the PCI-X bus 601 via the bus switch 156, the converted load number of the PCI-X slot is two. On the other hand, the PCI-X bus 6
01 has two on-board cryptographic processing devices 602, 6
03 are connected via the bus switch, the converted load number when the two on-board cryptographic processing devices are mounted on the system board is two. Since the simple total of the reduced loads of all the PCI-X slots and the on-board cryptographic processing devices described above is 4 loads, regardless of whether or not the on-board cryptographic processing devices are mounted on the system board, Table 5 100M shown
It falls within the total number of converted loads during the Hz operation. In this embodiment, when the on-board cryptographic processing device is mounted on a system board, the on-board cryptographic processing device
The following processing is performed to maintain the confidentiality of data related to cryptographic processing that is input and output through the CI-X bus 601. That is, when an on-board cryptographic processing device is detected when the entire system device is activated, the PCI-X
The slot 606 is electrically disconnected so that data on the PCI-X bus 601 cannot be monitored from the PCI-X slot 606. Specifically, initialization of the PCI-X bus system is performed according to the procedure of the flowchart shown in FIG.

The procedure for initializing the PCI-X bus system according to the fourth embodiment shown in FIG. 7 will be described with reference to the flowchart shown in FIG. From step 301 in the flowchart of FIG.
Initialization of the CI-X bus is started, and in step 302, first, all PCI-X devices connected to the PCI-X bus 601, that is, the PCI-X slot 60
6, the presence or absence of a PCI-X device on a PCI-X card that can be attached to
The presence or absence of mounting on the system board 2403 is detected. The detection of the PCI-X device can be performed by reading the device ID data in the configuration space of the PCI-X device in the same manner as in the above-described first embodiment of the present invention. PCI
Local Bus Specification Rev2.2 and PCI-X Addendum
Since the PCI Local Bus Specification is described, detailed description is omitted here. Hereinafter, the detailed operations of the PCI bus and the PCI-X bus which are not related to the gist of the present invention will be omitted. Step 303
When it is determined that there is a PCI-X device,
In step 304, a device ID is obtained. Subsequently, the PCI-X bus 601 is obtained by using the acquired device ID.
(Step 305), and repeats the above steps until all the PCI-X slots on the system board and the on-board PCI-X devices are detected (step 30).
6). Next, ID information and BIO of the created device map
Encryption processing device configuration information 401 stored in S134
Then, the presence or absence of the cryptographic processing device in the detected PCI-X device is determined using the above. In the fourth embodiment shown in FIG. 7, since the on-board PCI-X device is a cryptographic processing device, the PCI-X device connection control unit 610 controls the bus switch 156 to change the PCI-X slot 60.
6 is electrically disconnected from the PCI-X bus 601.
At the same time, the PCI-X device connection control unit 610 controls the indicator 161 to provide the user with the PCI-X slot 60.
6 is invalidated. If the cryptographic processing device is not mounted due to an option selection at the time of manufacturing the system, the process proceeds from step 308 to step 311,
The initialization of the PCI bus device is continued.

According to the above-described fourth embodiment of the present invention, when it is detected that the on-board cryptographic processing device is mounted at the time of initializing the PCI-X bus, the PCI-X bus is detected. Since the PCI-X slot on the bus is electrically disconnected from the PCI-X bus and is invalidated, it is possible to prevent encryption-related data input / output by the on-board cryptographic processing device from being monitored from the PCI-X slot. I can do it.

As a fifth embodiment of the present invention, 66
A case in which a PCI-X bus operating at MHz and a plurality of PCI-X slots are provided will be described with reference to the flowcharts of FIGS. 9 and 10. Further, in FIG. 9, the CPU and the front side bus are the same as those in the first embodiment shown in FIG. 1, and therefore are omitted, and the system operation of the system control unit 102 and thereafter will be described. In FIG. 9, a PCI-X bus 601 operating at 66 MHz is connected to a PCI-X bridge 60.
9 mainly controlled by four PCI-X slots 6
06, 607, 612, and 613. The PCI
-X slots are bus switches 156,157,152,
The PCI-X bus 601 is connected to the PCI-X bus 601 via a bus 153, and a PCI-X device connection control unit 610 controls each bus switch, so that an arbitrary PCI-X slot is electrically connected to the PCI-X bus 601. Can be electrically insulated or connected. The PCI-X device connection control unit 6
10 is a bus switch 152, 153, 156, 157
Indicators 161, 162, 61 according to the control state of
4,615 to notify the user of the connection status of the corresponding PCI-X slot to the PCI-X bus 601.

In this embodiment, any of the PCI-
An operation in the case where a PCI card having a PCI device having a cryptographic processing function mounted in the X slot is mounted will be described. When a PCI-X device having a cryptographic processing function is connected to the PCI-X bus as in the above-described fourth embodiment of the present invention, the other PCI-X slots are invalidated and empty PCI-X slots are set. , So that data on the PCI-X bus 601 cannot be monitored.

The operation of the embodiment shown in FIG. 9 will be specifically described with reference to the flowchart shown in FIG. Step 4
At 01, device initialization work of the PCI-X bus 601 is started. First, the PC on each PCI-X slot
The presence or absence of the IX card is detected (step 402),
If a PCI-X device is mounted (step 403), a device ID is obtained (step 40).
4). Using the acquired device IDs, a device map of the PCI-X device corresponding to the PCI-X bus 601 is created (step 405), and all the PCI-X devices are created.
The above detection operation is repeated until a slot is detected (step 406). Then, referring to each device ID information on the created device map and the encryption device ID information 401 stored in the BIOS 134 (step 4).
07), it is determined whether the detected PCI-X device is a PCI-X device having an encryption processing function (step 408). When an encryption-processed PCI-X device is detected (step 408), the PCI-X device connection control unit sets an empty PCI slot in which no PCI-X device is mounted by referring to the created device map. By controlling, the PCI-
It is electrically disconnected from the X bus 601 and invalidated (step 409). Thereafter, the PCI-X device connection control unit 610 displays the indicators 161, 162, 613, 61
4 is notified to the user of the invalidated PCI-X slot (step 410).

According to the fifth embodiment of the present invention described above, a PCI-X device having a cryptographic function is connected to the PCI-X bus via the PCI-X slot at the time of initialization of the PCI-X bus. When the connection is detected, the empty PCI-X slot on the PCI-X bus is electrically disconnected from the PCI-X bus and invalidated, so that the PCI-X having the cryptographic processing function is invalidated. This prevents the device from being monitored from the PCI-X slot for encryption-related data that is input / output using the PCI-X bus.

The above-described fifth embodiment of the present invention is not limited to the PCI-X bus system.
Similar control can be performed in a conventional PCI bus system. In that case, the number of PCI slots may be selected according to the operating frequency of the PCI bus so as to satisfy the operation timing specification and the electrical specification.

Further, when the fifth embodiment of the present invention is configured by using a PCI bus, the PCI slot
It is physically possible to mount an X card or connect an on-board PCI-X bus device. In that case, the PCI-X bus device operates as a conventional PCI device.
What is necessary is just to perform control in an I bus.

[0062]

As an effect of the present invention, in a PCI bus system having an arbitrary number of on-board PCI devices and an arbitrary number of PCI slots, the maximum electric load determined according to the operating frequency of the PCI bus system is maximized. It is possible to control the number of electrical connections of the arbitrary number of on-board PCI devices and PCI slots to the PCI bus so as not to exceed the value. This makes it possible to flexibly select a necessary PCI device according to a bus user's request and to satisfy an electrical constraint condition required for an operating frequency. In addition, a similar effect can be obtained with PCI-
It can also be obtained in the X bus system.

Another advantage of the present invention is that on-board PCI devices and PCI slots can be mounted on the system board exceeding the maximum number of loads determined by the operating frequency of the PCI bus, and the maximum load can be increased as necessary. The device can be selected and used within the range not exceeding. Thereby, for example, the on-board PCI device and the PC
The I-slot is mounted, and a backup PCI device is mounted in advance by disconnecting the connection from the PCI bus, and when the on-board PCI device fails, the failed device is electrically disconnected from the PCI bus. By electrically connecting the backup device, the backup device can be operated alternately while observing the electrical load restrictions of the PCI bus. As a result, it is possible to contribute to shortening the time required for functional recovery when a failure occurs, which is important in a server device or the like. A similar effect can be obtained in the PCI-X bus system.

Another advantage of the present invention is that when the confidentiality of data input / output by a device such as a cryptographic processing device is important, a PCI bus having a PCI device having a cryptographic processing function and not using a PCI bus is not used. Since the slot can be electrically disconnected and invalidated, data related to encryption processing input / output by the PCI device having the encryption processing function from the unused PCI slot is not monitored.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a PCI bus system according to a first embodiment.

FIG. 2 is a flowchart showing the operation of the first embodiment.

FIG. 3 is a block diagram showing a PCI bus system according to the related art.

FIG. 4 is a block diagram showing a PCI hot plug function according to the related art.

FIG. 5 is an exemplary block diagram showing a PCI-X bus system according to a second embodiment;

FIG. 6 is an exemplary block diagram showing a PCI-X bus system according to a third embodiment;

FIG. 7 is a block diagram showing a PCI-X bus system according to a fourth embodiment;

FIG. 8 is a flowchart showing the operation of the fourth embodiment.

FIG. 9 is a block diagram showing a PCI-X bus system according to a fifth embodiment.

FIG. 10 is a flowchart showing the operation of the fifth embodiment.

[Explanation of symbols]

100: front side bus, 101: CPU, 102
... system control unit, 103 ... main memory, 104, 105
... PCI bus bridge, 106 ... Onboard PCI device, 107 ... Basic I / O controller, 110 ... First PCI bus, 111-114 ... P of first PCI bus
CI slot, 120... Second PCI bus, 121, 1
22... PCI slot of the second PCI bus, 123, 1
24 ... I / O system bus, 131 ... Keyboard, 13
2 mouse, 133 HDD, 134 BIOS, 13
5 ... System configuration information, 140 ... PCI bridge (66
MHz), 141 ... PCI device connection control unit, 14
2,143 ... On-board PCI device, 146,14
7 PCI slot, 152-157 bus switch,
160 ... PCI bus, 161, 162 ... indicator,
201: PCI bus bridge, 202: Hot plug controller, 204, 205: PCI slot cutting section,
206, 207: PCI slot, 601: PCI-X
Bus, 602 to 605: On-board PCI-X device, 606, 607: PCI-X slot, 609: P
CI-X bus bridge, 610: PCI-X device connection control unit, 612, 613: PCI-X slot.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Nobuo Matsuoka 1st Horiyamashita, Hadano-shi, Kanagawa F-term in Enterprise Server Division, Hitachi Ltd. 5B014 EA01 GA13 GA25 GE02 HA05 HA13 5B061 FF01

Claims (33)

[Claims] 1. An arbitrary number of PCI slots, comprising at least one PCI bus, an arbitrary number of PCI slots, and an arbitrary number of PCI devices connected to the PCI bus without passing through the PCI slots. And the arbitrary number of PCI devices are connected to the PCI bus via devices that can be electrically connected or disconnected.
In the bus system, the PCI slot and the PC
Connecting the PCI device and the PCI slot to the PCI bus by controlling the device that can be electrically connected or disconnected so that the total of the electrical load capacities of the I devices is always equal to or less than a fixed value. Characteristic P
CI device connection control method. 2. The PCI bus and PC according to claim 1,
The I device and the PCI slot are PCI-X
A PCI device connection control method comprising a bus, a PCI-X device, and a PCI-X slot. 3. A PCI device connection control system according to claim 1, wherein the device capable of electrically connecting or disconnecting is configured by a bus switch. 4. At least one PCI bus, an arbitrary number of PCI slots, and a PCI device connected to the PCI bus without passing through an arbitrary number of PCI slots, wherein the PCI device and the PCI slot are electrically connected. The PCI through a device that can be connected or disconnected
A PCI bus system connected to a bus, wherein the sum of the number of the PCI slots electrically connected to the PCI bus and a value obtained by doubling the number of the PCI devices is always predetermined. The PCI device and the PCI slot are controlled by controlling the device that can be electrically connected or disconnected so as to be equal to or less than a predetermined value.
A PCI device connection control method characterized by connecting to a bus. 5. A PCI bus operating in at least one 66 MHz mode, an arbitrary number of PCI slots,
An arbitrary number of PCI devices connected to the PCI bus without passing through a CI slot;
The device and the arbitrary number of PCI slots are connected to the PCI slot via a device that can be electrically connected or disconnected.
A PCI bus system connected to a bus, wherein the sum of the number of the PCI slots electrically connected to the PCI bus and a value obtained by doubling the number of the PCI devices is always predetermined. The PCI device and the PCI slot are controlled by controlling the device that can be electrically connected or disconnected so as to be equal to or less than a predetermined value.
A PCI device connection control method characterized by connecting to a bus. 6. The PCI bus or PC according to claim 4, wherein
The I device and the PCI slot are PCI-X
A PCI device connection control system that is a bus, a PCI-X device, and a PCI-X slot. 7. The PCI bus, PC according to claim 5,
The I device and the PCI slot are PCI-X
A PCI device connection control system that is a bus, a PCI-X device, and a PCI-X slot. 8. A PCI device connection control method according to claim 4, wherein said device capable of electrically connecting or disconnecting is configured by a bus switch. 9. A PCI device connection control system according to claim 6, wherein said electrically connectable or disconnectable device is a bus switch. 10. At least one PCI bus, an arbitrary number of PCI slots, and a PCI device connected to the PCI bus without passing through an arbitrary number of PCI slots, wherein the PCI device and the PCI slot are electrically connected. The PCI through a device that can be connected or disconnected
Connected to a bus, the number of the PCI devices,
A PCI bus system in which the sum of a value obtained by doubling the number of the PCI slots is greater than 10, wherein the number of the PCI slots electrically connected to the PCI bus is twice the number of the PCI devices. A PCI device connection control system, wherein the PCI device and the PCI slot are connected to the PCI bus by controlling the device that can be electrically connected or disconnected so that the sum of the values is always 10 or less. 11. The PCI device, comprising: at least one PCI bus operating in a 66 MHz mode; an arbitrary number of PCI slots; and a PCI device connected to the PCI bus without passing through an arbitrary number of PCI slots. And the PCI slot is connected to the PCI bus via a device that can be electrically connected or disconnected, and the sum of the number of the PCI devices and a value obtained by doubling the number of the PCI slots is greater than 4. A PCI bus system, wherein the number of the PCI slots electrically connected to the PCI bus and a value obtained by doubling the number of the PCI devices are always four or less. Or a PCI that controls a device capable of shutting off and connects the PCI device and a PCI slot to the PCI bus Vice access control scheme. 12. The PCI bus according to claim 10, wherein
The PCI device and the PCI slot are PCI
A PCI device connection control system which is an X bus, a PCI-X device and a PCI-X slot. 13. The PCI bus according to claim 11, wherein
The PCI device and the PCI slot are PCI
A PCI device connection control system which is an X bus, a PCI-X device and a PCI-X slot. 14. A PCI device connection control system according to claim 10, wherein said electrically connectable or disconnectable device is a bus switch. 15. A PCI device connection control system according to claim 12, wherein said device capable of electrically connecting or disconnecting is configured by a bus switch. 16. The PCI device, comprising: at least one PCI bus, an arbitrary number of PCI slots, and a PCI device having at least one specific function and connected to the PCI bus without passing through a PCI slot. The device and the PCI slot are a PCI bus system connected to the PCI bus via a device that can be electrically connected or disconnected, and a PCI device having the specific function is connected to the PCI bus when the system starts up. A PCI device connection control method, wherein, when connection is detected, the PCI slot is electrically disconnected from the PCI bus by controlling the device capable of controlling the electrical connection or disconnection. . 17. The PCI bus according to claim 16, wherein
The PCI device and the PCI slot are PCI
A PCI device connection control system that is an X bus, a PCI-X device, and a PCI-X slot. 18. A PCI device connection control system according to claim 16, wherein said device capable of electrically connecting or disconnecting is configured by a bus switch. 19. The PCI device connection control method according to claim 16, wherein the PCI device having the specific function is a PCI device having an encryption processing function. 20. A PCI device connection control method according to claim 17, wherein the PCI device is a PCI device having an encryption function. 21. The P-type bus via at least one PCI bus and a device which can be electrically connected or disconnected.
A PCI bus system having an arbitrary number of PCI slots connected to a CI bus and detecting that a PCI device having a specific function is installed in the PCI slot when the system is started, A PCI device connection control method, comprising: controlling a device that can be electrically connected or disconnected to electrically disconnect a PCI slot among the PCI slots where no PCI device is mounted from the PCI bus. 22. The PCI bus according to claim 21,
The PCI device and the PCI slot are PCI
A PCI device connection control system that is an X bus, a PCI-X device, and a PCI-X slot. 23. A PCI device connection control system according to claim 21, wherein the device capable of electrically connecting or disconnecting is configured by a bus switch. 24. A PCI device connection control method according to claim 21, wherein the PCI device having the specific function is a PCI device having an encryption processing function. 25. A PCI device connection control method according to claim 22, wherein the PCI device is a PCI device having an encryption function. 26. A PCI-X bus operating in at least one 66 MHz mode, the PCI-X bus having an arbitrary number of PCI-X slots, and the PCI-X slot having no PCI-X slot.
A PCI-X device connected to the CI-X bus,
The PCI-X device and the PCI-X slot are connected to each other via a device that can be electrically connected or disconnected.
A PCI-X bus system connected to a CI-X bus, wherein a sum of the number of the PCI-X devices and a value obtained by doubling the number of the PCI-X slots is larger than 4; The PC electrically connected to the X bus
Controlling the device that can be electrically connected or disconnected so that the sum of the number of IX slots and the value obtained by doubling the number of PCI-X devices is always 4 or less; And a PCI-X device connection control system for connecting a PCI-X slot to the PCI-X bus. 27. A PCI-X device connection control system according to claim 26, wherein the device capable of electrically connecting or disconnecting is configured by a bus switch. 28. A PCI-X bus operating in at least one 66 MHz mode, the PCI-X slot, and the P-P bus without passing through an arbitrary number of PCI-X slots.
A PCI-X device connected to the CI-X bus,
The PCI-X device and the PCI-X slot are connected to each other via a device that can be electrically connected or disconnected.
A PCI-X bus system connected to a CI-X bus, wherein a sum of the number of the PCI-X devices and a value obtained by doubling the number of the PCI-X slots is larger than 8; The PC electrically connected to the X bus
Controlling the electrically connectable or disconnectable device so that the sum of the number of IX slots and the value obtained by doubling the number of PCI-X devices is always 8 or less; And a PCI-X device connection control system for connecting a PCI-X slot to the PCI-X bus. 29. A PCI-X device connection control system according to claim 28, wherein the device which can be electrically connected or disconnected is a bus switch. 30. A PCI-X bus operating in at least one 100 MHz mode, and a PCI-X bus connected to the PCI-X bus without passing through an arbitrary number of PCI-X slots and an arbitrary number of PCI-X slots. An X device, wherein the PCI-X device and the PCI-X slot are connected to the PCI-X bus via a device that can be electrically connected or disconnected, and the number of the PCI-X devices A PCI-X bus system in which the sum of a value obtained by doubling the number of the PCI-X slots is greater than four, wherein the PC electrically connected to the PCI-X bus
Controlling the device that can be electrically connected or disconnected so that the sum of the number of IX slots and the value obtained by doubling the number of PCI-X devices is always 4 or less; And a PCI-X device connection control system for connecting a PCI-X slot to the PCI-X bus. 31. A PCI-X device connection control system according to claim 30, wherein the device capable of being electrically connected or disconnected is a bus switch. 32. A PCI-X bus operating in at least one 133 MHz mode, and a PCI-X bus connected to the PCI-X bus without passing through an arbitrary number of PCI-X slots and an arbitrary number of PCI-X slots. An X device, wherein the PCI-X device and the PCI-X slot are connected to the PCI-X bus via a device that can be electrically connected or disconnected, and the number of the PCI-X devices A PCI-X bus system in which the sum of a value obtained by doubling the number of PCI-X slots is greater than two, wherein the PC electrically connected to the PCI-X bus
Controlling the electrically connectable or disconnectable device so that the sum of the number of IX slots and the value obtained by doubling the number of PCI-X devices is always 2 or less; And a PCI-X device connection control system for connecting a PCI-X slot to the PCI-X bus. 33. A PCI-X device connection control system according to claim 32, wherein the device that can be electrically connected or disconnected is a bus switch.