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JP2002026010A - Multilayer wiring for bare chip mounting and its manufacturing method - Google Patents

Multilayer wiring for bare chip mounting and its manufacturing method

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Publication number
JP2002026010A
JP2002026010A JP2000200773A JP2000200773A JP2002026010A JP 2002026010 A JP2002026010 A JP 2002026010A JP 2000200773 A JP2000200773 A JP 2000200773A JP 2000200773 A JP2000200773 A JP 2000200773A JP 2002026010 A JP2002026010 A JP 2002026010A
Authority
JP
Japan
Prior art keywords
wiring
film
metal layer
layer
interlayer film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000200773A
Other languages
Japanese (ja)
Other versions
JP3471723B2 (en
Inventor
Suehiro Sugitani
末広 杉谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
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Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP2000200773A priority Critical patent/JP3471723B2/en
Publication of JP2002026010A publication Critical patent/JP2002026010A/en
Application granted granted Critical
Publication of JP3471723B2 publication Critical patent/JP3471723B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

(57)【要約】 【課題】層間膜や保護膜に有機膜を用い、耐湿性に優
れ、配線の主メタルとの密着性が良く、信頼性の高いベ
アチップ実装対応多層配線およびその作製方法を提供す
る。 【解決手段】電子デバイスと、少なくとも一層よりなる
下層配線を有する半導体基板上に、下層配線と上層配線
とを繋ぐコンタクトホール部を有し、膜内部に所定の含
水率(好ましくは1〜5重量%)で水分を閉じ込め、か
つ膜外部に水分が滲出しにくい性状の有機材料(例えば
ポリイミド系)よりなる層間膜を設け、該層間膜上に、
配線の主メタル層との密着性を良くし、酸素原子が侵入
しにくいアモルファス組織の金属化合物よりなる下地メ
タル層(例えばWSiN系)を堆積し、その上に配線の
主メタル層を堆積して、上層配線パターンを形成し、該
上層配線パターンの上部に有機材料よりなる保護膜を設
けた多層配線構造とする。
[Problem] To provide a highly reliable multilayer wiring for bare chip mounting and an excellent method of using an organic film as an interlayer film and a protective film, having excellent moisture resistance, good adhesion to a main metal of the wiring, and high reliability. provide. A semiconductor substrate having an electronic device and at least one lower layer wiring has a contact hole portion connecting the lower layer wiring and the upper layer wiring, and a predetermined moisture content (preferably 1 to 5 wt. %), An interlayer film made of an organic material (for example, a polyimide-based material) having a property of confining moisture and hardly exuding moisture to the outside of the film is provided.
By improving the adhesion of the wiring to the main metal layer, depositing a base metal layer (for example, WSiN-based) made of a metal compound having an amorphous structure, which is difficult for oxygen atoms to penetrate, and depositing the main metal layer of the wiring thereon To form a multilayer wiring structure in which an upper layer wiring pattern is formed and a protective film made of an organic material is provided on the upper layer wiring pattern.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ベアチップ実装に
適用可能な、GaAs系およびSi系通信用IC・混成
マイクロ波回路等の半導体集積回路におけるベアチップ
実装対応多層配線およびその作製方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring compatible with bare chip mounting in a semiconductor integrated circuit such as a GaAs-based and Si-based communication IC / hybridized microwave circuit, which can be applied to bare chip mounting, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】GaAs系およびSi系通信用1C・混
成マイクロ波回路等の半導体集積回路の配線では、多数
の配線層を厚い有機材料を用いた絶縁膜を通してVIA
(バイアコンタクト)接続して形成した多層配線構造
が、回路の小型化や多機能化に有効である。
2. Description of the Related Art In the wiring of a semiconductor integrated circuit such as a 1C / hybrid microwave circuit for GaAs and Si communication, a large number of wiring layers are formed through a VIA through an insulating film using a thick organic material.
(Via contact) A multilayer wiring structure formed by connection is effective for miniaturization and multifunctionalization of a circuit.

【0003】従来のこの種の配線を持つ半導体チップ
は、セラミック等の完全密封ケースに入れて使用された
ため、配線部分の耐湿特性は全く問題にならなかった。
また、有機材料は、シリコン酸化膜、シリコン窒化膜等
の無機材料に比べて吸湿性が高いため、耐湿特性が悪く
十分な信頼性が得られないと一般的に思われていた。こ
のため、高い耐湿性を必要とする用途に適用するための
検討はあまりなされていなかった。
A conventional semiconductor chip having this type of wiring has been used in a completely sealed case made of ceramic or the like, so that the moisture resistance characteristics of the wiring portion did not matter at all.
In addition, since organic materials have higher hygroscopicity than inorganic materials such as a silicon oxide film and a silicon nitride film, it has generally been considered that moisture resistance is poor and sufficient reliability cannot be obtained. For this reason, studies for applying to applications requiring high moisture resistance have not been made much.

【0004】[0004]

【発明が解決しようとする課題】近年、通信機器の急速
な成長に伴い、上述の半導体デバイスにおいても低コス
ト化が望まれるようになってきた。また、デバイス製作
のコストダウンも進み、パッケージのコスト高が目立ち
はじめ、コストの低いベアチップ実装の要求が高まって
いる。
In recent years, with the rapid growth of communication equipment, it has been desired to reduce the cost of the above-mentioned semiconductor devices. In addition, the cost of device fabrication has been reduced, and the cost of packages has become noticeable, and demand for low-cost bare chip mounting has increased.

【0005】しかし、無機材料は耐湿性の点では有効で
あると考えられているが、無機材料を用いて厚い層間膜
を作製することは非常に難しいという問題がある。
However, although inorganic materials are considered to be effective in terms of moisture resistance, there is a problem that it is extremely difficult to form a thick interlayer film using inorganic materials.

【0006】また、有機層間膜の上に保護膜として耐湿
性に優れた無機膜を堆積する方法も考えられるが、有機
膜と無機膜では熱膨張係数が大きく異なるため、無機膜
にひびが入り易く、十分な信頼性が得られないという問
題がある。
A method of depositing an inorganic film having excellent moisture resistance as a protective film on the organic interlayer film is also considered. However, since the organic film and the inorganic film have significantly different thermal expansion coefficients, the inorganic film is cracked. There is a problem that it is easy and sufficient reliability cannot be obtained.

【0007】一方、配線メタルについては、配線の主メ
タルであるAu(金)は耐湿性については全く問題はな
いが、配線の下地メタル層については、W(タングステ
ン)系のメタルは密着性が高く、スパッタでの堆積が容
易、ドライエッチングでの加工が容易等の利点はある
が、Wは抵抗率が低く、酸化には強いが、エレクトロマ
イグレーションを起こし易いという問題があり、またW
Si(タングステンシリサイド)メタルは抵抗率は比較
的低いが酸化され易いという問題がある。
On the other hand, regarding the wiring metal, Au (gold), which is the main metal of the wiring, has no problem with respect to the moisture resistance, but the W (tungsten) -based metal has low adhesion with respect to the underlying metal layer of the wiring. Although W has advantages such as high deposition by sputtering and easy processing by dry etching, W has a low resistivity and is resistant to oxidation, but has a problem of easily causing electromigration.
Si (tungsten silicide) metal has a problem that it has a relatively low resistivity but is easily oxidized.

【0008】また、Ti(チタン)系メタルは加工性が
悪く、ドライエッチングで除去しにくいことから、加工
後にTi原子が残り易く、耐圧特性が劣化しやすいとい
う問題があり、また、Pt(白金)系メタルは密着性が
悪く、ボンディング時にパッド剥離を起こし易いという
問題があった。
Further, since Ti (titanium) -based metal has poor workability and is difficult to remove by dry etching, there is a problem that Ti atoms are apt to remain after processing and the withstand voltage characteristic is easily deteriorated. ) The system metal has poor adhesion and has a problem that the pad is easily peeled off during bonding.

【0009】本発明の目的は、上記従来技術における問
題点を解消し、層間膜や保護膜として特定の含水率を有
する有機膜を用い、配線の主メタル層との密着性が良
く、かつ酸素原子が侵入しにくいアモルファス組織の下
地メタル層を有する配線部分の耐湿特性に優れた信頼性
の高いベアチップ実装対応多層配線およびその作製方法
を提供することにある。
An object of the present invention is to solve the above-mentioned problems in the prior art, to use an organic film having a specific water content as an interlayer film or a protective film, to have good adhesion to a main metal layer of a wiring, and to provide oxygen. It is an object of the present invention to provide a highly reliable bare chip mounting multilayer wiring excellent in moisture resistance of a wiring portion having a base metal layer having an amorphous structure in which atoms do not easily penetrate, and a method of manufacturing the same.

【0010】[0010]

【課題を解決するための手段】上記本発明の目的を達成
するために、特許請求の範囲に記載のような構成とする
ものである。すなわち、請求項1に記載のように、電子
デバイスと、少なくとも一層よりなる下層配線を有する
半導体基板上に、上記下層配線と上層配線とを繋ぐコン
タクトホール部を有し、膜内部に所定の含水率で水分を
閉じ込め、かつ膜外部に水分が滲出しにくい性状の有機
材料よりなる層間膜を設け、該層間膜上に、配線の主メ
タル層との密着性を良くし、酸素原子が侵入しにくいア
モルファス構造の金属化合物よりなる下地メタル層を堆
積し、その上に配線の主メタル層を堆積して、上層配線
パターンを形成し、該上層配線パターンの上部に保護膜
を少なくとも設けてなるベアチップ実装対応多層配線と
するものである。
Means for Solving the Problems In order to achieve the above object of the present invention, the present invention is configured as described in the claims. That is, as described in claim 1, on a semiconductor substrate having an electronic device and at least one lower layer wiring, a contact hole portion connecting the lower layer wiring and the upper layer wiring is provided, and a predetermined amount of water is contained inside the film. An interlayer film made of an organic material having a property of confining moisture at a high rate and hardly exuding moisture is provided outside the film. On the interlayer film, adhesion between the wiring and the main metal layer is improved, and oxygen atoms enter the film. A bare chip comprising: depositing a base metal layer made of a metal compound having a difficult amorphous structure, depositing a main metal layer of wiring thereon, forming an upper wiring pattern, and providing at least a protective film on the upper wiring pattern. This is a multilayer wiring for mounting.

【0011】また、請求項2に記載のように、請求項1
において、上記下地メタル層はタングステンシリコンナ
イトライド(WSiN)系金属化合物よりなるベアチッ
プ実装対応多層配線とするものである。
Further, as described in claim 2, claim 1
In the above, the base metal layer is a multi-layer wiring for a bare chip mounting made of a tungsten silicon nitride (WSin) metal compound.

【0012】また、請求項3に記載のように、請求項1
において、上記層間膜または保護膜、もしくは上記層間
膜および保護膜を、含水率が重量%で1〜5%のポリイ
ミド系有機材料よりなるベアチップ実装対応多層配線と
するものである。
Further, as described in claim 3, claim 1
Wherein the interlayer film or the protective film, or the interlayer film and the protective film, is a bare chip mounting-compatible multilayer wiring made of a polyimide organic material having a moisture content of 1 to 5% by weight.

【0013】また、請求項4に記載のように、電子デバ
イスと、少なくとも一層よりなる下層配線を形成した半
導体基板上に、水分を膜内部に所定の含水率で閉じこ
め、かつ膜外部に水分が滲出しにくい性状のポリイミド
系有機材料を用いて層間膜を堆積する工程と、次に、下
層配線と上層配線を繋ぐコンタクトホール部を上記有機
材料よりなる層間膜に形成する工程と、上記層間膜上
に、配線の主メタル層との密着性を向上させるためのW
SiN系金属化合物よりなるアモルファス構造の下地メ
タル層を堆積する工程と、上記下地メタル層上に、配線
の主メタル層をメッキするためのメッキ用電極層を堆積
し、電解メッキにより上記主メタル層を堆積する工程
と、上記配線の主メタル層の表面に、レジスト材料を用
いて配線パタンを有するレジストマスクを形成した後、
該マスクを用いて、ミリング法により、不必要な主メタ
ル部分および下地メタル部分を除去して上層配線を加工
形成する工程と、上記レジストマスクを除去した後、フ
ッ素系ガスを用いた反応性イオンエッチングにより、上
記層間膜表面にわずかに残った下地メタル原子をエッチ
ング除去する工程と、上記主メタル層の表面および層間
膜の表面上に、上記層間膜と同じ有機材料、もしくはそ
の他の保護用有機材料を用いて保護膜を堆積した後、該
保護膜上に配線のパッド出しパタンを有するレジストマ
スクを形成し、該マスクを用いて配線のパッド領域を形
成した後、上記レジストマスクを除去する工程を含むベ
アチップ実装対応多層配線の作製方法とするものであ
る。
According to a fourth aspect of the present invention, on a semiconductor substrate on which an electronic device and at least one lower layer wiring are formed, moisture is confined inside the film at a predetermined moisture content, and moisture is contained outside the film. A step of depositing an interlayer film using a polyimide-based organic material having a property that is difficult to exude, a step of forming a contact hole portion connecting the lower wiring and the upper wiring in the interlayer film made of the organic material, On top, W for improving the adhesion of the wiring to the main metal layer is formed.
Depositing a base metal layer having an amorphous structure made of a SiN-based metal compound, depositing a plating electrode layer for plating a main metal layer of wiring on the base metal layer, and forming the main metal layer by electrolytic plating; And after forming a resist mask having a wiring pattern using a resist material on the surface of the main metal layer of the wiring,
Using the mask, a milling method is used to remove unnecessary main metal portions and underlying metal portions to process and form an upper wiring, and after removing the resist mask, reactive ions using a fluorine-based gas are removed. A step of etching and removing underlying metal atoms slightly remaining on the surface of the interlayer film by etching; and forming the same organic material as the interlayer film or another protective organic material on the surface of the main metal layer and the surface of the interlayer film. Depositing a protective film using a material, forming a resist mask having a pad pattern for wiring on the protective film, forming a pad region for wiring using the mask, and removing the resist mask And a method for producing a multilayer wiring for bare chip mounting.

【0014】本発明のベアチップ実装対応多層配線およ
びその作製方法は、次の2点の改善を行ったものであ
る。すなわち、(1)従来、多層配線の耐湿性について
有機材料の含水率(吸湿性)が問題とされてきたが、含
水率の低い材料は内部に水分を含むことができないた
め、水分の通過性は逆に非常に高い。このため、メタル
配線の腐食に必要とする水分量が十分に通過してしまう
ことになり、耐湿性が悪くなる。(2)一方、含水率
が、例えば1〜5%と適度にある材料は、膜内部で水分
をしっかりと保持する性質があるため、水分の通過性は
非常に低いことになる。したがって、耐湿性としては後
者の方が適していることになる。
The multilayer wiring for bare chip mounting and the method of manufacturing the same according to the present invention have the following two improvements. That is, (1) Conventionally, the moisture content (hygroscopicity) of an organic material has been regarded as a problem with respect to the moisture resistance of a multilayer wiring. However, since a material having a low moisture content cannot contain moisture inside, the moisture permeability is low. Is very high on the contrary. For this reason, the amount of water required for the corrosion of the metal wiring passes through sufficiently, and the moisture resistance deteriorates. (2) On the other hand, a material having a moderate moisture content of, for example, 1 to 5% has a property of firmly retaining moisture inside the membrane, and therefore has very low moisture permeability. Therefore, the latter is more suitable as moisture resistance.

【0015】図2に、非常に腐食され易いWSi(タン
グステンシリサイド)メタルを、吸湿性の低い、例え
ば、含水率が0.2%のBCB〔ベンゾシクロブテン(B
enzocyclobutene)〕被覆、または、適度な吸湿性、例
えば含水率が1〜5%のポリイミド(Polyimide)で覆
った試料の腐食状況を示す抵抗変化率〔抵抗R/初期の
抵抗Ro〕と試験時間との関係を示す。試験条件は、8
5℃、85%R.H.である。比較のため、被覆せずにメ
タル(WSi)が剥き出し状態の試料の結果も併せて示
す。
FIG. 2 shows that WSi (tungsten silicide) metal, which is very susceptible to corrosion, is replaced with BCB [benzocyclobutene (B) having a low hygroscopicity, for example, a water content of 0.2%.
enzocyclobutene)] The rate of change of resistance [resistance R / initial resistance Ro] indicating the corrosion state of a sample coated or covered with a suitable hygroscopic property, for example, a polyimide having a moisture content of 1 to 5%. Shows the relationship. The test conditions are 8
5 ° C., 85% RH. For comparison, the result of a sample in which metal (WSi) is exposed without coating is also shown.

【0016】図2より、吸湿性(含水率)の低いBCB
被覆より、適度の吸湿性を持つポリイミド被覆の方がR
/Roの値がほぼ一定で抵抗変化がなく、良好な耐湿特
性を示している。なお、ポリイミドの含水率は重量%で
1〜5%のものが好ましく、配線の耐湿性の点から言っ
て、より好ましい含水率の範囲は2〜3%である。
FIG. 2 shows that BCB having low hygroscopicity (moisture content)
Polyimide coating with moderate hygroscopicity has better R than coating.
The value of / Ro was almost constant, there was no change in resistance, and good moisture resistance was exhibited. The moisture content of the polyimide is preferably 1 to 5% by weight, and more preferably 2 to 3% in terms of moisture resistance of the wiring.

【0017】本発明は下地メタルとして、W(タングス
テン)系メタルの利点を有しながら、水分が浸入しにく
いアモルファス構造のWSiN系金属化合物を用いるこ
と、および下地メタルであるWSiN系金属化合物のミ
リング加工工程において、Wを確実に除去し、残ったW
原子の移動によるショート故障を防止するために、さら
にフッ素系ガスの反応性イオンエッチング工程を導入す
ることを特徴としたものである。
According to the present invention, a WSiN-based metal compound having an amorphous structure which does not easily penetrate moisture while having the advantage of a W (tungsten) -based metal is used as a base metal, and the WSiN-based metal compound as a base metal is milled. In the processing step, W is reliably removed and the remaining W
In order to prevent short-circuit failure due to movement of atoms, a reactive ion etching step of fluorine-based gas is further introduced.

【0018】下地メタル層を形成するWSiN系金属化
合物は、W原子間の隙間をSiとNが隙間なく埋めたア
モルファス構造となっているため、酸化の原因となる酸
素の侵入が非常に難しく、耐湿性に優れたメタル化合物
と言える。また、アモルファス構造であるため、原子の
移動も難しく、このためエレクトロマイグレーションも
起こしにくいという特徴がある。
Since the WSiN-based metal compound forming the base metal layer has an amorphous structure in which the gap between W atoms is filled with Si and N without any gap, it is very difficult for oxygen to cause oxidation to penetrate. It can be said that it is a metal compound having excellent moisture resistance. In addition, since it has an amorphous structure, it is difficult to move atoms, so that electromigration hardly occurs.

【0019】このWSiN系金属化合物を構成するW、
Si、Nの原子比は、必ずしも化学量論的量でなくても
よく、構成元素の量に多少の変動があっても、W原子間
の隙間をSiとNが隙間なく埋めたアモルファス構造を
とるものであれば本発明の下地メタル層として適用する
ことが可能である。
W constituting the WSiN-based metal compound,
The atomic ratio of Si and N does not necessarily have to be a stoichiometric amount, and even if there is a slight variation in the amount of constituent elements, an amorphous structure in which Si and N fill the gap between W atoms without gap. As long as it can be used, it can be applied as the base metal layer of the present invention.

【0020】図3に各種のメタルおよびメタル化合物の
抵抗変化率(腐食状況)と試験時間の関係を示す。メタ
ル上に保護膜はなく剥き出し状態の試料である。試験条
件は、85℃、85%R.H.である。WSiN系金属化
合物が水分に対し最も耐食性がよく、下地メタル層に適
していることが分かる。
FIG. 3 shows the relationship between the resistance change rate (corrosion state) of various metals and metal compounds and the test time. This is a bare sample without a protective film on the metal. The test conditions are 85 ° C. and 85% RH. It can be seen that the WSiN-based metal compound has the best corrosion resistance to moisture and is suitable for the underlying metal layer.

【0021】ただし、W系化合物は、ミリング加工等の
機械的除去方法では完全に除去することは難しい。残留
したW原子は湿度の低いときには全く問題は生じない
が、高温高湿下では単体メタル原子であるため容易に移
動し、ショート故障の原因となる。このため、本発明の
多層配線の作製方法においては、ミリング加工後に、例
えば、フッ素系ガスの反応性イオンエッチング工程を追
加し、残留したW原子をほぼ完全に除去することによ
り、W原子の移動によるショート故障を起こすことな
く、耐湿性に優れた信頼性の高いベアチップ実装対応多
層配線を実現できる効果がある。
However, it is difficult to completely remove the W-based compound by a mechanical removal method such as milling. The remaining W atoms do not cause any problem when the humidity is low, but easily move under high temperature and high humidity because they are single metal atoms and cause a short-circuit failure. For this reason, in the method for manufacturing a multilayer wiring according to the present invention, after the milling process, for example, a reactive ion etching step of a fluorine-based gas is added, and the remaining W atoms are almost completely removed. Thus, it is possible to realize a highly reliable multilayer wiring compatible with bare chip mounting having excellent moisture resistance without causing a short circuit failure due to the above.

【0022】[0022]

【発明の実施の形態】以下に、本発明のベアチップ実装
対応多層配線の作製方法に関する実施の形態を例示し、
図面を用いてさらに詳細に説明する。図1は本発明の実
施の形態で例示するベアチップ実装対応多層配線の作製
過程を示す工程図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a method for manufacturing a multilayer wiring for bare chip mounting according to the present invention will be exemplified.
This will be described in more detail with reference to the drawings. FIG. 1 is a process chart showing a process of manufacturing a multilayer wiring for bare chip mounting exemplified in the embodiment of the present invention.

【0023】図1(a)に示すように、下層配線2を有
する半導体基板1に、ポリイミド等の有機材料よりなる
層間膜3を堆積する。
As shown in FIG. 1A, an interlayer film 3 made of an organic material such as polyimide is deposited on a semiconductor substrate 1 having a lower wiring 2.

【0024】次に、レジスト等の材料を用いて穴パタン
5を有するレジストマスク4を形成し、該レジストマス
ク4を用いて、O(酸素)/CF(四フッ化炭素)
の混合ガスを用いてRIE(反応性イオンエッチング)
により、層間膜3に、下層配線2の表面に達する穴パタ
ン5を形成する〔図1(b)〕。
Next, a resist mask 4 having a hole pattern 5 is formed using a material such as a resist, and O 2 (oxygen) / CF 4 (carbon tetrafluoride) is formed using the resist mask 4.
(Reactive ion etching) using a mixed gas of
Thereby, a hole pattern 5 reaching the surface of the lower wiring 2 is formed in the interlayer film 3 (FIG. 1B).

【0025】次に、酸素プラズマ処理(灰化処理)等に
より、レジストマスク4を除去する〔図1(c)〕。
Next, the resist mask 4 is removed by an oxygen plasma treatment (ashing treatment) or the like (FIG. 1C).

【0026】次に、穴パタン5の内部も含めた層間膜3
の表面全域に、まず密着性向上のためのWSiN系金属
化合物よりなる下地メタル層6と、メッキ用電極7とし
て薄くAu(金)をスパッタ法により連続して形成す
る。次いで、メッキ用電極7を用いて、その上に、Au
の電解メッキにより、主メタル配線層8を堆積する〔図
1(d)〕。
Next, the interlayer film 3 including the inside of the hole pattern 5 is formed.
First, a thin underlayer of Au (gold) is continuously formed by sputtering as a base metal layer 6 made of a WSiN-based metal compound for improving adhesion and a thin electrode 7 for plating. Next, using the plating electrode 7, Au
The main metal wiring layer 8 is deposited by electroplating (FIG. 1D).

【0027】次に、穴パタン領域および所望の配線パタ
ン領域をフォトレジスト9で覆い、ミリングにより不要
な領域の主メタル配線層8、メッキ用電極7、および下
地メタル層6を除去する〔図1(e)〕。
Next, the hole pattern region and the desired wiring pattern region are covered with a photoresist 9, and the unnecessary portions of the main metal wiring layer 8, the plating electrode 7, and the base metal layer 6 are removed by milling [FIG. (E)].

【0028】この後、フォトレジスト9を酸素プラズマ
処理(灰化処理)などにより除去した後、SF(六フ
ッ化イオウ)ガスを用いたRIEなどで層間膜3上に残
ったわずかなW原子を除去する〔図1(f)〕。
After that, the photoresist 9 is removed by oxygen plasma treatment (ashing treatment) or the like, and then a small amount of W atoms remaining on the interlayer film 3 by RIE using SF 6 (sulfur hexafluoride) gas or the like. Is removed [FIG. 1 (f)].

【0029】次に、ポリイミド等の有機材料の保護膜1
0を堆積する。次いで、レジスト等の材料を用いてパッ
ド出しパタン12を有するレジストマスク11を形成す
る〔図1(g)〕。
Next, a protective film 1 made of an organic material such as polyimide is used.
Deposit 0. Next, a resist mask 11 having a pad pattern 12 is formed using a material such as a resist (FIG. 1 (g)).

【0030】次に、レジストマスク11を用いて、O
/CFの混合ガスを用いたRIEにより、配線のパッ
ド部13上の保護膜10を除去し、次いで、酸素プラズ
マ処理(灰化処理)などにより、レジストマスク11を
除去し、ベアチップ実装対応多層配線構造を作製する
〔図1(h)〕。
Next, using the resist mask 11, O 2
The protective film 10 on the pad portion 13 of the wiring is removed by RIE using a mixed gas of / CF 4 , and then the resist mask 11 is removed by an oxygen plasma treatment (ashing treatment) or the like, and the multilayer for bare chip mounting is removed. A wiring structure is manufactured (FIG. 1H).

【0031】このように、本発明の多層配線の作製方法
において、ミリング加工後に、例えば、フッ素系ガスの
反応性イオンエッチング工程を追加し、残留したW原子
を完全に除去することにより、W原子の移動等によるシ
ョート故障が抑止できる耐湿性に優れた信頼性の高いベ
アチップ実装対応多層配線を実現することができた。
As described above, in the method for manufacturing a multilayer wiring according to the present invention, after the milling process, for example, a reactive ion etching step of a fluorine-based gas is added, and the remaining W atoms are completely removed. A highly reliable multi-layer wiring for bare chip mounting with excellent moisture resistance and capable of suppressing short-circuit failure due to movement or the like was realized.

【0032】本実施の形態では、メッキ用電極7として
Auをスパッタした薄膜を用い、主メタル配線層8はA
uの電解メッキ層としたが、Auの代りにAu合金を用
いることもでき、あるいはCu(銅)またはCu合金等
を用いることも可能であり、主メタル配線層としての所
定の性能を有する金属または合金であれば本発明に適用
できることは言うまでもない。
In the present embodiment, a thin film obtained by sputtering Au is used as the plating electrode 7, and the main metal wiring layer 8 is made of A
Although the electroplated layer of u is used, an Au alloy can be used instead of Au, or Cu (copper) or a Cu alloy can be used, and a metal having a predetermined performance as a main metal wiring layer can be used. Of course, if it is an alloy, it can be applied to the present invention.

【0033】[0033]

【発明の効果】本発明のベアチップ実装対応多層配線と
その作製方法によれば、層間膜や保護膜として耐湿性に
優れたポリイミド等の有機膜を用い、また、配線の主メ
タルとの密着性が良く、酸素原子が侵入しにくいアモル
ファス構造のWSiN系金属化合物の下地メタル層を設
けることにより耐湿性に優れた多層配線構造を実現する
ことができる。
According to the multilayer wiring for bare chip mounting and the method of manufacturing the same according to the present invention, an organic film such as polyimide excellent in moisture resistance is used as an interlayer film and a protective film, and the adhesion of the wiring to the main metal is improved. By providing a base metal layer of a WSiN-based metal compound having an amorphous structure that is less likely to penetrate oxygen atoms, a multilayer wiring structure excellent in moisture resistance can be realized.

【0034】さらに、本発明の多層配線の作製方法によ
れば、ミリング加工後に、例えば、フッ素系ガスの反応
性イオンエッチング工程を追加し、残留したW原子を完
全に除去することにより、W原子の移動等によるショー
ト故障を抑止できる耐湿性に優れた信頼性の高いベアチ
ップ実装対応多層配線を簡易な工程で作製することが可
能となる。これにより、GaAs系およびSi系通信用
IC・混成マイクロ波回路等の半導体集積回路の低コス
ト化と信頼性の向上に寄与することができる。
Further, according to the method for manufacturing a multilayer wiring of the present invention, after the milling process, for example, a reactive ion etching step of a fluorine-based gas is added, and the remaining W atoms are completely removed. It is possible to manufacture a highly reliable multi-layer wiring for bare chip mounting, which is excellent in moisture resistance and can suppress a short circuit failure due to movement of the semiconductor chip, by a simple process. This can contribute to cost reduction and improvement in reliability of semiconductor integrated circuits such as GaAs-based and Si-based communication ICs and hybrid microwave circuits.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態で例示したベアチップ実装
対応多層配線の作製方法を示す工程図。
FIG. 1 is a process chart showing a method for manufacturing a multilayer wiring compatible with bare chip mounting exemplified in the embodiment of the present invention.

【図2】WSiメタルを、吸水性の低いBCBまたはポ
リイミド系有機材料で被覆した場合の試料の抵抗変化率
(腐食状況)と試験時間の関係を示す図。
FIG. 2 is a graph showing a relationship between a resistance change rate (corrosion state) of a sample and a test time when a WSi metal is coated with BCB or a polyimide organic material having low water absorption.

【図3】各種のメタルおよびメタル化合物の抵抗変化率
(腐食状況)と試験時間の関係を示す図。
FIG. 3 is a diagram showing the relationship between the resistance change rate (corrosion state) of various metals and metal compounds and the test time.

【符号の説明】[Explanation of symbols]

1…基板 2…下層配線 3…層間膜 4…レジストマスク 5…穴パタン 6…下地メタル層 7…メッキ用電極 8…主メタル配線層 9…レジストマスク 10…保護膜 11…レジストマスク 12…パッド出しパタン 13…配線のパッド部 DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Lower wiring 3 ... Interlayer film 4 ... Resist mask 5 ... Hole pattern 6 ... Base metal layer 7 ... Plating electrode 8 ... Main metal wiring layer 9 ... Resist mask 10 ... Protective film 11 ... Resist mask 12 ... Pad Output pattern 13 ... Pad part of wiring

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5F033 GG02 HH11 HH12 HH13 HH28 HH34 JJ01 JJ11 JJ12 JJ13 JJ28 JJ34 MM05 MM13 NN06 NN07 PP15 PP27 PP33 QQ08 QQ09 QQ10 QQ13 QQ14 QQ37 QQ93 RR22 VV07 WW00 XX14 XX18 XX31  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference)

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】電子デバイスと、少なくとも一層よりなる
下層配線を有する半導体基板上に、上記下層配線と上層
配線とを繋ぐコンタクトホール部を有し、膜内部に所定
の含水率で水分を閉じ込め、かつ膜外部に水分が滲出し
にくい性状の有機材料よりなる層間膜を設け、該層間膜
上に、配線の主メタル層との密着性が良く、酸素原子が
侵入しにくいアモルファス構造の金属化合物よりなる下
地メタル層を堆積し、その上に配線の主メタル層を堆積
して、上層配線パターンを形成し、該上層配線パターン
の上部に保護膜を少なくとも設けてなることを特徴とす
るベアチップ実装対応多層配線。
An electronic device and a semiconductor substrate having at least one lower layer wiring, a contact hole connecting the lower layer wiring and the upper layer wiring, and confining moisture at a predetermined moisture content inside the film, In addition, an interlayer film made of an organic material having a property of preventing moisture from oozing out is provided outside the film. On the interlayer film, a metal compound having an amorphous structure that has good adhesion to a main metal layer of wiring and has a low penetration of oxygen atoms. A base metal layer, and a main metal layer of wiring thereon, forming an upper wiring pattern, and at least a protective film provided on the upper wiring pattern. Multi-layer wiring.
【請求項2】請求項1において、上記下地メタル層はタ
ングステンシリコンナイトライド(WSiN)系金属化
合物よりなることを特徴とするベアチップ実装対応多層
配線。
2. The multilayer wiring for bare chip mounting according to claim 1, wherein said base metal layer is made of a tungsten silicon nitride (WSiN) based metal compound.
【請求項3】請求項1において、上記層間膜または保護
膜、もしくは上記層間膜および保護膜は、含水率が重量
%で1〜5%のポリイミド系有機材料よりなることを特
徴とするベアチップ実装対応多層配線。
3. The bare chip mounting according to claim 1, wherein the interlayer film or the protection film, or the interlayer film and the protection film are made of a polyimide organic material having a moisture content of 1 to 5% by weight. Corresponding multilayer wiring.
【請求項4】電子デバイスと、少なくとも一層よりなる
下層配線を形成した半導体基板上に、水分を膜内部に所
定の含水率で閉じこめ、かつ膜外部に水分が滲出しにく
い性状のポリイミド系有機材料を用いて層間膜を堆積す
る工程と、 次に、下層配線と上層配線を繋ぐコンタクトホール部を
上記有機材料よりなる層間膜に形成する工程と、 上記層間膜上に、配線の主メタル層との密着性を向上さ
せるためのWSiN系金属化合物よりなるアモルファス
構造の下地メタル層を堆積する工程と、 上記下地メタル層上に、配線の主メタル層をメッキする
ためのメッキ用電極層を堆積し、電解メッキにより上記
主メタル層を堆積する工程と、 上記配線の主メタル層の表面に、レジスト材料を用いて
配線パタンを有するレジストマスクを形成した後、該マ
スクを用いて、ミリング法により、不必要な主メタル部
分および下地メタル部分を除去して上層配線を加工形成
する工程と、 上記レジストマスクを除去した後、フッ素系ガスを用い
た反応性イオンエッチングにより、上記層間膜表面にわ
ずかに残った下地メタル原子をエッチング除去する工程
と、 上記主メタル層の表面および層間膜の表面上に、上記層
間膜と同じ有機材料、もしくはその他の保護用有機材料
を用いて保護膜を堆積した後、該保護膜上に配線のパッ
ド出しパタンを有するレジストマスクを形成し、該マス
クを用いて配線のパッド領域を形成した後、上記レジス
トマスクを除去する工程を含むことを特徴とするベアチ
ップ実装対応多層配線の作製方法。
4. A polyimide organic material having a property of confining moisture at a predetermined moisture content inside a film and preventing water from oozing out of the film on a semiconductor substrate on which an electronic device and at least one lower wiring layer are formed. A step of depositing an interlayer film by using, a step of forming a contact hole portion connecting the lower layer wiring and the upper layer wiring in the interlayer film made of the organic material, and forming a main metal layer of the wiring on the interlayer film. Depositing a base metal layer having an amorphous structure made of a WSiN-based metal compound to improve the adhesion of the substrate; and depositing a plating electrode layer for plating a main metal layer of the wiring on the base metal layer. Depositing the main metal layer by electrolytic plating, and after forming a resist mask having a wiring pattern using a resist material on the surface of the main metal layer of the wiring, Using the mask to remove unnecessary main metal portions and underlying metal portions by milling to form an upper layer wiring; and, after removing the resist mask, reactive ions using a fluorine-based gas. Etching the base metal atoms slightly remaining on the surface of the interlayer film by etching; and forming the same organic material as the interlayer film or another protective organic material on the surface of the main metal layer and the surface of the interlayer film. Depositing a protective film using a material, forming a resist mask having a pad pattern for wiring on the protective film, forming a pad region for wiring using the mask, and removing the resist mask A method for manufacturing a multilayer wiring for bare chip mounting, comprising:
JP2000200773A 2000-07-03 2000-07-03 Multilayer wiring for bare chip mounting and its manufacturing method Expired - Fee Related JP3471723B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000200773A JP3471723B2 (en) 2000-07-03 2000-07-03 Multilayer wiring for bare chip mounting and its manufacturing method

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JP2002026010A true JP2002026010A (en) 2002-01-25
JP3471723B2 JP3471723B2 (en) 2003-12-02

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ID=18698587

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Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114391851A (en) * 2021-12-20 2022-04-26 杭州电子科技大学 Fully-implanted brain-computer interface based on system-level integration process and manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114391851A (en) * 2021-12-20 2022-04-26 杭州电子科技大学 Fully-implanted brain-computer interface based on system-level integration process and manufacturing method

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