JP2001044280A - Multilayer wiring structure and method of manufacturing the same - Google Patents

Abstract

(57) [Problem] To improve electromigration resistance and further miniaturize a multilayer wiring structure. SOLUTION: A lower wiring A is formed of a first titanium film 10.
2, first titanium nitride film 103, first Al-Cu film 1
04, a second titanium film 105 and a second titanium nitride film 106. The via contact B includes a first adhesion layer 109 (a titanium film), a second adhesion layer 110 (a titanium nitride film), and a tungsten plug 111 (a tungsten film). An opening smaller than the planar shape of the via contact B is formed in the second titanium film 105 and the second titanium nitride film 106.
Is connected to the first Al-Cu film 104 at the opening. The first and second adhesion layers 109 and 110 are connected to the peripheral region of the opening in the second titanium nitride film 106 at the protruding portion protruding inward from the lower end of the side wall portion.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring structure in which a lower wiring and an upper wiring are connected by a via contact, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuit devices, especially LSI
In the technology, the component elements have been miniaturized and the aspect ratio of the via hole for connecting the lower layer wiring and the upper layer wiring has increased, so that when the via contact is formed by the sputtering method as in the related art, sufficient coverage can be obtained. It has become impossible to secure.

Therefore, as a via contact connecting the lower wiring and the upper wiring, a tungsten (W) plug formed by a chemical vapor deposition (CVD) method has come to be used. (First Conventional Example) A multilayer wiring structure and a method of manufacturing the same according to a first conventional example will be described below with reference to FIGS. 10 (a) and 10 (b).

First, as shown in FIG. 10A, a first barrier film 12 is formed on an insulating film 11 formed on a semiconductor substrate 10 and a trace amount of copper (Cu) is formed on aluminum (Al).
Are sequentially deposited to form a first laminated film by forming a first titanium nitride (TiN) film 14 serving as an anti-reflection film, and then forming the first laminated film. Of the first stacked film is formed by photolithography and dry etching.

Next, after an interlayer insulating film 15 is deposited on the insulating film 11 including the lower wiring, photolithography and dry etching are performed on the interlayer insulating film 15 and the first titanium nitride film 14. Then, a via hole 16 is formed. Thus, in the dry etching step, the polymer 17 adheres to the side wall surface of the via hole 16 and a natural oxide film is formed in a region of the first Al-Cu film 13 exposed to the via hole 16. Then, after removing the polymer 17 by washing, the first Al
-The natural oxide film formed on the Cu film 13 is removed by plasma made of argon (Ar).

Next, as shown in FIG. 10B, a titanium (Ti) film 18 and a second titanium nitride film 19 are formed on the interlayer insulating film 15 including the side wall surface of the via hole 16 by a sputtering method. Are sequentially deposited, a tungsten film 20 is deposited on the interlayer insulating film 15 including the inside of the via hole 16 by the CVD method. Thereafter, the interlayer insulating film 15 in the titanium film 18, the second titanium nitride film 19 and the tungsten film 20 is formed by anisotropic dry etching.
Remove the portion deposited on top of via hole 1
6, a via contact formed of an adhesion layer made of a titanium film 18, a barrier film made of a second titanium nitride film 19, and a tungsten plug made of a tungsten film 20 is formed.

Next, a second barrier film 21 and a second Al-C are formed on the interlayer insulating film 15 including the via contact.
After a u film 22 and a third titanium nitride film 23 are sequentially deposited to form a second laminated film, the second laminated film is patterned to form an upper wiring composed of the second laminated film. (Second Conventional Example) A multilayer wiring structure and a method of manufacturing the same according to a second conventional example will be described below with reference to FIG.

[0008] As in the first conventional example, the semiconductor substrate 1
After forming a lower wiring composed of a first barrier film 12, a first Al-Cu film 13, and a first titanium nitride film 14 on an insulating film 11 formed on the lower wiring, An interlayer insulating film 15 is deposited over the entire surface of the insulating film 11 including the upper portion, and then photolithography and dry etching are performed on the interlayer insulating film 15 to form via holes 16.
To form That is, unlike the first conventional example, the lower portion of the via hole 16 in the first titanium nitride film 14 is left.

Next, an adhesion layer made of a titanium film 18,
After forming a via contact composed of a barrier film composed of the second titanium nitride film 19 and a tungsten plug composed of the tungsten film 20, a first conventional example is formed on the interlayer insulating film 15 including on the via contact. In the same manner as in the above, an upper wiring composed of the second barrier film 21, the second Al—Cu film 22, and the third titanium nitride film 23 is formed. (Third Conventional Example) A multilayer wiring structure and a method of manufacturing the same according to a third conventional example will be described below with reference to FIGS.

First, as shown in FIG. 12A, a first insulating film 31 and a second insulating film 32 are formed on a semiconductor substrate 30.
Is formed, a first wiring groove is formed in the second insulating film 32. Next, the second insulating film 3 including the inside of the first wiring groove
After a first barrier film 33 and a first copper (Cu) film 34 are sequentially deposited on the second substrate 2, the first barrier film 33 and the first copper film 34 are formed by chemical mechanical polishing (CMP). The portion existing on the second insulating film 32 is removed to form a buried lower wiring composed of the first barrier film 33 and the first copper film.

Next, a first SiNx film 35 for preventing diffusion of copper atoms constituting the first copper film 34 and an interlayer insulating film 3
Then, dry etching is performed on the interlayer insulating film 36 using the resist pattern 37 as a mask to form a via hole 38.

Next, as shown in FIG. 12B, photolithography and dry etching are performed on the first SiNx film 35 and the interlayer insulating film 36 to form a first SiNx film 35 and a first SiNx film 35.
A portion of the Nx film 35 below the via hole 38 is removed, and a second wiring groove 39 connected to the via hole 38 is formed. Next, as in the first conventional example, the polymer adhering to the wall surface of the via hole 38 is removed by washing in the dry etching step, and then the first copper film 34 is removed.
The natural oxide film formed in the region exposed in the via hole 38 is removed by plasma made of argon.

Next, as shown in FIG. 12C, a second barrier film 40 and a second copper film 41 are formed on the interlayer insulating film 36 including the inside of the via hole 38 and the second wiring groove 39. Are sequentially deposited, and the second barrier film 40 is formed by the CMP method.
Then, a portion of the second copper film 41 existing on the interlayer insulating film 36 is removed to form a via contact including the second barrier film 40 and the second copper film 41 and a buried upper wiring. Next, a second SiNx film 42 for preventing diffusion of copper atoms constituting the second copper film 41 is deposited.

[0014]

According to the first prior art multilayer wiring structure, when a current flows from the lower wiring to the via contact, the current is reduced to the first Al-Cu film 13 constituting the lower wiring. Flows from the first titanium nitride film 14 (antireflection film) constituting the lower wiring, only to the titanium film 18 constituting the bottom of the via contact. The reason is that the first titanium nitride film 14 constituting the lower wiring, the titanium film 18, the second titanium nitride film 19 and the tungsten film 2 constituting the via contact
This is because there is no electrical connection or the contact resistance is extremely large between zero.

Here, the reason why no current flows from the first titanium nitride film 14 to the titanium film 18 will be described. (1) When the titanium film 18 and the second titanium nitride film 19 are formed by the sputtering method, the coverage of the side wall of the via hole 16 is deteriorated as the via hole 16 is miniaturized. The second titanium nitride film 19 is hardly formed on the side wall of the via hole 16. (2) When forming the via hole 16,
The polymer 17 attached to the side wall of the first Al-Cu film 13 is not reliably removed by the cleaning, and the natural oxide film formed on the surface of the first Al-Cu film 13 is not reliably removed by the plasma made of argon. (3) The natural oxide film flipped by the plasma of argon adheres to the side wall of the via hole 16. (4) In the dry etching process for forming the via hole 16 or the cleaning process for the via hole 16, a side etch is formed in the first titanium nitride film 14, and the titanium film 1 is formed in a portion where the side etch is formed.
8 and the second titanium nitride film 19 are not formed. (5) Even if the side wall of the via contact and the first titanium nitride film 14 are connected, the first titanium nitride film 1
4 is usually about 30 nm and thin, so that the contact resistance between the side wall of the via contact and the first titanium nitride film 14 is very high.

On the other hand, according to the multi-layer wiring structure of the second conventional example, the current flowing from the lower wiring to the via contact passes from the first Al-Cu film 13 to the first titanium nitride film 14. And flows into the titanium film 18.

According to the third prior art multilayer wiring structure, when a current flows from the lower wiring to the upper wiring, the current flows only directly from the first copper film 34 to the second barrier film 40, Does not flow to the barrier film 33. The reason is that the first barrier film 33 and the second barrier film 40 are not electrically connected or have extremely large contact resistance.

Here, the reason why the current does not flow from the first barrier film 33 to the second barrier film 40 will be described. (1) In the cleaning process performed after the CMP process for forming the lower wiring, or in the etching process for forming the via hole 38 or the subsequent cleaning process,
Of the first barrier film 33 is lower than the upper surface of the first copper film 34, so that the second barrier film 40 Barrier film 33
No film is formed on the substrate. (2) When forming the via hole 38,
The polymer adhered to the side wall of the first copper film 34 is not reliably removed by the cleaning, and the natural oxide film formed on the surface of the first copper film 34 is not reliably removed by the plasma made of argon. (3) Suppose the side wall of the via contact and the first barrier film 3
Even when the first barrier film 33 is connected to the first barrier film 33, the thickness of the first barrier film 33 is usually about 5 nm, which is very small. high.

Hereinafter, an electromigration test performed on the multilayer wiring structure according to the first, second and third conventional examples will be described.

FIGS. 13 (a), 13 (b) and 13 (c) show the rate of increase in resistance with time in an electromigration test in the multilayer wiring structure according to the first, second and third conventional examples. ing. According to the multilayer wiring structures according to the first and third conventional examples, it can be seen that the resistance rise rate sharply increases in the middle and the life of the multilayer wiring structure is short.
On the other hand, according to the multilayer wiring structure according to the second conventional example, the resistance rise rate does not increase sharply, and it can be seen that the life of the multilayer wiring structure is long.

In the following, according to the first and third prior art multilayer wiring structures, the rate of increase in resistance sharply increases.
The reason why the resistance increase rate does not increase rapidly according to the multilayer wiring structure according to the conventional example will be described.

FIG. 14A shows a multi-layer wiring structure according to a second conventional example. The lower part of the via contact in the first Al-Cu film 13 constituting the lower wiring is formed by electromigration. In this case, no current flows because the void 50 is formed. However,
The current flowing from the lower layer wiring to the via contact flows from the first Al-Cu film 13 to the titanium film 18 via the first titanium nitride film 14, so that the resistance increases.
This is because disconnection does not occur.

FIG. 14B shows a multi-layer wiring structure according to a first conventional example. The lower part of the via contact in the first Al-Cu film 13 constituting the lower wiring is formed by electromigration. In this case, no current flows because the void 50 is formed. in this case,
Since the via contact and the first titanium nitride film 14 constituting the lower wiring are not connected, no current flows from the lower wiring to the via contact, so that disconnection occurs.

FIG. 14C shows a multi-layer wiring structure according to a third conventional example. In the lower part of the via contact in the first copper film 34 constituting the lower wiring by electromigration, FIG. Since the void 50 is formed, no current flows. In this case, the first barrier film 33 and the second barrier film 40 are not connected or have a very high resistance, so that no current flows from the lower layer wiring to the via contact, so that disconnection occurs. It is.

For the above reasons, the multilayer wiring structures according to the first and third conventional examples have a serious problem in terms of electromigration resistance.

On the other hand, the multilayer wiring structure according to the second conventional example is excellent in electromigration resistance. However, if the multilayer wiring is further miniaturized, the following problems occur.

In order to stop the dry etching for forming the via hole at the first titanium nitride film 14, the thickness of the first titanium nitride film 14 needs to be 100 nm or more.

However, when the thickness of the first titanium nitride film 14 is increased, the inter-wiring capacitance increases, so that the wiring delay increases. In addition, when the thickness of the first titanium nitride film 14 is increased, the thickness of the lower wiring, and hence the thickness to be subjected to dry etching, is increased. Therefore, the thickness of the resist pattern for patterning the lower wiring is changed by dry etching. Must be large enough to withstand
There is a problem that it is difficult to form a fine resist pattern, and it is difficult to miniaturize a multilayer wiring.

Further, in the case of forming the first titanium nitride film 14 like the second conventional example on the lower wiring in the multilayer wiring structure according to the third conventional example, the number of steps is greatly increased. In addition, there is a problem that the first titanium nitride film 14 cannot be formed stably.

In view of the above, it is an object of the present invention to provide a multilayer wiring structure capable of improving electromigration resistance and achieving further miniaturization without increasing the number of steps. The purpose is to:

[0031]

In order to achieve the above-mentioned object, a first multilayer wiring structure according to the present invention is directed to a multilayer wiring structure in which a lower wiring and an upper wiring are connected by a via contact. The wiring includes a first metal film and the first metal film.
Having a first high melting point metal film formed on the metal film of
The via contact has a second metal film and a second refractory metal film that covers a side wall surface and a bottom surface of the second metal film, and the first refractory metal film has a via under the via contact. The second high melting point metal film has an opening smaller than the planar shape of the contact, the second high melting point metal film has an overhanging portion projecting inward from the lower end of the side wall portion, and a second high melting point metal film overhanging portion. One of the refractory metal films is connected to the peripheral region of the opening.

According to the first multilayer wiring structure, a via hole is formed in the first refractory metal film because an opening smaller than the planar shape of the via contact is formed below the via contact. It is not necessary to stop dry etching for the first refractory metal film, so that the thickness of the first refractory metal film can be reduced.

The overhanging portion of the second refractory metal film is connected to the peripheral region of the opening in the first refractory metal film, and the first refractory metal film has electromigration resistance. Therefore, even if the region under the via contact in the first metal film is eliminated by electromigration, the current flowing from the first metal film of the lower wiring to the second metal film of the via contact is the first high voltage. From the melting point metal film to the second high melting point metal film.

A first method of manufacturing a multilayer wiring structure according to the present invention is directed to a method of manufacturing a multilayer wiring structure in which a lower wiring and an upper wiring are connected by via contacts, and includes a first metal film and the first metal film. Forming a lower wiring having a first refractory metal film formed on the lower metal film, forming an interlayer insulating film on the lower wiring, and then forming the interlayer insulating film and the first refractory metal film Forming a via hole in the interlayer insulating film and forming an opening in the first refractory metal film, and enlarging the planar shape of the via hole to form the first refractory metal. Exposing the peripheral region of the opening in the film to the via hole; forming a second refractory metal film on the bottom and the side wall of the via hole;
The second region on the peripheral region of the opening in the refractory metal film of FIG.
Forming an overhang from the lower end of the side wall portion of the high melting point metal film and connecting to the peripheral region of the opening in the first high melting point metal film; Filling the second metal film to form a via contact having the second metal film and the second refractory metal film.

A second method for manufacturing a multilayer wiring structure according to the present invention is directed to a method for manufacturing a multilayer wiring structure in which a lower wiring and an upper wiring are connected by via contacts, and includes a first metal film and the first metal film. Forming a lower wiring having a first refractory metal film formed on the lower metal film, forming an interlayer insulating film on the lower wiring, and then forming the interlayer insulating film and the first refractory metal film On the other hand, the etching is performed under the condition that the etching rate for the first refractory metal film is lower than the etching rate for the interlayer insulating film to form a via hole in the interlayer insulating film and to form a via hole in the first refractory metal film. Forming an opening smaller than the planar shape of the via hole; forming a second refractory metal film on the bottom and side walls of the via hole to form a peripheral region of the opening in the first refractory metal film; upon Forming an overhang from the lower end of the side wall of the second refractory metal film and connecting to a peripheral region of the opening in the first refractory metal film; Forming a via contact having a second metal film and a second high melting point metal film by filling a second metal film inside the substrate.

The second multilayer wiring structure according to the present invention is directed to a multilayer wiring structure in which a lower wiring and an upper wiring are connected by a via contact, and the lower wiring is formed of a first metal embedded in an insulating film. A first refractory metal film covering the side wall surface and the bottom surface of the first metal film; and a via contact covering the second metal film and the side wall surface and the bottom surface of the second metal film. 2 high melting point metal film, the bottom of the via contact is located lower than the upper surface of the lower wiring,
The portion of the second refractory metal film that forms the bottom of the via contact is connected to the side wall or the bottom of the first refractory metal film.

According to the second multilayer wiring structure, the bottom of the via contact is located lower than the upper surface of the lower wiring, and the portion forming the bottom of the via contact in the second refractory metal film and the first contact are formed. And the first refractory metal film has high electromigration resistance, so that the region below the via contact in the first metal film is electromigrated. Even if it disappears,
The current flowing from the first metal film to the second metal film of the via contact goes from the first high melting point metal film to the second high melting point metal film.

The third method of manufacturing a multilayer wiring structure according to the present invention is directed to a method of manufacturing a multilayer wiring structure in which a lower wiring and an upper wiring are connected by via contacts, and is a method of manufacturing a multilayer wiring structure embedded in an insulating film. Forming a lower wiring having a first refractory metal film covering the side wall surface and bottom surface of the first metal film, and forming an interlayer insulating film on the lower wiring, And etching the insulating film under the condition that the etching rate for the interlayer insulating film and the insulating film is higher than the etching rate for the first refractory metal film, so that the via hole is formed in the interlayer insulating film and the bottom of the via hole is formed. A step of exposing the side wall of the first high melting point metal film to the bottom of the via hole and forming a second high melting point on the bottom and side wall of the via hole; Shokumaku a film of a portion located at the bottom of the via hole in the second refractory metal film, the first
Connecting the second refractory metal film to the side wall portion, and filling the second refractory metal film inside the second refractory metal film to have a second metal film and a second refractory metal film. Forming a via contact.

A fourth method of manufacturing a multilayer wiring structure according to the present invention is directed to a method of manufacturing a multilayer wiring structure in which a lower wiring and an upper wiring are connected by via contacts, and is a method of manufacturing a multilayer wiring structure in which a first wiring is embedded in an insulating film. Forming a lower wiring having a first refractory metal film covering the side wall surface and bottom surface of the first metal film, and forming an interlayer insulating film on the lower wiring, And sequentially etching the first metal film to form a via hole in the interlayer insulating film such that the bottom of the via hole is located inside the first metal film. Second on side wall
Forming a high-melting-point metal film, and connecting a portion of the second high-melting-point metal film located at the bottom of the via hole to a side wall or bottom of the first high-melting-point metal film; Forming a via contact having the second metal film and the second high melting point metal film by filling the inside of the high melting point metal film with a second metal film.

[0040]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) Hereinafter, a multilayer wiring structure according to a first embodiment will be described with reference to FIG.

As shown in FIG. 1, an insulating film 101 is formed on a semiconductor substrate 100 on which a plurality of functional elements are formed, and a lower wiring A is formed on the insulating film 101. The lower wiring A is a first titanium film 102, a first titanium nitride film 103, and a first A in which 0.5 to 2.0 wt% of copper is contained in aluminum.
It comprises an l-Cu film 104, a second titanium film 105, and a second titanium nitride film 106 serving as an anti-reflection film. In the first embodiment, the first Al-
The Cu film 104 constitutes a first metal film, and the second titanium nitride film 106 constitutes a first refractory metal film.

An interlayer insulating film 107 is formed on the insulating film 101 including on the lower wiring A.
A via contact B is formed in a via hole 108 provided in the reference numeral 07. The via contact B includes a first adhesion layer 109 made of a titanium film, a second adhesion layer 110 made of a titanium nitride film, and a tungsten plug 111 made of a tungsten film, which are sequentially formed from the outside. In the first embodiment, the tungsten film forms the second metal film, and the titanium film and the titanium nitride film form the second refractory metal film. May be a single layer.

An upper wiring C is formed on the interlayer insulating film 107 including the upper part of the via contact B. The upper wiring C is formed of a third titanium film 112, No. 3 titanium nitride film 113, second Al-Cu containing 0.5 to 2.0 wt% of copper in aluminum
It is composed of a film 114, a fourth titanium film 115, and a fourth titanium nitride film 116 serving as an anti-reflection film.
The upper wiring C and the lower wiring A are connected via via contacts B.

As a feature of the first embodiment, the lower wiring A
An opening smaller than the planar shape of the via contact B is formed in a region below the via contact B in the second titanium film 105 and the second titanium nitride film 106 constituting , The second titanium film 105 and the second titanium nitride film 106 are directly connected to the first Al-Cu film 104 at the openings.

The first and second adhesion layers 109 and 11
Numeral 0 has a projecting portion projecting inward from the lower end of the side wall portion, and the projecting portion is connected to a region around the opening in the second titanium nitride film 106.

Hereinafter, a method for manufacturing the multilayer wiring structure according to the first embodiment will be described with reference to FIGS.

First, as shown in FIG. 2A, an insulating film 10 is formed on a semiconductor substrate 100 on which a plurality of functional elements are formed.
1, a first titanium film 102 having a thickness of, for example, 40 nm, for example, a first titanium film having a thickness of 20 nm, which is sequentially deposited on the insulating film 101 by a sputtering method.
Titanium nitride film 103, 0.5 to 2.0 on aluminum
a first layer having a thickness of, for example, 450 nm, which contains
Al-Cu film 104, for example, a second film having a thickness of 5 nm.
A first laminated film composed of the titanium film 105 and a second titanium nitride film 106 having a thickness of, for example, 30 nm and serving as an anti-reflection film is deposited. The second titanium film 105 is formed in order to reduce the contact resistance between the first Al—Cu film 104 and the second titanium nitride film 106, and a part of the second titanium film 105 is formed in a later heat treatment step. 1 reacts with the Al-Cu film 104 to form an alloy layer of aluminum and titanium. Next, after photolithography and dry etching are performed on the first stacked film to pattern the first stacked film, a heat treatment is performed at a temperature of, for example, 400 ° C. for 10 minutes, and the patterned first stacked film is formed. A lower wiring A made of a laminated film is formed.

Next, a silicon oxide film is formed on the insulating film 101 including the lower wiring A by the plasma CVD method, and the silicon oxide film is flattened by the CMP method to form an interlayer insulating film 107. I do. Next, the interlayer insulating film 107
After forming a resist pattern thereon, dry etching is performed using the resist pattern as a mask to form a via hole 108 in the interlayer insulating film 107. next,
After the resist pattern is removed by oxygen plasma, cleaning for removing the polymer attached to the side wall and the bottom of the via hole 108 in a dry etching process is performed. In this cleaning step, the second titanium nitride film 1
06 and the second titanium film 105 are removed.
The titanium nitride film 106 and the second titanium film 105 may remain.

Next, the side wall portion of the via hole 108 in the interlayer insulating film 107 is removed by about 30 nm by performing wet etching using an etching solution such as ammonium fluoride on the interlayer insulating film 107, thereby obtaining FIG. As shown in b), the planar shape of the via hole 108 is enlarged, and the region around the opening in the second titanium nitride film 106 is exposed to the via hole 108.

The etching solution is not limited to ammonium fluoride, and the etching rate for the interlayer insulating film 107 is etching for the second titanium nitride film 106, the second titanium film 105, and the first Al-Cu film 104. A rate larger than the rate can be used, and isotropic dry etching may be performed instead of wet etching.

Further, the cleaning step for removing the polymer adhered to the side wall and the bottom of via hole 108 and the etching step for interlayer insulating film 107 may be performed in the same step.

Next, after removing a natural oxide film formed in a region of the surface of the first Al—Cu film 104 exposed to the via hole 108 by a reverse sputtering method using argon plasma, the via hole 108 is removed. On the entire surface of the interlayer insulating film 107 including the inside, a titanium film serving as a first adhesion layer and a second
After depositing a titanium nitride film to be an adhesion layer of
A tungsten film is deposited by the D method. Since the peripheral region of the opening in the second titanium nitride film 206 is exposed to the via hole 108, an extension is formed in the titanium film and the titanium nitride film so as to extend inward from the lower end of the side wall.

Next, portions of the titanium film, the titanium nitride film, and the tungsten film, which are exposed on the interlayer insulating film 107, are removed by, for example, a CMP method, and the first adhesion layer 109 made of a titanium film and the titanium nitride film are removed. Contact B composed of a second adhesion layer 110 made of a film and a tungsten plug 111 made of a tungsten film
To form

By the way, the enlarged via hole 108
Is 0.3 μm and the depth is 0.7 μm, a titanium film having a thickness of 20 nm is deposited by a collimation method (collimation sputtering method) (collimator aspect ratio: 1.5), and then a 100 nm film is deposited. When a titanium nitride film having a thickness of 300 nm and a tungsten film having a thickness of 300 nm are deposited, a titanium film having a thickness of about 10 nm is formed at the bottom of the via hole 108. Layer 109)
Second titanium nitride film 106 and first Al-Cu film 10
4 can be stably contacted.

Next, after removing a natural oxide film formed on the surface of the tungsten plug 111 by a reverse sputtering method using argon plasma, a sputtering method is used.
A third titanium film 112 having a thickness of, for example, 40 nm, a third titanium nitride film 113 having a thickness of, for example, 20 nm, and
A second Al—Cu film 114 containing 2.0 wt% of copper and having a thickness of, for example, 450 nm, a fourth titanium film 115 having a thickness of, for example, 5 nm, and an antireflection film having a thickness of, for example, 30 nm A second laminated film composed of a fourth titanium nitride film 116 to be formed is deposited. Next, after photolithography and dry etching are performed on the second laminated film to pattern the second laminated film, a heat treatment is performed, for example, at a temperature of 400 ° C. for 10 minutes to obtain a second laminated film. Is formed.

According to the first embodiment, the interlayer insulating film 10
In order to enlarge the planar shape of the via hole 108 by etching the side wall portion of the via hole 108 in FIG. 7, the peripheral region of the opening in the second titanium nitride film 106 is surely exposed to the bottom of the via hole 108. In addition, the natural oxide film and the polymer formed on the surface of the second titanium nitride film 106 can be surely removed by the cleaning liquid or the argon plasma.

Also, the first and second adhesion layers 109 and 11
The coverage at the bottom of via hole 108 at 0 is
Since the coverage is sufficiently better than the coverage of the side wall of the via hole 108, a stable contact between the first and second adhesion layers 109 and 110 and the first Al-Cu film 104, and the first and second adhesion A stable contact between the layers 109 and 110 and the second titanium nitride film 106 can be realized.

Also, the first and second adhesion layers 109 and 11
10B is connected to the peripheral region of the opening in the second titanium nitride film 106, and therefore, FIG.
As shown in the first conventional example shown in FIG.
The contact area is greatly increased as compared with the case where the contact area is connected to the side wall of the opening, so that the contact resistance can be reduced.

FIG. 3 shows a state in which a void 120 due to electromigration is formed in a region below the via contact B in the first Al-Cu film 104 in the multilayer wiring structure according to the first embodiment. I have.
Via contact B in first Al-Cu film 104
Even if the lower region is lost by electromigration, the second titanium nitride film 106, which is the first refractory metal film, has very high electromigration resistance. It is secured and no disconnection occurs. That is, the current flowing from the tungsten plug 111 to the first Al—Cu film 104 is changed from the first adhesion layer 109 to the second titanium nitride film 106.
In addition, the current flows through the first Al—Cu film 104 via the second titanium film 105 (including an alloy layer of aluminum and titanium), so that the contact resistance increases but no disconnection occurs. Therefore, the multilayer wiring structure according to the first embodiment has improved electromigration resistance.

Further, the first and second adhesion layers 109, 1
Since the overhanging portion 10 is connected to the peripheral region of the opening in the second titanium nitride film 106, it is not necessary to increase the thickness of the second titanium nitride film 106. , And an increase in the inter-wiring capacitance in the lower wiring A can be suppressed.

(Second Embodiment) Hereinafter, a multilayer wiring structure and a method of manufacturing the same according to a second embodiment will be described with reference to FIG.
This will be described with reference to (a) to (c).

As shown in FIG. 4A, similarly to the first embodiment, a first titanium film 202 and a first nitride film are formed on an insulating film 201 formed on a semiconductor substrate 200. After sequentially stacking a titanium film 203, a first Al-Cu film 204, a second titanium film 205, and a second titanium nitride film 206, the stacked film is patterned to form a lower wiring A. In the second embodiment, the first Al—Cu film 204 forms a first metal film, and the second titanium nitride film 206 forms a first refractory metal film.

Next, the insulating film 201 including the upper part of the lower wiring A is formed.
After the interlayer insulating film 207 is deposited on the
07 is flattened.

Next, after forming a resist pattern 208 on the interlayer insulating film 207, the resist pattern 208
Is used as a mask to dry etch the interlayer insulating film 207, the second titanium nitride film 206, and the second titanium film 205 to form a via hole 209.
In this dry etching, the etching rate for the second titanium nitride film 206 and the second titanium film 205 is lower than the etching rate for the interlayer insulating film 207, for example, etching using a gas system of C ₅ F ₈ + CHF ₃ + Ar. Perform under conditions. When dry etching is performed under such conditions, the polymer 210 adheres to the side wall of the via hole 209 in the interlayer insulating film 207. 2 titanium nitride film 20
At the time of etching (shown in FIG. 4B) on the sixth titanium film 205 and the second titanium film 205, the amount of the polymer 210 to be attached increases, and the etching in the lateral direction is suppressed. For this reason, as shown in FIG. 4B, openings are formed in the second titanium nitride film 206 and the second titanium film 205 to expose the first Al—Cu film 204, and
The region around the opening in the titanium nitride film 206 has a tapered shape in which the film thickness decreases toward the opening. Accordingly, a tapered shape can be formed in a self-aligned manner in the peripheral region of the opening in the second titanium nitride film 206.

Next, after removing the resist pattern 208 by ashing using oxygen plasma, the polymer 210 adhering to the side wall surface of the via hole 209 is removed by washing, and thereafter, by reverse sputtering using argon plasma, The natural oxide film formed on the surface of the first Al-Cu film 204 is removed.

Next, as shown in FIG. 4C, a titanium film serving as a first adhesion layer is formed over the entire surface of the interlayer insulating film 207 including the inside of the via hole 209 by, for example, sputtering. After depositing the titanium nitride film serving as the second adhesion layer, a tungsten film is deposited by, for example, a CVD method. Since the peripheral region of the opening in the second titanium nitride film 206 has a tapered shape, an extension is formed in the titanium film and the titanium nitride film so as to extend inward from the lower end of the side wall. In the second embodiment, the tungsten film forms the second metal film, and the titanium film and the titanium nitride film form the second refractory metal film. May be a single layer.

Next, portions of the titanium film, the titanium nitride film, and the tungsten film, which are exposed on the interlayer insulating film 207, are removed by, for example, a CMP method, and the first adhesion layer 211 made of a titanium film and the titanium nitride film are removed. Contact B composed of a second adhesion layer 212 made of a film and a tungsten plug 213 made of a tungsten film
To form

By the way, the diameter of the via hole 209 is set to 0.
If the depth is 3 μm and the depth is 0.7 μm, a titanium film having a thickness of 20 nm is deposited by a collimation method (collimation sputtering method) (collimator aspect ratio: 1.5), and then a nitride film having a thickness of 100 nm is deposited. When a titanium film and a tungsten film having a thickness of 300 nm are deposited, 10n is formed at the bottom of the via hole 209.
Since a titanium film having a thickness of about m is formed,
The titanium film (first adhesion layer 211) can make stable contact with the second titanium nitride film 206 and the first Al-Cu film 204.

Next, similarly to the first embodiment, a third titanium film, a third titanium nitride film, a second Al—Cu film, and a fourth titanium film are formed on the interlayer insulating film 207. After depositing a second laminated film composed of a fourth titanium nitride film to be an anti-reflection film, the second laminated film is patterned to form an upper wiring C composed of the second laminated film. .

According to the second embodiment, the via hole 2
09, the second titanium nitride film 206 can be reliably exposed at the bottom, and a natural oxide film and a polymer formed on the surface of the second titanium nitride film 206 are surely removed by a cleaning liquid or argon plasma. Can be.

The first and second adhesion layers 211 and 21
2, the coverage at the bottom of the via hole 209 is:
Since the coverage is sufficiently better than the coverage of the side wall portion of the via hole 209, a stable contact between the first and second adhesion layers 211 and 212 and the first Al-Cu film 204, and the first and second adhesion A stable contact between the layers 211 and 212 and the second titanium nitride film 206 can be realized.

The first and second adhesion layers 211 and 21
2 and a second titanium nitride film 20.
6 is connected to the peripheral region of the opening, so that it is connected to the side wall of the opening in the first titanium nitride film 14 as in the first conventional example shown in FIG. Since the contact area is greatly increased, the contact resistance can be reduced.

Even if the region under the via contact in the first Al—Cu film 204 is lost by electromigration, the second titanium nitride film 206 as the first refractory metal film has electromigration resistance. Since it is very high, the connection between the via contact B and the lower wiring A is secured, and no disconnection occurs. That is,
From the tungsten plug 213 to the first Al-Cu film 20
4 flows from the first adhesion layer 211 through the second titanium nitride film 206 and the second titanium film 205 (including an alloy layer of aluminum and titanium).
Flows through the Al-Cu film 204, the contact resistance increases but no disconnection occurs. Therefore, the multilayer wiring structure according to the second embodiment has improved electromigration resistance.

Further, since it is not necessary to increase the thickness of the second titanium nitride film 206, it is possible to suppress the difficulty in processing the lower wiring A and the increase in inter-wiring capacitance in the lower wiring A.

(Third Embodiment) Hereinafter, a multilayer wiring structure according to a third embodiment will be described with reference to FIG.

As shown in FIG. 5, a first insulating film 301 and a second insulating film 302 are formed on a semiconductor substrate 300 on which a plurality of functional elements are formed.
Is formed with a buried lower wiring A. The lower wiring A is formed of a first tantalum nitride film 303 serving as a barrier film.
And a first copper film 304. An interlayer insulating film 306 is formed on the lower wiring A and the second insulating film 302 via a first silicon nitride film (SiN _x ) 305 serving as a copper diffusion preventing film. Is formed with a via contact B and an upper wiring C having a dual damascene structure, and the via contact B and the upper wiring C are formed on the second tantalum nitride film 30 serving as a barrier film.
7 and a second copper film 308. Also,
On the upper wiring C and the interlayer insulating film 306, a second silicon nitride film 309 serving as a copper diffusion preventing film is formed.

As a feature of the third embodiment, the via contact B projects to the side of the lower wiring A, and the second tantalum nitride film 30 at the projecting portion of the via contact B is formed.
7 and the first tantalum nitride film 30 constituting the lower wiring A
3 is connected to the side surface.

Hereinafter, a method for manufacturing a multilayer wiring structure according to the third embodiment will be described with reference to FIGS. 6 (a), 6 (b) and 7.

First, as shown in FIG. 6A, a first insulating film 301 and a second insulating film 302 are sequentially formed on a semiconductor substrate 300 on which a plurality of functional elements are formed, and then photolithography is performed. Then, a wiring groove is formed in the second insulating film 302 by dry etching. Next, CVD is performed on the entire surface of the second insulating film 302 including the inside of the wiring groove.
After a first tantalum nitride film 303 serving as a barrier film is formed by a sputtering method, a seed layer (not shown) made of a copper film is formed by a sputtering method. In order to improve the surface morphology, the seed layer is formed at a temperature equal to or lower than room temperature, and is formed so as to be a continuous film at the bottom and side walls of the wiring groove. For example, if the width of the wiring groove is 0.2 μm
When the depth is 0.3 μm, the thickness in the flat portion is about 10 nm in the first tantalum nitride film 303 and about 100 nm in the seed layer. Is formed.

Next, after a first copper film 304 is formed on the seed layer by an electrolytic plating method using copper sulfate, an inert gas (for example, argon (Ar) gas) and a nitrogen (N ₂ ) gas are used. Alternatively, a crystal is grown by performing a heat treatment at a temperature of 100 to 500 ° C. for about 30 minutes in an atmosphere of a mixed gas of a nitrogen gas and a hydrogen gas. Thus, the seed layer made of the copper film and the first copper film 304 formed by the electrolytic plating method are integrated to form a continuous film. Next, a first tantalum nitride film 303 and a first copper film 304
When the portion exposed on the second insulating film 302 is removed, the lower wiring A including the first tantalum nitride film 303 and the first copper film 304 is formed.

Next, the entire surface of the first copper film 304 and the second insulating film 302 is formed by plasma CVD.
A first silicon nitride film 305 serving as a copper diffusion prevention film is formed. In this case, in order to reduce the copper oxide layer formed on the surface portion of the first copper film 304, a hydrogen gas or an ammonia gas may be supplied before the first silicon nitride film 305 is formed. preferable.

Next, after an interlayer insulating film 306 made of, for example, SiO _{2 is} formed on the first silicon nitride film 305 by a plasma CVD method, the interlayer insulating film 306 is flattened by, for example, a CMP method. .

Next, after a first resist pattern (not shown) having an opening for forming a wiring groove is formed on the interlayer insulating film 306, the first resist pattern is used as a mask. By etching the interlayer insulating film 306, a wiring groove 310 is formed. Next, after removing the first resist pattern by ashing, the attached polymer is removed by washing.

Next, a second resist pattern 3 having an opening for forming a via hole is formed on the interlayer insulating film 306.
After the formation of 11, the second resist pattern 311 is used as a mask to dry-etch the interlayer insulating film 306 to form a via hole 312. In this case, the via hole forming opening of the second resist pattern 311 is shifted from the lower layer wiring A or is enlarged so that the via hole 312 is partially shifted from the lower layer wiring A. In the dry etching step, when the interlayer insulating film 306 and the second insulating film 302 are made of SiO ₂ , the interlayer insulating film 306 is etched using an etching gas made of a fluorine (F) based gas, for example, C ₂ F _6. After that, the first silicon nitride film 305 is etched by switching to a chlorine (Cl ₂ ) -based etching gas, and then switched again to a fluorine-based etching gas so that the side of the lower wiring A in the second insulating film 302 is removed. The part is partially etched. In this case, the first silicon nitride film 305
In the step of etching the second insulating film 302, the first tantalum nitride film 303 exposed during the etching is prevented from being excessively etched by using etching conditions having selectivity with respect to the first tantalum nitride film 303. To

Next, after removing the second resist pattern 311 by ashing, the polymer adhering to the bottom and side walls of the via hole 312 is removed by washing, and thereafter, the reverse sputtering method using argon plasma is performed. The natural oxide film formed on the surface of the first copper film 304 is removed.

Next, as shown in FIG.
10 and interlayer insulating film 3 including the inside of via hole 312
After a second tantalum nitride film 307 serving as a barrier film is formed on the entire surface of the substrate 06 by a CVD method, a seed layer 313 made of a copper film is formed by a sputtering method. In this case, since the second tantalum nitride film 307 is formed by the CVD method, a conformal film can be obtained. Therefore, the second tantalum nitride film 307 is exposed to the via hole 312 on the side surface of the first tantalum nitride film 303 forming the lower wiring A. A sufficient film thickness can be ensured even in the portion.

Next, as shown in FIG. 7, after a second copper film 308 is formed on the seed layer 313 by an electrolytic plating method using copper sulfate, an inert gas (eg, argon gas) A crystal is grown by performing a heat treatment at a temperature of 100 to 500 ° C. for about 30 minutes in an atmosphere of a gas or a mixed gas of a nitrogen gas and a hydrogen gas to grow the seed layer 31.
3 and the second copper film 308 are integrated. Next, portions of the second tantalum nitride film 307 and the second copper film 308 exposed above the interlayer insulating film 306 are removed by a CMP method, and the second tantalum nitride film 307 and the second copper film 308 are removed. A via contact B and an upper wiring C made of the film 308 are formed.

Next, after reducing the copper oxide layer formed on the surface of the second copper film 308, the plasma CV is applied over the entire surface of the second copper film 308 and the interlayer insulating film 306.
By a method D, a second silicon nitride film 309 serving as a copper diffusion prevention film is formed.

According to the third embodiment, via holes 3
The first tantalum nitride film 303 can be reliably exposed to the side of the lower wiring A at the bottom of the twelve.

Further, the first tantalum nitride film 303 is connected to the second tantalum nitride film 307 not only on the top surface but also on the side surface, that is, the first tantalum nitride film 303
Although the width (film thickness) of the upper surface of this is very small, about 5 nm, since the side surface of the first tantalum nitride film 303 is connected to the second tantalum nitride film 307, the contact area is greatly increased. The contact resistance can be reduced.

Further, as shown in FIG.
4, the first tantalum nitride film 303, which is a refractory metal film, has a very high electromigration resistance even if the void 320 is formed by electromigration in the region below the via contact B in FIG. The connection with the wiring A is ensured and no disconnection occurs. That is, the current flowing from the second copper film 308 to the first copper film 304 is changed by the second tantalum nitride film 307.
Flows through the first copper film 304 via the first tantalum nitride film 303, the contact resistance increases but no disconnection occurs. Therefore, the multilayer wiring structure according to the third embodiment has improved electromigration resistance.

Furthermore, the number of steps can be reduced as compared with the first or second embodiment in which a barrier film is formed above the lower wiring A, so that the electromigration resistance can be improved efficiently.

(Fourth Embodiment) Hereinafter, a multilayer wiring structure and a method of manufacturing the same according to a fourth embodiment will be described with reference to FIG.
This will be described with reference to (a) to (c).

As shown in FIG. 8A, a first insulating film 4 is formed on a semiconductor substrate 400 in the same manner as in the third embodiment.
After the first and second insulating films 402 are sequentially formed, a wiring groove is formed in the second insulating film 402. Next, CVD is performed on the entire surface of the second insulating film 402 including the inside of the wiring groove.
The first tungsten nitride (W
After forming the N) 403, a seed layer (not shown) made of a copper film is formed by a sputtering method. In order to improve the surface morphology, the seed layer is formed at a temperature equal to or lower than room temperature, and is formed so as to be a continuous film at the bottom and side walls of the wiring groove. For example, when the width of the wiring groove is 0.2 μm and the depth is 0.3 μm, the thickness of the first tungsten nitride film 403 in the flat portion is 35 μm.
When the film is formed to a thickness of about nm and the seed layer is formed to a thickness of about 130 nm, the film is formed to a thickness of about 5 nm on the side wall of the wiring groove.

Next, after a first copper film 404 is formed on the seed layer by an electrolytic plating method using copper sulfate, an inert gas, a nitrogen gas, or a mixed gas of a nitrogen gas and a hydrogen gas is used. 3 at a temperature of 100 to 500 ° C in the atmosphere
By performing a heat treatment for about 0 minutes to grow the crystal, and then removing portions of the first tungsten nitride film 403 and the first copper film 404 which are exposed on the second insulating film 402, the first A lower wiring A composed of the tungsten nitride film 403 and the first copper film 404 is formed.

Next, the entire surface of the first copper film 404 and the second insulating film 402 is formed by a plasma CVD method.
After a first silicon nitride film 405 serving as a copper diffusion preventing film is formed, an interlayer insulating film 406 made of, for example, SiO _{2 is} formed on the first silicon nitride film 405 by a plasma CVD method. After that, the interlayer insulating film 406 is planarized by, for example, a CMP method.

Next, a first resist pattern 407 having an opening for forming a wiring groove is formed on the interlayer insulating film 406, and the first resist pattern 407 is used as a mask to form the first resist pattern 407 on the interlayer insulating film 406. On the other hand, a via hole 408 is formed by performing dry etching. In this case, the wall surface of the via hole 408 is
03 or is located on the wall of the first tungsten nitride film 403. In the dry etching step, the interlayer insulating film 406 is made of SiO ₂
In the case where the first silicon nitride film 405 is formed by using an etching gas composed of a fluorine-based gas, for example, C ₂ F ₆ , the first silicon nitride film 405 is provided with selectivity. End the etching. Next, after removing the first resist pattern 407 by ashing, the attached polymer is removed by washing.

Next, after a second resist pattern (not shown) having an opening for forming a via hole is formed on the interlayer insulating film 406, the second resist pattern is used as a mask. Then, dry etching is performed on the interlayer insulating film 406, as shown in FIG.
A wiring groove 409 is formed. In this dry etching process, by using a fluorine-based gas, for example, an etching gas consisting of C ₂ F _6, the first silicon nitride film 40
5, the first silicon nitride film 4
05 is not etched. Next, after removing the second resist pattern by ashing, the attached polymer is removed by washing.

Next, the first silicon nitride film 405 and the first copper film 404 are dry-etched by using the interlayer insulating film 406 as a mask and using a chlorine-based etching gas. The inner wall surface of the tungsten film 403 is exposed. In this case, since a chlorine-based etching gas is used, the etching rates for the interlayer insulating film 406 and the first tungsten nitride film 403 are lower than the etching rates for the first silicon nitride film 405 and the first copper film 404. Therefore, the interlayer insulating film 40
6 and via holes 408 and wiring grooves 40
9 and the first tungsten nitride film 403 are hardly etched, and a desired shape can be maintained. Next, after the polymer adhering to the via hole 408 and the bottom and side wall of the wiring groove 409 in the dry etching process is removed by ashing and washing, the first copper film 404 is formed by reverse sputtering using argon plasma.
The natural oxide film formed on the surface of the substrate is removed.

Next, as shown in FIG. 8C, the interlayer insulating film 4 including the inside of the via hole 408 and the wiring groove 409 is formed.
After a second tungsten nitride 410 serving as a barrier film is formed on the entire surface of the substrate 06 by a CVD method, a seed layer (not shown) made of a copper film is formed by a sputtering method. In this case, since the second tungsten nitride film 410 is formed by the CVD method, a conformal film can be obtained. Therefore, the via holes 40 on the side surfaces of the first tungsten nitride film 403 forming the lower wiring A are formed.
A sufficient film thickness can be ensured even in the portion exposed to the portion 8.

Next, after a second copper film 411 is formed by an electrolytic plating method using copper sulfate, the second copper film 411 is formed in an atmosphere of an inert gas, a nitrogen gas, or a mixed gas of a nitrogen gas and a hydrogen gas. A crystal growth is performed by performing a heat treatment at a temperature of 500 ° C. for about 30 minutes, and then a portion of the second tungsten nitride film 410 and the second copper film 411 exposed on the interlayer insulating film 406 is subjected to the CMP method. To form a via contact B and an upper wiring C composed of the second tungsten nitride film 410 and the second copper film 411.

Next, after the copper oxide layer formed on the surface of the second copper film 411 is reduced, the plasma CV is formed on the entire surface of the second copper film 411 and the interlayer insulating film 406.
By a method D, a second silicon nitride film 412 to be a copper diffusion prevention film is formed.

According to the fourth embodiment, the via hole 4
08, the first tungsten nitride film 403 can be reliably exposed at the side wall of the lower wiring A.

Further, since the side surface is connected to the second tungsten nitride film 410 in addition to the upper surface of the first tungsten nitride film 403, that is, the width (film thickness) of the upper surface of the first tungsten nitride film 403 Is as small as about 5 nm, but since the side surface of the first tungsten nitride film 403 is connected to the second tungsten nitride film 410,
Since the contact area is greatly increased, the contact resistance can be reduced.

Even if a void is formed by electromigration in the region below the via contact B in the first copper film 404, the first melting point metal film
Since the tungsten nitride film 403 has very high electromigration resistance, the connection between the via contact B and the lower wiring A is secured, and no disconnection occurs. That is,
The current flowing from the second copper film 411 to the first copper film 404 flows from the second tungsten nitride film 410 to the first copper film 404 via the first tungsten nitride film 403. Ascends but no disconnection occurs. Therefore, the multilayer wiring structure according to the fourth embodiment has improved electromigration resistance.

Furthermore, the number of steps can be reduced as compared with the first or second embodiment in which a barrier film is formed above the lower layer wiring A, so that the electromigration resistance can be improved efficiently.

In the fourth embodiment, the first copper film 404 is dry-etched. Instead, the first tungsten film 403 and the interlayer insulating film 406 are selectively etched. The first copper film 404 may be wet-etched using an etchant having a property.

(Modification of Fourth Embodiment) Hereinafter, a multilayer wiring structure and a method of manufacturing the same according to a modification of the fourth embodiment will be described with reference to FIGS. 9 (a) and 9 (b).

As shown in FIG. 9A, a first insulating film 4 is formed on a semiconductor substrate 400 in the same manner as in the fourth embodiment.
After the first and second insulating films 402 are sequentially formed, a lower wiring A including a first tungsten nitride film 403 and a first copper film 404 is formed on the second insulating film 402. Next, a first silicon nitride film 405 and an interlayer insulating film 406 are formed over the entire surface of the first copper film 404 and the second insulating film 402, and then the interlayer insulating film 406 is planarized. I do.

Next, the via hole 4 is formed in the interlayer insulating film 406.
08 and the wiring groove 409, the first silicon nitride film 405 and the first copper film 404 are dry-etched using the interlayer insulating film 406 as a mask and using a chlorine-based etching gas. The bottom of the first tungsten nitride film 403 is exposed.

Next, as shown in FIG. 9B, the interlayer insulating film 4 including the inside of the via hole 408 and the wiring groove 409 is formed.
06, the entire surface of the second tungsten nitride 41
After the first and second copper films 411 are formed, portions of the second tungsten nitride film 410 and the second copper film 411 exposed on the interlayer insulating film 406 are removed by a CMP method. A via contact B and an upper wiring C composed of the second tungsten nitride film 410 and the second copper film 411 are formed.

Next, the second copper film 411 and the interlayer insulating film 4
A second silicon nitride film 412 serving as a copper diffusion prevention film is formed on the entire surface of the semiconductor substrate 06.

According to the modification of the fourth embodiment, the second tungsten nitride film 41 forming the via contact B is formed.
0 is connected to the bottom of the first tungsten nitride film 403 constituting the lower wiring A, so that the wall surface of the via hole 408 is formed by the first tungsten nitride film 403 as in the fourth embodiment. It is not necessary to set so as to coincide with the inner wall surface or to be located on the wall portion of the first tungsten nitride film 403. For this reason, the via contact B can be formed on the central portion of the lower wiring A having a wide wiring width, so that the layout of the via contact B is increased in flexibility.

[0114]

According to the first multilayer wiring structure, the thickness of the first refractory metal film can be reduced, so that the thickness of the lower wiring can be reduced and the lower wiring can be formed. Therefore, the thickness of the resist pattern can be reduced, so that the multilayer wiring structure can be further miniaturized.

Even if the region below the via contact in the first metal film disappears due to the electromigration, the current flowing from the second metal film of the via contact to the first metal film of the lower wiring is the first metal film. The high refractory metal film moves from the high refractory metal film to the second refractory metal film, so that even if the contact resistance increases, the disconnection does not occur, so that the electromigration resistance is improved.

According to the first method for manufacturing a multilayer wiring structure,
After the planar shape of the via hole formed in the interlayer insulating film is enlarged to expose the peripheral region of the opening in the first refractory metal film to the via hole, second via holes are formed at the bottom and side walls of the via hole. In order to form the high melting point metal film, a projecting portion extending inward from the side wall portion in the second high melting point metal film forming the via contact, and an opening in the first high melting point metal film forming the lower wiring Can be reliably manufactured without increasing the number of steps.

According to the second method of manufacturing a multilayer wiring structure,
A via hole is formed in the interlayer insulating film because the etching is performed on the interlayer insulating film and the first refractory metal film under the condition that the etching rate for the first refractory metal film is lower than the etching rate for the interlayer insulating film. At this time, an opening smaller than the planar shape of the via hole can be formed in the first refractory metal film. Thereafter, in order to form a second refractory metal film on the bottom and the side wall of the via hole, a projecting portion projecting inward from the side wall of the second refractory metal film forming the via contact;
The first multilayer wiring structure connected to the peripheral region of the opening in the first refractory metal film constituting the lower wiring can be reliably manufactured without increasing the number of steps.

According to the second multilayer wiring structure, even if the region under the via contact in the first metal film disappears due to the electromigration, the second metal film of the via contact changes from the first metal film of the lower wiring. Current flows from the first refractory metal film to the second refractory metal film, so that even if the contact resistance increases, the disconnection does not occur, so that the electromigration resistance is improved.

According to the third method of manufacturing a multilayer wiring structure,
Since the etching is performed on the interlayer insulating film and the insulating film under the condition that the etching rate for the interlayer insulating film and the insulating film is higher than the etching rate for the first refractory metal film, the bottom of the via hole is insulated from the interlayer insulating film. The via hole can be formed so as to be located inside the film, and the side wall of the first refractory metal film can be exposed at the bottom of the via hole. After that, the second refractory metal film is formed on the bottom and side walls of the via hole, so that a portion forming the bottom of the via contact in the second refractory metal film and the side wall of the first refractory metal film are formed. The second multilayer wiring structure connected to the parts can be reliably manufactured without increasing the number of steps.

According to the fourth method of manufacturing a multilayer wiring structure,
Etching is sequentially performed on the interlayer insulating film and the first metal film to form a via hole in the interlayer insulating film such that the bottom of the via hole is located inside the first metal film. In order to form the second refractory metal film on the bottom and the side wall, the portion forming the bottom of the via contact in the second refractory metal film and the side wall or the bottom of the first refractory metal film are formed. The connected second multilayer wiring structure can be surely manufactured without increasing the number of steps.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a multilayer wiring structure according to a first embodiment.

FIGS. 2A, 2B, and 2C are cross-sectional views illustrating respective steps of a method for manufacturing a multilayer wiring structure according to the first embodiment.

FIG. 3 is a cross-sectional view illustrating an effect of the multilayer wiring structure according to the first embodiment.

FIGS. 4A, 4B, and 4C are cross-sectional views illustrating respective steps of a method for manufacturing a multilayer wiring structure according to a second embodiment.

FIG. 5 is a cross-sectional view of a multilayer wiring structure according to a third embodiment.

FIGS. 6A and 6B are cross-sectional views illustrating respective steps of a method for manufacturing a multilayer wiring structure according to a third embodiment.

FIG. 7 is a cross-sectional view illustrating an effect of the multilayer wiring structure according to the third embodiment.

FIGS. 8A, 8B, and 8C are cross-sectional views illustrating respective steps of a method for manufacturing a multilayer wiring structure according to a fourth embodiment.

FIGS. 9A and 9B are cross-sectional views illustrating respective steps of a method for manufacturing a multilayer wiring structure according to a modification of the fourth embodiment.

FIGS. 10A and 10B are cross-sectional views showing steps of a method for manufacturing a multilayer wiring structure according to a first conventional example.

FIG. 11 is a cross-sectional view showing one step of a method for manufacturing a multilayer wiring structure according to a second conventional example.

FIGS. 12 (a), (b) and (c) are cross-sectional views showing steps of a method for manufacturing a multilayer wiring structure according to a third conventional example.

13 (a), (b) and (c) show the rate of increase in resistance over time in the multilayer wiring structure according to the first conventional example, the second conventional example, and the third conventional example. FIG.

FIGS. 14A, 14B and 14C show a case where voids are formed by electromigration in the multilayer wiring structure according to the second conventional example, the first conventional example, and the third conventional example. FIG. 4 is a cross-sectional view illustrating the flow of current.

[Explanation of symbols]

 Reference Signs List A lower wiring B via contact C upper wiring 100 semiconductor substrate 101 insulating film 102 first titanium film 103 first titanium nitride film 104 first Al-Cu film 105 second titanium film 106 second titanium nitride film 107 Interlayer insulating film 108 Via hole 109 First adhesion layer 110 Second adhesion layer 111 Tungsten plug 112 Third titanium film 113 Third titanium nitride film 114 Second Al-Cu film 115 Fourth titanium film 116 First 4 titanium nitride film 120 void 200 semiconductor substrate 201 insulating film 202 first titanium film 203 first titanium nitride film 204 first Al-Cu film 205 second titanium film 206 second titanium nitride film 207 interlayer insulation Film 208 resist pattern 209 via hole 210 Marker 211 First adhesion layer 212 Second adhesion layer 213 Tungsten plug 300 Semiconductor substrate 301 First insulation film 302 Second insulation film 303 First tantalum nitride film 304 First copper film 305 First silicon nitride Film 306 interlayer insulating film 307 second tantalum nitride film 308 second copper film 309 second silicon nitride film 310 wiring groove 311 second resist pattern 312 via hole 313 seed layer 320 void 400 semiconductor substrate 401 first insulation Film 402 second insulating film 403 first tungsten nitride film 404 first copper film 405 first silicon nitride film 406 interlayer insulating film 407 first resist pattern 408 via hole 409 wiring groove 410 second tungsten nitride film 411 second copper film 412 second silicon nitride film

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (6)

[Claims] 1. A multilayer wiring structure in which a lower wiring and an upper wiring are connected by a via contact, wherein the lower wiring comprises a first metal film and a first metal film formed on the first metal film. Wherein the via contact has a second metal film and a second high melting point metal film which covers a side wall surface and a bottom surface of the second metal film, and wherein the first high melting point The metal film has an opening below the via contact and smaller than the planar shape of the via contact, and the second refractory metal film has an overhang that projects inward from the lower end of the side wall. The overhanging portion of the second refractory metal film is connected to a peripheral region of an opening in the first refractory metal film. 2. A method for manufacturing a multilayer wiring structure in which a lower wiring and an upper wiring are connected by a via contact, comprising: a first metal film and a first metal film formed on the first metal film.
Forming a lower wiring having a high melting point metal film, and forming an interlayer insulating film on the lower wiring, etching the interlayer insulating film and the first high melting point metal film, Forming a via hole in the interlayer insulating film and forming an opening in the first refractory metal film; and enlarging a planar shape of the via hole to form the opening in the first refractory metal film. Exposing a peripheral region of the via hole to the via hole; forming a second refractory metal film on a bottom portion and a side wall portion of the via hole to form a peripheral region of the first refractory metal film around the opening Forming an overhanging portion overlying the lower refractory metal film from the lower end of the side wall portion of the second refractory metal film and connecting to a peripheral region of the opening in the first refractory metal film; Second refractory metal Filling a second metal film inside the film to form a via contact having the second metal film and the second refractory metal film. Production method. 3. A method of manufacturing a multilayer wiring structure in which a lower wiring and an upper wiring are connected by a via contact, wherein a first metal film and a first metal film formed on the first metal film are formed.
Forming a lower wiring having a high melting point metal film, and forming an interlayer insulating film on the lower wiring, and then forming the first high melting point metal on the interlayer insulating film and the first high melting metal film. Etching is performed under the condition that the etching rate for the melting point metal film is lower than the etching rate for the interlayer insulating film to form a via hole in the interlayer insulating film, and the first refractory metal film has a flat surface of the via hole. Forming an opening smaller than the shape; forming a second refractory metal film at the bottom and side walls of the via hole; forming a second refractory metal film around the opening in the first refractory metal film; A step of projecting inward from a lower end of a side wall of the second refractory metal film and forming an overhang connected to a peripheral region of the opening in the first refractory metal film; Filling a second metal film inside the second refractory metal film to form a via contact having the second metal film and the second refractory metal film. A method for manufacturing a multilayer wiring structure, which is characterized by the following. 4. A multilayer wiring structure in which a lower wiring and an upper wiring are connected by a via contact, wherein the lower wiring is a first metal film and a first metal film embedded in an insulating film. The via contact has a first refractory metal film covering the side wall surface and the bottom surface, and the via contact has a second metal film and a second refractory metal film covering the side wall surface and the bottom surface of the second metal film. The bottom of the via contact is located lower than the upper surface of the lower wiring, a portion of the second refractory metal film forming the bottom of the via contact, and a first high melting point. A multilayer wiring structure wherein the side wall or the bottom of the metal film is connected. 5. A method for manufacturing a multilayer wiring structure in which a lower wiring and an upper wiring are connected by a via contact, wherein the first metal film and a side wall surface of the first metal film are embedded in an insulating film. Forming a lower wiring having a first refractory metal film covering the bottom surface, and forming an interlayer insulating film on the lower wiring, and then forming the interlayer insulating film on the interlayer insulating film and the insulating film. Etching is performed under the condition that the etching rate for the insulating film is higher than the etching rate for the first refractory metal film, and a via hole is formed in the interlayer insulating film so that the bottom of the via hole is located inside the insulating film. Exposing the side wall of the first refractory metal film to the bottom of the via hole, and forming a second refractory metal film on the bottom and the side wall of the via hole. Forming a film and connecting a portion of the second refractory metal film located at the bottom of the via hole to a side wall of the first refractory metal film; Filling a second metal film inside the film to form a via contact having the second metal film and the second refractory metal film. Production method. 6. A method of manufacturing a multilayer wiring structure in which a lower wiring and an upper wiring are connected by a via contact, comprising: a first metal film embedded in an insulating film; and a side wall surface of the first metal film. Forming a lower wiring having a first refractory metal film covering the bottom surface, and after forming an interlayer insulating film on the lower wiring, sequentially etching the interlayer insulating film and the first metal film. Forming a via hole in the interlayer insulating film such that the bottom of the via hole is located inside the first metal film; and forming a second high melting point on the bottom and the side wall of the via hole. Forming a metal film and connecting a portion of the second refractory metal film located at the bottom of the via hole to a side wall or a bottom of the first refractory metal film; No. 2 inside the high melting point metal film By filling a metal film, a method for manufacturing a multilayer wiring structure characterized by comprising a step of forming a via contact with the second metal film and the second refractory metal film.