JP2002016256A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of the conventional semiconductor devices that a metal element used to promote crystallization of an amorphous semiconductor film acts as a cause for damaging the stability and the reliability of electrical characteristics, when a TFT is manufactured. SOLUTION: A crystalline semiconductor film is formed by using the metal element used to promote the crystallization of the amorphous semiconductor film. The amorphous semiconductor film is selectivity doped with an impurity element, and an impurity region is formed. An electrode which is connected to the impurity region is formed. In succession, when a voltage is applied to the impurity region, the metal element is subjected to gettering in the impurity region. When a heating operation is performed at the same time, the diffusion rate of a gettering process is increased, and the gettering capability of the semiconductor device is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device having a circuit composed of thin film transistors (hereinafter, referred to as TFTs). For example, the present invention relates to a configuration of an electro-optical device typified by a liquid crystal display device, and an electric apparatus including the electro-optical device as a component. Further, the present invention relates to a method for manufacturing the device. Note that in this specification, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics, and the above-described electro-optical device and electric device are also included in the category.

[0002]

2. Description of the Related Art A technique for heating or laser annealing, or both heating and laser annealing, an amorphous semiconductor film formed on an insulating substrate such as glass to crystallize or improve crystallinity. Has been widely studied. A silicon film is often used as the semiconductor film.

[0003] The crystalline semiconductor film obtained by the above technique is made of many crystal grains and is called a polycrystalline semiconductor film. The crystalline semiconductor film is compared with the amorphous semiconductor film,
Has a very high mobility. For this reason, if a crystalline semiconductor film is used, for example, a monolithic liquid crystal electro-optical device (a pixel driving device) cannot be realized with a semiconductor device manufactured using a conventional amorphous semiconductor film. And a semiconductor device in which a thin film transistor (TFT) for a driver circuit is manufactured.

[0004] As described above, a crystalline semiconductor film is a semiconductor film having extremely high characteristics as compared with an amorphous semiconductor film. This is the reason why the above studies are performed. For example, in order to crystallize an amorphous semiconductor film by heating, a heating temperature of 600 ° C. or more and a heating time of 10 hours or more were required.
A substrate that can withstand this crystallization condition is, for example, a synthetic quartz substrate. However, a synthetic quartz substrate is expensive and poor in workability, and it is very difficult to process a large area in particular. Increasing the area of the substrate is an indispensable element particularly for increasing the mass production efficiency. In recent years, there has been a remarkable movement to increase the area of a substrate in order to improve the efficiency of mass production, and the line of a newly constructed mass production plant has a substrate size of 600 × 720 mm as a standard.

[0005] It is difficult to process a quartz substrate on such a large-area substrate with the current technology, and even if it is possible, it is considered that the price does not fall to a level that can be realized as an industry. For example, a glass substrate is a material that can be easily manufactured for a large-area substrate. On a glass substrate, for example, Corning 70
There is something called 59. Corning 7059 is very inexpensive, has good workability, and is easy to increase in area. However, Corning 7059 has a strain point temperature of 593 ° C.
There was a problem with heating at 600 ° C. or higher.

[0006] One type of glass substrate is Corning 1737, which has a relatively high strain point temperature. The strain point temperature of this is 667 ° C., which is higher than the strain point temperature of Corning 7059. Even when an amorphous semiconductor film was formed on the Corning 1737 substrate and was placed in an atmosphere at 600 ° C. for 20 hours, no deformation of the substrate was found that would affect the manufacturing process. However, the heating time of 20 hours was too long for the mass production process, and the heating temperature of 600 ° C. was preferred to be slightly lower from the viewpoint of cost.

[0007] To solve such a problem, a new crystallization method has been devised. Details of the above method are described in
No. 183540. Here, the method will be briefly described. First, a small amount of a metal element such as nickel, palladium, or lead is added to an amorphous semiconductor film. As a method of addition, a plasma treatment method, an evaporation method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used. After the addition, when the amorphous semiconductor film is placed in a nitrogen atmosphere at 550 ° C. for 4 hours, for example, a crystalline semiconductor film having good characteristics can be obtained. The optimal heating temperature and heating time for crystallization depend on the amount of the metal element added and the state of the amorphous semiconductor film.

However, the technique has a problem that the metal element used to promote crystallization remains in the high-resistance layer (channel formation region or offset region). Since the metal element easily conducts electricity, it lowers the resistance of a region that should be a high-resistance layer, and impairs stability and reliability of TFT characteristics.

In order to solve this problem, the present applicant has developed a technique (gettering technique) for removing a metal element for promoting crystallization from a crystalline semiconductor film.
It is disclosed in 270363. In the gettering technique, first, an element belonging to Group 15 is selectively added to a crystalline semiconductor film to perform heat treatment. Due to the heat treatment, the metal element in the region to which the element belonging to Group 15 is not added (the region to be gettered) is released from the region to be gettered, diffuses, and the region to which the element belonging to Group 15 is added ( Gettering region). As a result, it is possible to remove or reduce the metal element in the gettering region. Further, the heating temperature at the time of gettering can be set to 600 ° C. or less, which can withstand the glass substrate.

[0010]

After the crystallization of the semiconductor film, it is necessary to remove the metal element from the gettered region or reduce it to such an extent that the TFT does not affect the electrical characteristics when the TFT is manufactured. is there. However, the gettering region is smaller than the gettered region, the content of the metal element in the gettered region is excessive,
When the particle size of the metal compound is large, there is a problem that the metal element remains in the region to be gettered.

Further, when the heating temperature of the gettering is high, the diffusion time of the metal element is increased, so that the processing time of the gettering is shortened. Does not go up.
It is considered that this is because the bonding of the compound of the element belonging to Group 15 in the gettering region is strengthened by the experiment performed by the present applicant. Further, when the heating temperature is low, the diffusion rate of the metal element is reduced, so that the processing time of gettering becomes long, which is a disadvantage that it is too long for a mass production process.

An object of the present invention is to solve the above-mentioned problems and to provide a technique for forming a crystalline semiconductor film using a metal element, in which the removal or reduction of the metal element is improved. Is to do.

[0013]

Here, the mechanism of gettering of a metal element used to promote crystallization, which has been considered up to now, will be described by experiments of the present applicant. When an element belonging to Group XV is selectively added to the semiconductor film, the added region (gettering region) becomes amorphous. Next, the gettering region is crystallized from an amorphous state by heating the semiconductor film. At this time, the element belonging to Group 15 added to the gettering region comes to be located between lattices formed by the semiconductor film. In addition, by the heat treatment, the 1
In a region to which an element belonging to Group 5 is not added (a region to be gettered), a bond of a compound (called a metal compound) formed by the metal element is broken (this state is called emission). Subsequently, the metal element moves (this state is called diffusion), and the metal element and the element belonging to Group 15 are combined (this state is called capture). Thus, the metal element can be removed or reduced in the gettering region.

As described above, in the gettering process, the release of the metal element from the metal compound in the region to be gettered, the diffusion of the metal element, and the removal of the metal element by the element belonging to Group 15 in the gettering region. There is a capture process. According to experiments performed by the present applicant, it has been found that the emission energy of a metal element is so small as to be negligible in a TFT manufacturing process. That is, it is understood that the metal element is easily released by the thermal energy given during the manufacturing process of the TFT. Also,
According to an experiment conducted by the present applicant, it has been found that when the heat treatment is performed at a high temperature, the diffusion rate of the metal element increases, but the metal element is hardly gettered, and it is preferable to perform the heat treatment at a low temperature. At present, it is considered that the mechanism belonging to Group 15 is taken into a network formed by a semiconductor film at a high temperature and cannot be bonded to the metal element.

Therefore, in order to improve the gettering speed and efficiency, it is desirable to perform the process at a low temperature, and the process speed of the diffusion of the metal element in gettering may be promoted. As a method thereof, the present invention is characterized in that a voltage is applied to the gettering region.

When a voltage is applied to the gettering region, the metal compound is present in the high resistance layer.
An electric current selectively flows through the metal compound. Due to this current effect, the metal compound is heated, the bond is broken, and the release of the metal element occurs. The diffusion rate of the released metal element is accelerated by application of a voltage, and is combined with the element belonging to Group XV.

Thus, the removal or reduction of the metal element can be performed with high efficiency.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

First, a base insulating film 11 is formed on a substrate 10. The substrate 10 may be a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed. Alternatively, a plastic substrate having heat resistance enough to withstand the processing temperature may be used.

As the base insulating film 11, a base film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. The base insulating film may have a single-layer structure of the insulating film or a structure in which two or more layers are stacked. Note that the base insulating film need not be formed.

Next, the semiconductor layer 12 is formed on the base insulating film. As the semiconductor layer 12, a semiconductor film having an amorphous structure is formed by a known method (such as a sputtering method, an LPCVD method, or a plasma CVD method). Examples of the semiconductor film 12 include an amorphous semiconductor film, a microcrystalline semiconductor film, and a polycrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied.

Subsequently, a thermal crystallization method using a metal element such as nickel is performed. As a method for adding a metal element such as nickel, a plasma treatment method, an evaporation method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used, and the metal shown in FIG. The containing layer 13 is formed. After that, heat treatment is performed to crystallize the semiconductor layer. By this crystallization method, a metal element remains in the semiconductor film. After that, a laser crystallization method may be further performed as shown in FIG. An excimer laser is widely used as a laser oscillator used for laser crystallization because it has a large output and can oscillate a high-frequency pulse of about 300 Hz at present. In addition to the pulse oscillation excimer laser, a continuous oscillation excimer laser,
An Ar laser, a YAG laser, a YVO ₄ laser, a YLF laser, or the like can also be used. The laser beam irradiation can be performed in a vacuum, in the air, in a nitrogen atmosphere, or the like. Further, when irradiating a laser beam,
It may be heated to about 00 degrees.

The obtained crystalline semiconductor film is patterned into a desired shape using a photomask to form a semiconductor layer. This semiconductor layer is formed to have a thickness of 25 to 80 nm (preferably 30 to 60 nm).

Next, an insulating film 16 covering the semiconductor layer is formed. The insulating film 16 is formed to have a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method and has a single-layer or stacked-layer structure of an insulating film containing silicon. The insulating film 16 becomes a gate insulating film.

Then, a gate electrode 17 is formed on the insulating film 16 with a conductive material containing one or more elements selected from tantalum, tungsten, titanium, aluminum and molybdenum.

Thereafter, as shown in FIG. 1E, a doping process is performed using the gate electrode 17 as a mask to form the impurity region 17 in a self-aligned manner.

Thereafter, an interlayer insulating film 18 is formed from a silicon nitride film and a silicon nitride oxide film manufactured by a plasma CVD method.

Next, as shown in FIG. 2A, it is desirable to perform a step of activating the impurity element added to each semiconductor layer. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm or less.
The heat treatment may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere of ppm or less.

Simultaneously with the above-described activation treatment, an amorphous region containing a high concentration of elements belonging to Group 15 is crystallized. Therefore, the metal element used as a catalyst at the time of crystallization is gettered in the impurity region, and the concentration of the metal element in the semiconductor layer which mainly becomes a channel formation region is reduced.

An activation process may be performed before the formation of the interlayer insulating film. However, when the wiring material used is weak to heat, after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) for protecting the wiring and the like as in this embodiment, the active material is activated. It is preferable to carry out a chemical treatment.

Then, an electrode 20 electrically connected to each of the impurity regions 17 is formed to obtain a TFT. These electrodes are composed of a 50 nm-thick Ti film,
A stacked film of a 500-nm-thick alloy film (an alloy film of Al and Ti) is formed by patterning.

Here, a voltage is applied between the source and drain electrodes 20 to create a potential difference, thereby removing or reducing the metal element remaining in the channel formation region. When a voltage is applied, current flows from the source region to the drain region through the channel formation region. However, since the channel formation region has high resistance, the current is selectively applied to the metal compound particularly in the channel formation region. Flows. For this reason, the temperature of the metal compound increases, the bond is broken,
The metal element is released. Also, since the source and drain regions are not selectively heated by current,
Gettering can be performed without reducing the capturing ability. The diffusion speed of the metal element is increased by the potential difference between the source region and the drain region, and is captured in the source region or the drain region. How the voltage is applied depends on whether it is captured in the source region or the drain region,
It depends on the n-type and p-type of the TFT. Further, when a voltage is applied to the gate electrode, a current easily flows from the source region to the drain region, so that the diffusion capability is increased. Also, if heating is performed at the same time as applying a voltage, the emission and diffusion rates increase.

Thus, the metal element can be removed or reduced from the channel formation region, and the electrical characteristics of the TFT are improved. In particular, variation in off-state current can be reduced.

It should be noted that the present invention relates to the TF described in the embodiment.
Not only the method of manufacturing T, but also bottom gate and other TFT
It can also be applied to the structure of

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0036]

[Embodiment 1] Here, a method of manufacturing an n-channel TFT and performing gettering will be described with reference to the cross-sectional views of FIGS.

First, a base insulating film 11 is formed on a substrate 10. The substrate 10 may be a glass substrate, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed. Alternatively, a plastic substrate having heat resistance enough to withstand the processing temperature may be used.

As the base insulating film 11, a base film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed. The base insulating film may have a single-layer structure of the insulating film or a structure in which two or more layers are stacked. Note that the base insulating film need not be formed. In this embodiment, a 100-nm-thick silicon oxynitride film 11 (composition ratio: Si = 32%, O = 27%, N = 24
%, H = 17%).

Next, the semiconductor film 12 is formed on the base insulating film. As the semiconductor film 12, a semiconductor film having an amorphous structure is formed by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like). Examples of the semiconductor film 12 include an amorphous semiconductor film, a microcrystalline semiconductor film, and a polycrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied.
In this embodiment, an amorphous silicon film having a thickness of 55 nm is formed by a plasma CVD method.

Subsequently, a thermal crystallization method using a metal element such as nickel is performed. As a method for adding a metal element such as nickel, a plasma treatment method, an evaporation method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used, and the metal shown in FIG. The containing layer 13 is formed. After that, heat treatment is performed to crystallize the semiconductor layer. In this embodiment, a solution containing nickel is held on an amorphous silicon film, and dehydrogenation (500
C. for 1 hour), followed by thermal crystallization (550 ° C. for 4 hours). The metal element remains in the semiconductor film by this crystallization method.

A semiconductor layer is formed by patterning the obtained crystalline semiconductor film into a desired shape using a photomask. This semiconductor layer is formed to have a thickness of 25 to 80 nm (preferably 30 to 60 nm).

Next, an insulating film 16 covering the semiconductor layer is formed. The insulating film 16 is formed to have a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method and has a single-layer or stacked-layer structure of an insulating film containing silicon. The insulating film 16 becomes a gate insulating film. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H =
2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Then, a gate electrode 17 is formed on the insulating film 16 by using a conductive material containing one or more elements selected from tantalum, tungsten, titanium, aluminum, and molybdenum. In this embodiment, the film thickness is 400
A gate electrode made of a TaN film having a thickness of nm was formed. In order to use it as a gate electrode, it is necessary to reduce the resistance, and it is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains many impurity elements such as oxygen, the crystallization is inhibited and the resistance is increased. Therefore, in this embodiment, the W film is formed by a sputtering method using a high-purity W (purity of 99.9999%) target, and further taking care not to mix impurities from the gas phase during film formation. By forming, a resistivity of 9 to 20 μΩcm could be realized.

Thereafter, as shown in FIG. 1D, a doping process is performed using the gate electrode 17 as a mask to form the impurity regions 18 in a self-aligned manner. The doping treatment may be performed by an ion doping method or an ion implantation method.
an element belonging to Group 15 as an impurity element imparting n-type,
Typically, phosphorus (P) or arsenic (As) is used,
Here, phosphorus (P) was used. In this case, the gate electrode 1
7 is a mask for an impurity element imparting n-type,
Impurity region 18 is formed in a self-aligned manner.

Thereafter, an interlayer insulating film 19 is formed from a silicon nitride film and a silicon nitride oxide film manufactured by a plasma CVD method. The insulating film containing silicon is formed with a thickness of 100 to 200 nm by a plasma CVD method or a sputtering method. In this embodiment, a 150-nm-thick silicon oxynitride film is formed by a plasma CVD method. Needless to say, the interlayer insulating film 19 is not limited to a silicon oxynitride film, but may be another insulating film containing silicon in a single layer or a laminated structure.

Next, as shown in FIG. 2A, it is desirable to perform a step of activating the impurity element added to each semiconductor layer. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm or less.
The heat treatment may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere of ppm or less.

Simultaneously with the above-mentioned activation treatment, an impurity region containing a high-concentration element belonging to Group 15 in an amorphous state is crystallized. Therefore, the metal element used as a catalyst at the time of crystallization is gettered in the impurity region, and the concentration of the metal element in the semiconductor layer which mainly becomes a channel formation region is reduced.

Further, a crystallization process may be performed before forming the interlayer insulating film. However, when the wiring material used is weak to heat, after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) for protecting the wiring and the like as in this embodiment, the crystal is formed. It is preferable to carry out a chemical treatment.

Then, an electrode 20 electrically connected to each of the impurity regions 18 is formed, so that an n-channel TFT can be obtained. These electrodes have a thickness of 50 nm.
And a 500 nm-thick alloy film (an alloy film of Al and Ti) is patterned and formed.

Here, a voltage is applied to the source and drain electrodes 20 to create a potential difference, thereby removing or reducing the metal element remaining in the channel formation region. When a voltage is applied, current flows from the source region to the drain region through the channel formation region. However, since the channel formation region has high resistance, the current is selectively applied to the metal compound particularly in the channel formation region. Flows. For this reason, the temperature of the metal compound increases, the bond is broken,
The metal element is released. In addition, since the source and drain regions are not heated due to the selective flow of current, gettering can be performed without lowering the trapping ability. The diffusion speed of the metal element is increased by the potential difference between the source region and the drain region, and is captured in the source region or the drain region. Which of the source region and the drain region is captured depends on how the voltage is applied. Further, when a voltage is applied to the gate electrode, a current easily flows from the source region to the drain region, so that the diffusion capability is increased. When the heating is performed at the same time or higher than the standard of the TFT at the time of applying the voltage, the emission and diffusion rates are increased. Increase. In the present embodiment, a voltage higher than the standard of the n-channel TFT is applied to the source electrode, the drain electrode is connected to the ground, and the gettering is performed by heating at a temperature higher than the standard. The present inventor, in this embodiment,
It is considered that the metal element moves in the direction indicated by 22 (the direction opposite to the direction of the electric field) by creating a potential difference between the source region and the drain region as shown in FIG.

Thus, the metal element can be removed or reduced from the channel formation region, and the electrical characteristics of the TFT are improved. In particular, variation in off-state current can be reduced.

[Embodiment 2] In this embodiment, a p-channel type T
Figure 1 shows how to make FT and perform gettering
This will be described with reference to FIG.

1E, a doping process is performed using the gate electrode 16 as a mask, and the impurity region 23 is self-aligned.
Is formed (FIG. 9A). The doping treatment may be performed by an ion doping method or an ion implantation method. Here, as an impurity element imparting p-type, diborane (B
Using an ion doping method using ₂ H _6). in this case,
Gate electrode 16 serves as a mask for the impurity element imparting p-type, and impurity region 23 is formed in a self-aligned manner.

After that, an interlayer insulating film 24 is formed from a silicon nitride film and a silicon nitride oxide film manufactured by a plasma CVD method. The insulating film containing silicon is formed with a thickness of 100 to 200 nm by a plasma CVD method or a sputtering method. In this embodiment, a 150-nm-thick silicon oxynitride film is formed by a plasma CVD method. Needless to say, the interlayer insulating film 24 is not limited to a silicon oxynitride film, but may be another insulating film containing silicon as a single layer or a laminated structure.

Next, as shown in FIG. 9B, it is desirable to perform a step of activating the impurity element added to each semiconductor layer. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the oxygen concentration is 1 ppm or less, preferably 0.1 ppm or less.
The heat treatment may be performed at 400 to 700 ° C., typically 500 to 550 ° C. in a nitrogen atmosphere of ppm or less.

Simultaneously with the above-described activation treatment, an amorphous region containing a high concentration of elements belonging to Group 15 is crystallized. Therefore, the metal element used as a catalyst at the time of crystallization is gettered in the impurity region, and the concentration of the metal element in the semiconductor layer which mainly becomes a channel formation region is reduced.

Further, a crystallization process may be performed before forming the interlayer insulating film. However, when the wiring material used is weak to heat, after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) for protecting the wiring and the like as in this embodiment, the crystal is formed. It is preferable to carry out a chemical treatment.

Then, an electrode 25 electrically connected to each of the impurity regions 23 is formed, so that an n-channel TFT can be obtained. These electrodes have a thickness of 50 nm.
And a 500 nm-thick alloy film (an alloy film of Al and Ti) is patterned and formed.

Here, a voltage is applied to the source and drain electrodes 25 to create a potential difference, thereby removing or reducing the metal element remaining in the channel formation region. When a voltage is applied, current flows from the source region to the drain region through the channel formation region. However, since the channel formation region has high resistance, the current is selectively applied to the metal compound particularly in the channel formation region. Flows. For this reason, the temperature of the metal compound increases, the bond is broken,
The metal element is released. In addition, since the source and drain regions are not heated due to the selective flow of current, gettering can be performed without lowering the trapping ability. The diffusion speed of the metal element is increased by the potential difference between the source region and the drain region, and is captured in the source region or the drain region. Which of the source region and the drain region is captured depends on how the voltage is applied. Further, when a voltage is applied to the gate electrode, a current easily flows from the source region to the drain region, so that the diffusion capability is increased. When the heating is performed at the same time or higher than the standard of the TFT at the time of applying the voltage, the emission and diffusion rates are increased. Increase. In this embodiment, a voltage higher than the standard of the p-channel TFT is applied to the source electrode, the drain electrode is connected to the ground, and the gettering is performed by heating at a temperature higher than the standard. The present inventor, in this embodiment,
It is considered that the metal element moves in the direction indicated by 26 (the direction opposite to the direction of the electric field) by creating a potential difference between the source region and the drain region as shown in FIG. 9C.

Thus, the metal element can be removed or reduced from the channel formation region, and the electrical characteristics of the TFT are improved. In particular, variation in off-state current can be reduced.

[Embodiment 3] In this embodiment, a method of performing gettering at a higher temperature than in Embodiment 1 will be described.

1E, the interlayer insulating film 19 is formed, the activation of the impurity element and the crystallization of the impurity region 18 are performed. Further, an activation process may be performed before forming the interlayer insulating film. However, when the wiring material used is weak to heat, after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) for protecting the wiring and the like as in this embodiment, the active material is activated. It is preferable to carry out a chemical treatment.

Then, an electrode 20 electrically connected to each of the impurity regions 18 is formed, and an n-channel TFT can be obtained. In this embodiment, these electrodes are formed by using a high melting point W film and patterning a 550 nm-thick film.

Here, a voltage is applied to the source and drain electrodes 20 to create a potential difference, and the metal element remaining in the channel formation region is removed or reduced. By applying a voltage, current flows from the source region to the drain region through the channel formation region. However, since the channel formation region has high resistance, in the channel formation region,
In particular, an electric current selectively flows through the metal compound. For this reason, the temperature of the metal compound increases, the bond is broken, and the metal element is released. Further, since the source and drain regions are not selectively heated by the current, gettering can be performed without lowering the capturing ability. The diffusion speed of the metal element is increased by the potential difference between the source region and the drain region, and is captured in the source region or the drain region. Which of the source region and the drain region is captured depends on how the voltage is applied. Furthermore, when a voltage is applied to the gate electrode,
Since the current easily flows from the source region to the drain region, the diffusion capability is increased. Further, when heating at a voltage higher than the standard of the TFT is performed simultaneously, the emission and diffusion speeds are increased. In this embodiment, the voltage within the standard of the n-channel TFT is applied to the gate electrode, the source electrode, and the drain electrode, and the gettering is performed by heating to a high temperature of about 200 ° C.

Thus, the metal element can be removed or reduced from the channel formation region, and the electrical characteristics of the TFT are improved. In particular, variation in off-state current can be reduced.

[Embodiment 4] In this embodiment, a method for manufacturing an active matrix substrate will be described with reference to FIGS.

First, in this embodiment, Corning # 70
A substrate 400 made of glass such as barium borosilicate glass typified by 59 glass or # 1737 glass, or aluminoborosilicate glass is used. Note that as the substrate 400, a quartz substrate, a silicon substrate, a metal substrate, or a stainless steel substrate on which an insulating film is formed may be used. Further, a plastic substrate having heat resistance enough to withstand the processing temperature of this embodiment may be used.

Next, a silicon oxide film is formed on the substrate 400,
A base film 401 including an insulating film such as a silicon nitride film or a silicon oxynitride film is formed. Although a two-layer structure is used as the base film 401 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. For the first layer of the base film 401, a plasma CVD
iH _4, NH _3, the deposited the silicon oxynitride film 401a and the N ₂ O as reaction gases 10 to 200 nm (preferably 50 to 100 nm) is formed. In this embodiment, the film thickness 5
0 nm silicon oxynitride film 401a (composition ratio Si = 3
2%, O = 27%, N = 24%, H = 17%). Next, as the second layer of the base film 401, a silicon oxynitride film 401b formed using SiH ₄ and N ₂ O as a reaction gas by plasma CVD is used to form a _second layer of 50 to 200.
nm (preferably 100 to 150 nm). In this embodiment, a 100-nm-thick silicon oxynitride film 401b (composition ratio: Si = 32%, O = 59%, N =
7%, H = 2%).

Next, semiconductor layers 402 to 40 are formed on the underlying film.
6 is formed. The semiconductor layers 402 to 406 are formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCV
D method or plasma CVD method). Examples of the semiconductor film 12 include an amorphous semiconductor film, a microcrystalline semiconductor film, and a polycrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be applied. In this embodiment, an amorphous silicon film having a thickness of 55 nm is formed by a plasma CVD method.

Subsequently, a thermal crystallization method using a metal element such as nickel is performed. As a method for adding a metal element such as nickel, a plasma treatment method, an evaporation method, an ion implantation method, a sputtering method, a solution coating method, or the like may be used, and the metal shown in FIG. The containing layer 303 is formed. After that, heat treatment is performed to crystallize the semiconductor layer. In this embodiment, a solution containing nickel is held on an amorphous silicon film, and the amorphous silicon film is dehydrogenated (50%).
0 ° C., 1 hour), and then heat crystallization (550 ° C., 4 hours).
Hours). The metal element remains in the semiconductor film by this crystallization method.

The obtained crystalline semiconductor film is formed by patterning it into a desired shape. These semiconductor layers 402 to 406
Has a thickness of 25 to 80 nm (preferably 30 to 60 nm)
Formed with a thickness of In this embodiment, the semiconductor layers 402 to 406 are formed by patterning the crystalline silicon film using a photolithography method.

After the formation of the semiconductor layers 402 to 406, a small amount of impurity element (boron or phosphorus) may be doped to control the threshold value of the TFT.

When a crystalline semiconductor film is formed by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, a YAG laser, a YVO ₄ laser, or the like can be used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 300 Hz and the laser energy density is set to 100 to 4.
(Typically ^{200~300mJ / cm 2) 00mJ / cm} 2 to.
When a YAG laser is used, its second harmonic is used, the pulse oscillation frequency is set to 1 to 300 Hz, and the laser energy density is set to 300 to 600 mJ / cm ² (typically 3 to 600 mJ / cm ² ).
It is good to be 50-500 mJ / cm ² ). And width 100 ~
A laser beam condensed linearly at 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear laser light at this time is 50 to 98.
% May be used.

Next, a gate insulating film 407 covering the semiconductor layers 402 to 406 is formed. The gate insulating film 407 is formed by a plasma CVD method or a sputtering method and has a thickness of 40 to
The insulating film containing silicon is formed to have a thickness of 150 nm. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59) having a thickness of 110 nm by a plasma CVD method.
%, N = 7%, H = 2%). Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

When a silicon oxide film is used,
TEOS (Tetraethyl Orthosilica) by plasma CVD
te) and O ₂ , a reaction pressure of 40 Pa, and a substrate temperature of 30
It can be formed by discharging at a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² at 0 to 400 ° C. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Next, as shown in FIG. 3C, a first conductive film 408 having a thickness of 20 to 100 nm and a second conductive film 40 having a thickness of 100 to 400 nm are formed on the gate insulating film 407.
9 are laminated. In this embodiment, a 30 nm-thick T
a first conductive film 408 made of an aN film and a film thickness of 370 nm
A second conductive film 409 made of a W film was laminated. T
The aN film was formed by a sputtering method, and was sputtered using a Ta target in an atmosphere containing nitrogen. The W film was formed by a sputtering method using a W target. In addition, thermal CV using tungsten hexafluoride (WF ₆ )
It can also be formed by Method D. In any case, it is necessary to lower the resistance in order to use it as a gate electrode,
It is desirable that the resistivity of the W film be 20 μΩcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when the W film contains many impurity elements such as oxygen, the crystallization is inhibited and the resistance is increased. Therefore, in this embodiment, the W film is formed by a sputtering method using a high-purity W (purity of 99.9999%) target, and further taking care not to mix impurities from the gas phase during film formation. By forming, a resistivity of 9 to 20 μΩcm could be realized.

In this embodiment, the first conductive film 408
Is TaN and the second conductive film 409 is W, but there is no particular limitation, and any of Ta, W, Ti, Mo, Al, Cu,
It may be formed of an element selected from Cr and Nd, or an alloy material or a compound material containing the element as a main component.
Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. Also, A
A gPdCu alloy may be used. A first conductive film formed of a tantalum (Ta) film, a second conductive film formed of a W film, a first conductive film formed of a titanium nitride (TiN) film, and a second conductive film formed of a titanium nitride (TiN) film; As a W film, the first
The first conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of a tantalum nitride (TaN) film, the second conductive film is formed of a tantalum nitride (TaN) film, and the second conductive film is formed of a Cu film. May be combined.

Next, resist masks 410 to 415 are formed by photolithography, and a first etching process for forming electrodes and wirings is performed. The first etching process is performed under the first and second etching conditions. In this embodiment, the first etching condition is I
Using a CP (Inductively Coupled Plasma) etching method, using CF ₄ , Cl _2, and O _{2 as} etching gases, and using a gas flow ratio of 25/2.
At 5/10 (sccm), 500 W RF (13.56 MHz) power was applied to the coil-type electrode at a pressure of 1 Pa to generate plasma and perform etching. Here, a dry etching apparatus (Model E645- □ ICP) using ICP manufactured by Matsushita Electric Industrial Co., Ltd. was used. A 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under the first etching conditions to form the first film.
Of the conductive layer is tapered.

Thereafter, a mask 410 made of resist is formed.
The second etching condition was changed without removing 415, CF ₄ and Cl ₂ were used as etching gases, the respective gas flow ratios were 30/30 (sccm), and the pressure was 1 Pa to form a coil-type electrode. RF (13.56 MHz) power of 500 W was applied to generate plasma, and etching was performed for about 30 seconds. The substrate side (sample stage) also has a 20 W RF (13.56
MHz) power is applied and a substantially negative self-bias voltage is applied. Under the second etching condition in which CF ₄ and Cl ₂ are mixed, the W film and the TaN film are etched to the same extent. Note that in order to perform etching without leaving a residue on the gate insulating film, the etching time is preferably increased by about 10 to 20%.

In the first etching process, by making the shape of the resist mask appropriate,
The ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °. Thus, the first-shaped conductive layers 417 to 422 (the first conductive layers 417 a to 422 a and the second conductive layers 417 b to 422) formed of the first conductive layer and the second conductive layer by the first etching process.
2b) is formed. 416 is a gate insulating film,
The region not covered by the conductive layers 417 to 422 having the
A region that is etched and thinned by about 50 nm is formed.

Then, the resist mask is removed.
First doping processing without adding an n-type semiconductor layer.
The added impurity element is added. (FIG. 4A) Dopin
Can be done by ion doping or ion implantation
Good. The condition of the ion doping method is that the dose amount is 1 × 10¹³
~ 5 × 10^Fifteenatoms / cm^TwoAnd the acceleration voltage is 60 to 100
Performed as keV. In this embodiment, the dose is 1.5 × 1
0^Fifteenatoms / cm^TwoAnd the acceleration voltage is set to 80 keV.
Was. Element belonging to Group 15 as an impurity element imparting n-type
Using arsenic, typically phosphorus (P) or arsenic (As)
However, phosphorus (P) was used here. In this case, the conductive layer 4
17 to 421 are masses for the impurity element imparting n-type.
And the high-concentration impurity regions 423 to 42 are self-aligned.
7 is formed. In the high-concentration impurity regions 423 to 427,
1 × 10²⁰~ 1 × 10^{twenty one}atoms / cm ^ThreeN type in the concentration range of
An impurity element to be added is added.

Next, a second etching process is performed without removing the resist mask. Here, the W film is selectively etched using CF ₄ , Cl ₂ and O _{2 as} an etching gas. At this time, first conductive layers 428b to 433b are formed by a second etching process. On the other hand, the second conductive layers 417a to 422a are hardly etched, and form the second conductive layers 428a to 433a.

After removing the resist mask, new resist masks 438a to 438g are formed and the second doping process is performed to obtain the state shown in FIG. 4B. An impurity element is selectively added to the impurity regions 423 to 427 to form impurity regions 439 to 443.

Next, the resist mask is removed.
After that, masks 452 to 454 made of a new resist
Then, a third doping process is performed. This third do
Ping process becomes active layer of p-channel TFT
Impurities that impart a conductivity type opposite to the one conductivity type to the semiconductor layer
Impurity regions 455 to 460 to which the impurity element is added
You. The second conductive layers 428a to 432a correspond to impurity elements.
Impurity element for imparting p-type
In addition, an impurity region is formed in a self-aligned manner. In this embodiment
Indicates that the impurity regions 455 to 460 have diborane (B_TwoH₆)
It is formed by the ion doping method used. (FIG. 5A)
In the third doping process, an n-channel TFT is
The semiconductor layer to be formed is a mask 452 to 4 made of resist.
Covered with 54. A first doping process and a second
By the doping process, the impurity regions 455 to 460 are formed.
Have different concentrations of phosphorus,
In any region, the concentration of the impurity element imparting p-type
Degree 2 × 10²⁰~ 2 × 10 ^{twenty one}atoms / cm^ThreeSo that
The p-channel TFT
To function as source and drain regions
No problem. In this embodiment, the p-channel TFT
Since part of the semiconductor layer serving as the active layer is exposed,
This has the advantage that a substance element (boron) can be easily added.

By the steps described above, impurity regions are formed in each semiconductor layer.

Next, a resist mask 452 to 452 is formed.
454 is removed to form a first interlayer insulating film 461.
As the first interlayer insulating film 461, plasma CVD
Thickness of 100 to 200 nm by using a sputtering method or a sputtering method
As an insulating film containing silicon. In this embodiment, a 150-nm-thick silicon oxynitride film is formed by a plasma CVD method. Of course, the first interlayer insulating film 461
Is not limited to a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, as shown in FIG. 5B, a step of activating the impurity element added to each semiconductor layer is performed. This activation step is performed by a thermal annealing method using a furnace annealing furnace. As the thermal annealing method, the oxygen concentration is 400 to 700 ° C. in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less, typically 500 to
The activation treatment may be performed at 550 ° C. In this embodiment, the activation treatment is performed by heat treatment at 550 ° C. for 4 hours. Note that, other than the thermal annealing method, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied.

In this embodiment, at the same time as the above-mentioned activation treatment, nickel used as a catalyst during crystallization is doped with impurity regions 439, 441, 442, and 4 containing high-concentration phosphorus.
55, 458 are crystallized. Therefore, the impurity region and the metal element are gettered, and the nickel concentration in the semiconductor layer mainly serving as a channel formation region is reduced. A TFT having a channel formation region manufactured in this manner has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and favorable characteristics can be achieved.

Further, an activation process may be performed before forming the first interlayer insulating film. However, when the wiring material used is weak to heat, after forming an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) for protecting the wiring and the like as in this embodiment, the active material is activated. It is preferable to carry out a chemical treatment.

Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to hydrogenate the semiconductor layer. In this embodiment, heat treatment was performed at 410 ° C. for one hour in a nitrogen atmosphere containing about 3% of hydrogen. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

In the case where a laser annealing method is used as the activation treatment, it is preferable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the above hydrogenation.

Next, a second interlayer insulating film 462 made of an inorganic insulating material or an organic insulating material is formed on the first interlayer insulating film 461. In this embodiment, the film thickness is 1.6 μm
Was formed, but the viscosity was 10 to 1000
cp, preferably 40 to 200 cp, and those having irregularities on the surface were used.

In this embodiment, in order to prevent specular reflection, irregularities are formed on the surface of the pixel electrode by forming a second interlayer insulating film having irregularities on the surface. In addition, a projection may be formed in a region below the pixel electrode in order to obtain light scattering by providing unevenness on the surface of the pixel electrode. In that case, the projection can be formed using the same photomask as that for forming the TFT, and thus can be formed without increasing the number of steps. Note that the protrusions may be appropriately provided on the substrate in the pixel portion region other than the wiring and the TFT portion. Thus, irregularities are formed on the surface of the pixel electrode along irregularities formed on the surface of the insulating film covering the convex portions.

Further, a film whose surface is flattened may be used as second interlayer insulating film 462. In that case, after forming the pixel electrode, the surface is made uneven by adding a process such as a known sand blasting method or an etching method to prevent specular reflection and increase whiteness by scattering reflected light. Is preferred.

In drive circuit 506, wirings 463 to 467 electrically connected to the respective impurity regions, respectively.
To form Note that these wirings are made of a 50 nm thick T
A laminated film of an i film and a 500 nm-thick alloy film (an alloy film of Al and Ti) is formed by patterning.

In the pixel portion 507, a pixel electrode 470, a gate wiring 469, and a connection electrode 468 are formed. (FIG. 5C) The connection wiring 468 forms an electrical connection between the source wiring (the lamination of 443b and 449) and the pixel TFT. Further, the gate wiring 469 is electrically connected to the gate electrode of the pixel TFT. The pixel electrode 470 is connected to the drain region 44 of the pixel TFT.
2 and an electrical connection is formed with the semiconductor layer 458 functioning as one electrode forming a storage capacitor. The pixel electrode 471 has A
It is desirable to use a material having excellent reflectivity, such as a film containing l or Ag as a main component or a laminated film thereof.

As described above, the n-channel TFT 50
1 and a CMOS circuit comprising a p-channel TFT 502;
And driving circuit 506 having n-channel TFT 503
And a pixel portion 507 having a pixel TFT 504 and a storage capacitor 505 can be formed over the same substrate. Thus, an active matrix substrate is completed.

The n-channel TFT 50 of the driving circuit 506
Reference numeral 1 denotes a low-concentration impurity region 43 overlapping with a channel formation region 471 and a first conductive layer 444 forming a part of a gate electrode.
4b (GOLD region), a low concentration impurity region 434a (LDD region) formed outside the gate electrode, and a high concentration impurity region 4 functioning as a source region or a drain region.
39. The p-channel TFT 502 connected to the n-channel TFT 501 by the electrode 466 to form a CMOS circuit has a channel formation region 472, an impurity region 457 overlapping with the gate electrode, an impurity region 458 formed outside the gate electrode, and a source region. Alternatively, the semiconductor device includes a high-concentration impurity region 455 functioning as a drain region. The n-channel TFT 503 includes a channel formation region 473, a low-concentration impurity region 436b (a GOLD region) overlapping with the first conductive layer 446 forming a part of the gate electrode, and a low-concentration impurity formed outside the gate electrode. A region 437a (LDD region) and a high-concentration impurity region 441 functioning as a source or drain region are provided.

In the pixel TFT 504 in the pixel portion, a channel formation region 474 and a low-concentration impurity region 437b (GOLD) overlapping the first conductive layer 447 forming a part of the gate electrode are provided.
Region), a low concentration impurity region 437a (LDD region) formed outside the gate electrode, and a high concentration impurity region 443 functioning as a source region or a drain region. Further, each of the semiconductor layers 458 to 460 functioning as one electrode of the storage capacitor 505 is doped with an impurity element imparting p-type. The storage capacitor 505 is formed using electrodes (a laminate of 448 and 432b) and semiconductor layers 458 to 460 using the insulating film 451 as a dielectric.

In the pixel structure of this embodiment, the end of the pixel electrode is formed so as to overlap with the source wiring so that the gap between the pixel electrodes is shielded from light without using a black matrix.

The terminal 202 is connected to the connection wiring 468 of the active matrix substrate 201 thus manufactured, a voltage 203 is applied, and the substrate is heated in the oven 204 (FIG. 7). A method for applying a voltage to the TFT and the pixel TFT of the driver circuit will be described with reference to FIG. The driver circuit is constituted by a CMOS circuit shown in FIG. COMS circuit comprises a p-channel TFT and n-channel type TFT, V to V _{in
When dd} is input, the p-channel TFT is turned off,
The n-channel TFT is turned ON, and V _ss is applied to V _out.
Is output. Also, if you enter the V _ss to V _in, p to the channel type TFT is ON, n-channel TFT OF
The state becomes the F state, and _Vdd is output to _Vout . However,
V _dd > V _{s s} . That is, if the input alternating V _ss and V _dd to V _in, p-channel TFT and n-channel type T
A current flows alternately in the FT, and the metal element can be gettered from the channel formation region. The inventor is CMO
When the voltage is applied to the S circuit as described above, FIG.
Since an electric field as shown in FIG.
It is considered that the metal element moves in the direction opposite to the direction of the electric field in both the FT and the n-channel TFT and is gettered in the source region in the p-channel TFT and in the drain region in the n-channel TFT. Further, as another method for applying voltage, is applied to _{(V dd + V ss) /} 2 voltage to the V _in, current always flows through the p-ch and n-ch, it is possible to perform gettering. Of course, V _in V in
_A voltage higher than _dd may be applied.

FIG. 8B shows a circuit of the pixel TFT. In the pixel TFT, the gate electrode is connected to the gate line, and the source region is connected to the source line. The drain region is connected to a storage capacitor, and the storage capacitor is connected to a common potential. Further, when a liquid crystal panel or the like is manufactured, the drain region is connected to the liquid crystal via the drain wiring, but is not connected at this stage because it is in an active matrix substrate state. When a voltage is applied to the source region, a potential difference occurs between the source region and the drain region. When a voltage is further applied to the gate electrode, the source region and the drain region have the same potential due to the presence of the storage capacitor. However, since the time when the gate electrode is turned on and the time when the gate electrode is turned off is extremely short, the state where there is a potential difference between the source region and the drain region is long.
Gettering can be performed using this potential difference. Further, instead of connecting the storage capacitor to the common potential, a potential can be applied to further increase the potential difference from the source line. In this way, the pixel T
Gettering in FT can be performed.

According to the above-described method, the metal element can be removed or reduced from the channel forming region and the offset region, and the electrical characteristics of the TFT are improved. In particular, variation in off-state current can be reduced.

FIG. 6 is a top view of a pixel portion of an active matrix substrate manufactured in this embodiment. Note that FIG.
5 are denoted by the same reference numerals. FIG.
A chain line AA ′ in FIG. 6 corresponds to a cross-sectional view taken along a line AA ′ in FIG. The dashed line BB ′ in FIG. 5 corresponds to the cross-sectional view taken along the dashed line BB ′ in FIG.

[Embodiment 5] In this embodiment, a process of fabricating a reflective liquid crystal display device from the active matrix substrate fabricated in Embodiment 4 will be described below. FIG. 10 is used for the description.

First, according to the fourth embodiment, after obtaining the active matrix substrate in the state shown in FIG. 5C, an alignment film 471 is formed on at least the pixel electrode 470 on the active matrix substrate shown in FIG. . In this embodiment, before forming the alignment film 471, a columnar spacer (not shown) for maintaining a substrate interval was formed at a desired position by patterning an organic resin film such as an acrylic resin film. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 472 is prepared. Next, the coloring layers 473 and 474 and the flattening film 475 are formed over the counter substrate 472. The red coloring layer 473 and the blue coloring layer 474 are overlapped to form a light-shielding portion. Alternatively, the light-blocking portion may be formed by partially overlapping the red coloring layer and the green coloring layer.

In this embodiment, the substrate shown in Embodiment 4 is used. Therefore, FIG. 6 shows a top view of the pixel portion of the fourth embodiment.
Then, at least a gap between the gate wiring 469 and the pixel electrode 470, a gap between the gate wiring 469 and the connection electrode 468,
It is necessary to shield the gap between the connection electrode 468 and the pixel electrode 470 from light. In this embodiment, the colored layers are arranged such that the light-shielding portion formed of the colored layers is overlapped at the positions where the light is to be shielded, and the opposing substrates are bonded to each other.

As described above, the number of steps can be reduced by shielding the gap between each pixel with the light-shielding portion formed of the colored layers without forming a light-shielding layer such as a black mask.

Next, a counter electrode 476 made of a transparent conductive film was formed on at least the pixel portion on the flattening film 475, an alignment film 477 was formed on the entire surface of the counter substrate, and rubbing treatment was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the opposing substrate are sealed with a sealing material 478.
Paste in. A filler is mixed in the sealant 478, and the two substrates are bonded to each other at a uniform interval by the filler and the columnar spacer. afterwards,
A liquid crystal material 479 is injected between the two substrates, and completely sealed with a sealant (not shown). As the liquid crystal material 479, a known liquid crystal material may be used. Thus, the reflection type liquid crystal display device shown in FIG. 10 is completed. Then, if necessary, the active matrix substrate or the opposing substrate is cut into a desired shape. Further, a polarizing plate (not shown) was attached only to the counter substrate. Then, using a known technique, F
PC was pasted.

The liquid crystal display panel manufactured as described above can be used as a display section of various electronic devices.

[Embodiment 6] TFTs formed by carrying out any one of Embodiments 1 to 5 can be used in various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC). Display). That is,
The invention of the present application can be applied to all electronic devices in which these electro-optical devices are incorporated in a display unit.

Examples of such electronic devices include a video camera, a digital camera, a projector, a head-mounted display (goggle type display), a car navigation, a car stereo, a personal computer, a portable information terminal (a mobile computer, a mobile phone, an electronic book, etc.). ). An example of them is shown in FIG.
FIG. 12 and FIG.

FIG. 11A shows a personal computer, which comprises a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. Display unit 2 of the present invention
003 can be applied.

FIG. 11B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6 and so on. The present invention can be applied to the display portion 2102.

FIG. 11C shows a mobile computer (mobile computer), which includes a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205.

FIG. 11D shows a goggle type display, which includes a main body 2301, a display section 2302, and an arm section 230.
3 and so on. The present invention can be applied to the display portion 2302.

FIG. 11E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402.

FIG. 11F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502.

FIG. 12A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other driving circuits.

FIG. 12B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to a liquid crystal display device 2808 forming a part of the LCD 702 and other driving circuits.

FIG. 12C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 12A and 12B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802, 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9. The projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 12D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 12C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 12D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 12, a case where a transmission type electro-optical device is used is shown, and examples of application to a reflection type electro-optical device and an EL display device are not shown.

FIG. 13A shows a mobile phone, and the main body 29 is shown.
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the display portion 2904.

FIG. 13B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003.

FIG. 13C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in various fields. Further, the electronic apparatus of the present embodiment can be realized by using a configuration composed of any combination of the first to fifth embodiments.

[0130]

[Effect of the present invention] By adopting the configuration of the present invention,
Basic significance as shown below can be obtained. (A) A simple structure suitable for a conventional TFT manufacturing process. (B) By applying a voltage, a current selectively flows through the metal compound present in the semiconductor film of the high resistance layer. Thus, only the metal compound can be heated to release the metal element. In addition, since the other regions are not heated, the capturing ability does not decrease. (C) The rate of diffusion of the released metal element is increased by application of a voltage. (D) This method is a method capable of improving the gettering ability and manufacturing a TFT having excellent electric characteristics while satisfying the above advantages.

[Brief description of the drawings]

FIG. 1 is a view showing an example illustrating a gettering technique disclosed by the present invention.

FIG. 2 is a view showing an example explaining a gettering technique disclosed by the present invention.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 6 is a top view illustrating a configuration of a pixel TFT.

FIG. 7 is a view showing an example illustrating a gettering technique disclosed by the present invention.

FIG. 8 is a view showing an example illustrating a gettering technique disclosed by the present invention.

FIG. 9 is a view showing an example illustrating a gettering technique disclosed by the present invention.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 11 illustrates an example of a semiconductor device.

FIG. 12 illustrates an example of a semiconductor device.

FIG. 13 illustrates an example of a semiconductor device.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 29/78 627F 627Z F term (Reference) 2H092 GA59 JA25 JA29 JA33 JA35 JA38 JA39 JA42 JA43 JA44 JA46 JB13 JB23 JB27 JB32 JB33 JB38 JB51 JB57 JB63 JB69 KA04 KA07 MA05 MA07 MA14 MA15 MA16 MA18 MA19 MA20 MA27 MA30 MA35 MA37 MA41 NA25 NA27 NA28 NA29 RA05 5F052 AA02 AA11 BB01 BB02 BB07 DA02 DA10 DB02 DB03 DB07 EA16 FA04 AFF DD01 DD03 DD05 DD13 DD14 DD15 DD17 EE01 EE02 EE03 EE04 EE14 EE23 EE44 EE45 FF02 FF03 FF04 FF09 FF28 FF30 GG01 GG02 GG13 GG25 GG32 GG43 NN45 NN47 NN23 NN04 NN PP13 PP27 PP29 PP34 PP35 QQ04 QQ09 QQ11 QQ25 QQ28

Claims (35)

[Claims] A step of introducing a metal element that promotes crystallization into the amorphous semiconductor film; a step of crystallizing the amorphous semiconductor film by heat treatment to form a crystalline semiconductor film; Etching a semiconductor film to form an island-shaped semiconductor layer, selectively introducing an impurity element into the island-shaped semiconductor film to form a plurality of impurity regions, and connecting to the plurality of impurity regions, respectively. Forming an electrode to be formed;
Applying a voltage to the electrode to getter the metal element to the impurity region. A step of introducing a metal element that promotes crystallization into the amorphous semiconductor film; a step of crystallizing the amorphous semiconductor film by heat treatment to form a first crystalline semiconductor film; Irradiating the first crystalline semiconductor film with a laser beam to form a second crystalline semiconductor film, and etching the second crystalline semiconductor film to form an island-like semiconductor layer; Forming a plurality of impurity regions by selectively introducing an impurity element into the island-shaped semiconductor film, forming electrodes connected to the plurality of impurity regions, and applying a voltage to the electrodes. A step of gettering the metal element in the impurity region. A step of introducing a metal element which promotes crystallization into the amorphous semiconductor film; a step of crystallizing the amorphous semiconductor film by heat treatment to form a crystalline semiconductor film; Etching a semiconductor film to form an island-like semiconductor layer; selectively introducing an impurity element into the island-like semiconductor film to form a source region and a drain region; Forming a source electrode or a drain electrode to be connected; and applying a voltage to the source electrode and the drain electrode to getter the metal element to the source region or the drain region. Of manufacturing a semiconductor device. 4. A step of introducing a metal element which promotes crystallization into the amorphous semiconductor film, and partially crystallizing the amorphous semiconductor film by heat treatment to form a first crystalline semiconductor film. Forming a second crystalline semiconductor film by irradiating a laser beam to the first crystalline semiconductor film, and forming an island-shaped semiconductor layer by etching the second crystalline semiconductor film. Forming a source region and a drain region by selectively introducing an impurity element into the island-shaped semiconductor film, and forming a source electrode or a drain electrode connected to the source region or the drain region;
Applying a voltage to the source electrode and the drain electrode to getter the metal element to the source region or the drain region. 5. A step of introducing a metal element that promotes crystallization into the amorphous semiconductor film, a step of crystallizing the amorphous semiconductor film by heat treatment to form a crystalline semiconductor film, Etching a semiconductor film to form an island-shaped semiconductor layer; forming an insulating film on the island-shaped semiconductor layer; forming a gate electrode on the insulating film; and using the gate electrode as a mask. Forming a source region and a drain region by selectively introducing an impurity element into the island-shaped semiconductor layer, and forming a channel formation region below the gate electrode; and selectively introducing the impurity element. Forming an interlayer insulating film in contact with the island-shaped semiconductor layer and the gate electrode, and forming a source electrode or a drain electrode connected to the source region or the drain region on the interlayer insulating film And applying a voltage to the source electrode and the drain electrode to getter the metal element from the channel formation region to the source region or the drain region. Production method. 6. A step of introducing a metal element that promotes crystallization into the amorphous semiconductor film, a step of crystallizing the amorphous semiconductor film by heat treatment to form a crystalline semiconductor film, Etching a semiconductor film to form an island-shaped semiconductor layer; forming an insulating film on the island-shaped semiconductor layer; forming a gate electrode on the insulating film; and using the gate electrode as a mask. Forming a source region and a drain region by selectively introducing an impurity element into the island-shaped semiconductor layer, and forming a channel formation region below the gate electrode; and selectively introducing the impurity element. Forming an interlayer insulating film in contact with the island-shaped semiconductor layer and the gate electrode, and forming a source electrode or a drain electrode connected to the source region or the drain region on the interlayer insulating film And applying a voltage to the gate electrode, the source electrode, and the drain electrode to getter the metal element from the channel formation region to the source region or the drain region. Of manufacturing a semiconductor device. 7. A step of introducing a metal element which promotes crystallization into the amorphous semiconductor film, and partially crystallizing the amorphous semiconductor film by heat treatment to form a first crystalline semiconductor film. Forming a second crystalline semiconductor film by irradiating a laser beam to the first crystalline semiconductor film, and forming an island-shaped semiconductor layer by etching the second crystalline semiconductor film. A step of forming an insulating film on the island-shaped semiconductor layer, a step of forming a gate electrode on the insulating film, and selectively forming an impurity element in the island-shaped semiconductor layer using the gate electrode as a mask. Introducing a source region and a drain region to form a channel forming region below the gate electrode; and forming an interlayer in contact with the island-shaped semiconductor layer and the gate electrode into which the impurity element is selectively introduced. Form insulating film Forming a source electrode or a drain electrode connected to the source region or the drain region on the interlayer insulating film; and applying a voltage to the source electrode and the drain electrode to remove the source from the channel formation region. A step of gettering the metal element to a region or the drain region. 8. A step of introducing a metal element which promotes crystallization into the amorphous semiconductor film, and partially crystallizing the amorphous semiconductor film by heat treatment to form a first crystalline semiconductor film. Forming a second crystalline semiconductor film by irradiating a laser beam to the first crystalline semiconductor film, and forming an island-shaped semiconductor layer by etching the second crystalline semiconductor film. A step of forming an insulating film on the island-shaped semiconductor layer, a step of forming a gate electrode on the insulating film, and selectively forming an impurity element in the island-shaped semiconductor layer using the gate electrode as a mask. Introducing a source region and a drain region to form a channel forming region below the gate electrode; and forming an interlayer in contact with the island-shaped semiconductor layer and the gate electrode into which the impurity element is selectively introduced. Form insulating film Forming a source electrode or a drain electrode connected to the source region or the drain region on the interlayer insulating film; and applying a voltage to the gate electrode, the source electrode, and the drain electrode to form the channel. A step of gettering the metal element from a region to the source region or the drain region. 9. A method for manufacturing a semiconductor device in which a gate electrode and a channel formation region and an impurity region are formed in an island-shaped semiconductor layer, wherein the island-shaped semiconductor film is a metal which promotes crystallization to an amorphous semiconductor film. Introducing an element, crystallizing the amorphous semiconductor film by heat treatment to form a crystalline semiconductor film,
The gate electrode is formed by etching the crystalline semiconductor film, the gate electrode is formed in contact with an insulating film formed on at least one surface of the island-shaped semiconductor layer, and after forming an electrode connected to the impurity region, Applying a voltage to the gate electrode and the electrode to getter the metal element from the channel formation region to the impurity region. 10. A method for manufacturing a semiconductor device in which a gate electrode and a channel formation region and an impurity region are formed in an island-shaped semiconductor layer, wherein the island-shaped semiconductor film is a metal which promotes crystallization to an amorphous semiconductor film. An element is introduced, the amorphous semiconductor film is crystallized by heat treatment to form a first crystalline semiconductor film, and the first crystalline semiconductor film is irradiated with a laser beam to form a second crystalline semiconductor film. Forming a film, etching the second crystalline semiconductor film, and forming the gate electrode in contact with an insulating film formed on at least one surface of the island-shaped semiconductor layer; Forming an electrode to be connected to the gate electrode and applying a voltage to the gate electrode and the electrode to getter the metal element from the channel formation region to the impurity region. Law. 11. A step of introducing a metal element that promotes crystallization into the amorphous semiconductor film; and a step of crystallizing the amorphous semiconductor film by heat treatment to form a crystalline semiconductor film.
Etching the crystalline semiconductor film to form an island-shaped semiconductor layer; selectively introducing an impurity element into the island-shaped semiconductor film to form a plurality of impurity regions; Forming electrodes connected to each other, and heating the island-shaped semiconductor film into which the impurity element is selectively introduced, and applying a voltage to the electrode to getter the metal element to the impurity region. And a method for manufacturing a semiconductor device. 12. A step of introducing a metal element that promotes crystallization into the amorphous semiconductor film, and a step of crystallizing the amorphous semiconductor film by heat treatment to form a first crystalline semiconductor film. Irradiating the first crystalline semiconductor film with a laser beam to form a second crystalline semiconductor film;
Forming an island-shaped semiconductor layer by etching the crystalline semiconductor film, forming a plurality of impurity regions by selectively introducing an impurity element into the island-shaped semiconductor film, and forming the plurality of impurity regions. Forming electrodes connected to each other,
Heating the island-shaped semiconductor film into which the impurity element has been selectively introduced, and applying a voltage to the electrode to getter the metal element to the impurity region. Method for manufacturing the device. 13. A step of introducing a metal element that promotes crystallization into the amorphous semiconductor film, and a step of crystallizing the amorphous semiconductor film by heat treatment to form a crystalline semiconductor film.
Etching the crystalline semiconductor film to form an island-shaped semiconductor layer; selectively introducing an impurity element into the island-shaped semiconductor film to form a source region and a drain region; Forming a source electrode or a drain electrode connected to the drain region, heating the island-shaped semiconductor layer into which the impurity element is selectively introduced, and applying a voltage to the source electrode and the drain electrode; A step of gettering the metal element in a source region or the drain region. 14. A step of introducing a metal element which promotes crystallization into an amorphous semiconductor film, and partially crystallizing the amorphous semiconductor film by heat treatment to form a first crystalline semiconductor film. Forming a second crystalline semiconductor film by irradiating a laser beam to the first crystalline semiconductor film;
Etching the second crystalline semiconductor film to form an island-shaped semiconductor layer; selectively introducing an impurity element into the island-shaped semiconductor film to form a source region and a drain region; Forming a source electrode or a drain electrode connected to a source region or a drain region, heating the island-shaped semiconductor layer into which the impurity element is selectively introduced, and applying a voltage to the source electrode and the drain electrode And gettering the metal element to the source region or the drain region. 15. A step of introducing a metal element that promotes crystallization into the amorphous semiconductor film, and a step of crystallizing the amorphous semiconductor film by heat treatment to form a crystalline semiconductor film.
Forming the island-shaped semiconductor layer by etching the crystalline semiconductor film, forming an insulating film on the island-shaped semiconductor layer, and forming a gate electrode on the insulating film;
Forming a source region and a drain region by selectively introducing an impurity element into the island-shaped semiconductor layer using the gate electrode as a mask, and forming a channel formation region below the gate electrode; Forming an interlayer insulating film in contact with the selectively introduced island-shaped semiconductor layer and the gate electrode; and forming a source electrode or a drain electrode connected to the source region or the drain region on the interlayer insulating film. Heating the island-shaped semiconductor layer into which the impurity element is selectively introduced, and applying a voltage to the source electrode and the drain electrode to transfer the voltage from the channel formation region to the source region or the drain region. Gettering the metal element;
A method for manufacturing a semiconductor device, comprising: 16. A step of introducing a metal element that promotes crystallization into the amorphous semiconductor film, a step of crystallizing the amorphous semiconductor film by heat treatment to form a crystalline semiconductor film,
Forming the island-shaped semiconductor layer by etching the crystalline semiconductor film, forming an insulating film on the island-shaped semiconductor layer, and forming a gate electrode on the insulating film;
Forming a source region and a drain region by selectively introducing an impurity element into the island-shaped semiconductor layer using the gate electrode as a mask, and forming a channel formation region below the gate electrode; Forming an interlayer insulating film in contact with the selectively introduced island-shaped semiconductor layer and the gate electrode; and forming a source electrode or a drain electrode connected to the source region or the drain region on the interlayer insulating film. Heating the island-shaped semiconductor layer into which the impurity element is selectively introduced, and applying a voltage to the gate electrode, the source electrode, and the drain electrode, from the channel formation region to the source region or A step of gettering the metal element to the drain region. 17. A step of introducing a metal element which promotes crystallization into an amorphous semiconductor film, and partially crystallizing the amorphous semiconductor film by heat treatment to form a first crystalline semiconductor film. Forming a second crystalline semiconductor film by irradiating a laser beam to the first crystalline semiconductor film;
Etching the second crystalline semiconductor film to form an island-shaped semiconductor layer, forming an insulating film on the island-shaped semiconductor layer, and forming a gate electrode on the insulating film; Forming a source region and a drain region by selectively introducing an impurity element into the island-shaped semiconductor layer using the gate electrode as a mask, and forming a channel formation region below the gate electrode; Forming an interlayer insulating film in contact with the selectively introduced island-shaped semiconductor layer and the gate electrode; and forming a source electrode or a drain electrode connected to the source region or the drain region on the interlayer insulating film. Heating the island-shaped semiconductor layer into which the impurity element is selectively introduced, and applying a voltage to the source electrode and the drain electrode to form the channel. The method for manufacturing a semiconductor device, characterized in that the forming region and a step of gettering the metal element to the source region or the drain region. 18. A step of introducing a metal element that promotes crystallization into an amorphous semiconductor film, and partially crystallizing the amorphous semiconductor film by heat treatment to form a first crystalline semiconductor film. Forming a second crystalline semiconductor film by irradiating a laser beam to the first crystalline semiconductor film;
Etching the second crystalline semiconductor film to form an island-shaped semiconductor layer, forming an insulating film on the island-shaped semiconductor layer, and forming a gate electrode on the insulating film; Forming a source region and a drain region by selectively introducing an impurity element into the island-shaped semiconductor layer using the gate electrode as a mask, and forming a channel formation region below the gate electrode; Forming an interlayer insulating film in contact with the selectively introduced island-shaped semiconductor layer and the gate electrode; and forming a source electrode or a drain electrode connected to the source region or the drain region on the interlayer insulating film. Heating the island-shaped semiconductor layer into which the impurity element is selectively introduced, and applying a voltage to the gate electrode, the source electrode, and the drain electrode. The method for manufacturing a semiconductor device, characterized in that it comprises a step of gettering the metal element to the source region or the drain region from the channel formation region by, a. 19. A method for manufacturing a semiconductor device in which a channel formation region and an impurity region are formed in a gate electrode and an island-like semiconductor layer, wherein the island-like semiconductor film is a metal which promotes crystallization to an amorphous semiconductor film. An element is introduced, the amorphous semiconductor film is crystallized by heat treatment to form a crystalline semiconductor film, and the crystalline semiconductor film is formed by etching. The gate electrode is formed at least in the island-like semiconductor layer. After forming an electrode connected to the impurity region, which is formed in contact with the insulating film formed on one surface, the island-shaped semiconductor layer is heated, and a voltage is applied to the gate electrode and the electrode. A method for manufacturing a semiconductor device, wherein the metal element is gettered from the channel formation region to the impurity region. 20. In a method for manufacturing a semiconductor device in which a channel formation region and an impurity region are formed in a gate electrode and an island-like semiconductor layer, the island-like semiconductor film is a metal that promotes crystallization to an amorphous semiconductor film. An element is introduced, the amorphous semiconductor film is crystallized by heat treatment to form a first crystalline semiconductor film, and the first crystalline semiconductor film is irradiated with a laser beam to form a second crystalline semiconductor film. Forming a film, etching the second crystalline semiconductor film, and forming the gate electrode in contact with an insulating film formed on at least one surface of the island-shaped semiconductor layer; After forming an electrode connected to the gate electrode, the island-shaped semiconductor layer is heated, and a voltage is applied to the gate electrode and the electrode to getter the metal element from the channel formation region to the impurity region. And a method for manufacturing a semiconductor device. 21. The method according to claim 11, wherein a temperature at which the island-shaped semiconductor film into which the impurity element is selectively introduced is heated to a temperature equal to or higher than a standard of a TFT. Of manufacturing a semiconductor device. 22. The method for manufacturing a semiconductor device according to claim 1, wherein the impurity element is an impurity element that imparts n-type or p-type to the semiconductor layer. 23. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a liquid crystal display device, an EL display device, or an image sensor. 24. The semiconductor device according to claim 1, wherein the semiconductor device is a mobile phone, a video camera, a digital camera, a projector, a goggle type display, a personal computer, a DVD player, an electronic dictionary, or portable information. A method for manufacturing a semiconductor device, which is a terminal. 25. A semiconductor device comprising: an insulating film formed on a semiconductor layer; and a gate electrode formed on the insulating film, wherein a concentration of a metal element in a source region of the semiconductor layer is lower than that of the semiconductor layer. A semiconductor device characterized by being higher than the channel forming region. 26. A semiconductor device comprising: an insulating film formed on a semiconductor layer; and a gate electrode formed on the insulating film, wherein a concentration of a metal element in a source region of the semiconductor layer is lower than that of the semiconductor layer. A semiconductor device characterized by being higher than the drain region. 27. A semiconductor device including an insulating film formed on a semiconductor layer, and a gate electrode formed on the insulating film, wherein a concentration of a metal element in a drain region of the semiconductor layer is lower than that of the semiconductor layer. A semiconductor device characterized by being higher than the channel forming region. 28. A semiconductor device comprising: an insulating film formed on a semiconductor layer; and a gate electrode formed on the insulating film, wherein a concentration of a metal element in a drain region of the semiconductor layer is lower than that of the semiconductor layer. A semiconductor device which is higher than the source region of the semiconductor device. 29. An insulating film formed on the gate electrode,
A semiconductor device comprising: a semiconductor layer formed on the insulating film; wherein a concentration of a metal element in a source region of the semiconductor layer is higher than that in a channel formation region of the semiconductor layer. 30. An insulating film formed on the gate electrode,
A semiconductor device comprising: a semiconductor layer formed on the insulating film; wherein the concentration of a metal element in a source region of the semiconductor layer is higher than that in a drain region of the semiconductor layer. 31. An insulating film formed on the gate electrode,
A semiconductor device comprising: a semiconductor layer formed on the insulating film; wherein a concentration of a metal element in a drain region of the semiconductor layer is higher than that in a channel formation region of the semiconductor layer. 32. An insulating film formed on the gate electrode,
A semiconductor device comprising: a semiconductor layer formed on the insulating film; wherein the concentration of a metal element in a drain region of the semiconductor layer is higher than that in a source region of the semiconductor layer. 33. The semiconductor device according to claim 25, wherein the metal element promotes crystallization of the semiconductor layer. 34. The semiconductor device according to claim 25, wherein the semiconductor device is a liquid crystal display device, an EL display device, or an image sensor. 35. The semiconductor device according to claim 25, wherein the semiconductor device is a mobile phone, a video camera,
A semiconductor device, which is a digital camera, a projector, a goggle-type display, a personal computer, a DVD player, an electronic dictionary, or a portable information terminal.