JP2002016071A - Silicon wafer and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form an IG layer which has no aggregate of point defects, and at the same time, has a gettering capability. SOLUTION: When a region that is placed adjacent to a region [I], where the silicon type point defect between lattices dominantly exists, belongs to a perfect region [P] where the aggregate of the point defect is not present, and is set to less than the minimum silicon concentration between the lattices for forming infiltration-type transposition is set to [PI], a region that is placed adjacent to a region [V], where a bore hole type point defect dominantly exists, belongs to the region [P], and is set to bore hole concentration or lower for forming COP or FPD is set to [PV], a wafer that consists of one or both of the [PV] and [PI], sets the concentration of oxygen to 0.5×1018 to 1.1×1018 atoms/cm3 (former ASTM), and is doped with nitrogen is heated at a heat-up rate of 40 deg.C/second from the room temperature up to 1, 250 deg.C under an atmosphere of nitrogen or the like, is maintained at 1,250 deg.C for 0 to 10 seconds, and furthermore, is cooled at a temperature decrease speed of 50 deg.C/second from 1,250 deg.C to the room temperature.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides an intrinsic gettering (IG) effect on a silicon wafer formed by the Czochralski method (hereinafter, referred to as CZ method) free of point defect aggregates. It relates to a manufacturing method. More particularly, the present invention relates to a method for producing a silicon wafer which sufficiently expresses oxygen precipitation nuclei and exhibits an IG effect in a heat treatment in a device production process, and a silicon wafer produced by the method.

[0002]

2. Description of the Related Art In recent years, in the process of manufacturing a semiconductor integrated circuit, an oxidation-induced stacking fault (hereinafter referred to as OSF) is a cause of lowering the yield.
That. ) Nuclei of oxygen precipitates and microcrystalline particles (Crystal Originated Particl
e, hereinafter referred to as COP. ) Or interstitial dislocations (Int
erstitial-type Large Dislocation, hereinafter referred to as LD. ). OSF introduces minute defects serving as nuclei during crystal growth, becomes apparent in a thermal oxidation step or the like when manufacturing a semiconductor device, and causes defects such as an increase in leak current of the manufactured device. Also COP
Are pits caused by crystals that appear on the wafer surface when the mirror-polished silicon wafer is washed with a mixed solution of ammonia and hydrogen peroxide. When this wafer is measured with a particle counter, these pits are also detected as light scattering defects together with the original particles. This C
OP is an electrical characteristic, for example, a time-dependent dielectric breakdown characteristic (Time Dependent dielectric Breakdown, TDD) of an oxide film.
B), oxide film breakdown voltage characteristics (Time Zero Dielectric Breakdo
wn, TZDB) and the like. Also COP
Is present on the wafer surface, a step is generated in a device wiring process, which may cause disconnection. This also causes a leak and the like in the element isolation portion, and lowers the product yield. Furthermore, LD is also called a dislocation cluster,
Alternatively, when a silicon wafer having this defect is immersed in a selective etching solution containing hydrofluoric acid as a main component, a pit is generated, and thus the silicon wafer is also called a dislocation pit. This LD also causes deterioration of electrical characteristics such as leak characteristics and isolation characteristics.

[0003] From the above, OSF, CO, etc. can be obtained from a silicon wafer used for manufacturing a semiconductor integrated circuit.
There is a need to reduce P and LD. A defect-free silicon wafer having no OSF, COP and LD is disclosed in JP-A-11-1393. This defect-free silicon wafer has a perfect region [P] when a perfect region in which no aggregate of vacancy type point defects and no aggregate of interstitial silicon type point defects are present in a silicon single crystal ingot is defined as [P]. P] is a silicon wafer cut from the ingot. The perfect region [P] is located between the region [I] where interstitial silicon type point defects predominantly exist and the region [V] where vacancy type point defects predominantly exist in the silicon single crystal ingot. Intervene. This perfect area [P]
In the silicon wafer made of, the pulling speed of the ingot is V (mm / min), and the temperature gradient in the vertical direction of the ingot near the interface between the silicon melt and the ingot is G.
(° C./mm), V / G (mm ² / min · ° C.) is determined so that the OSF generated in a ring shape during the thermal oxidation treatment disappears at the center of the wafer. .
On the other hand, some of the semiconductor device manufacturers include OSF, CO
Some manufacturers seek silicon wafers that do not have P and LD, but also have the ability to getter metal contamination from device processing. If the wafer does not have sufficient gettering ability, contamination with metal in the device process causes junction leakage, device operation failure due to trap levels due to metal impurities, and the like, thereby lowering product yield.

[0004]

However, a silicon wafer cut from the ingot consisting of the perfect region [P] does not have an OSF, a COP and an LD. Oxygen precipitation does not occur, so that the IG effect may not be sufficiently obtained. An object of the present invention is to form either one of the region [P _V ] or the region [P _I ] or a mixed region of both, and the oxygen concentration is 0.5 × 10 ^18.
Even a silicon wafer cut from an ingot of 1.1 × 10 ¹⁸ atoms / cm ³ (former ASTM) is subjected to a predetermined heat treatment for a relatively short time to reduce point defects. It is an object of the present invention to provide a method of manufacturing a silicon wafer and a silicon wafer manufactured by the method, in which an IG layer having no getter and having gettering ability can be formed. Another object of the invention is
An object of the present invention is to provide a method of manufacturing a silicon wafer and a silicon wafer manufactured by the method, which do not require an oxygen donor killer process.

[0005]

The invention according to claim 1 is
As shown in FIG. 1 to FIG.
Elementary 1 × 10^Ten~ 1 × 10¹⁴atoms / cm^ThreeDope
Grown silicon single crystal ingot
Region in which interstitial silicon-type point defects predominantly exist
Is defined as [I], and the region where the vacancy type point defect is
[V], and aggregates and vacancies of interstitial silicon type point defects
A perfect area where no agglomerates of mold point defects exist
When [P] is set, an image consisting of the perfect area [P]
A point-free agglomerate
This is a method for manufacturing a recon wafer. Its characteristic configuration
Is adjacent to the region [I] and in the perfect region [P].
Lowest interstitial silicon concentration that belongs to and can form interstitial dislocations
The area less than [P_I] And adjacent to the area [V]
The COP or FPD belonging to the
The region below the obtained vacancy concentration is [P_V] And the area
[P_V] Or area [P_I] Either one or both
And the oxygen concentration is 0.5 × 10 ¹⁸~
1.1 × 10¹⁸atoms / cm^Three(Former ASTM)
Pull the silicon single crystal ingot and remove it from the ingot
Nitrogen, argon, hydrogen,
1100 from room temperature in an atmosphere of oxygen or a mixed gas of oxygen
Heating up to 1300 ° C at a heating rate of 10-100 ° C / sec
And hold at 1100-1300 ° C. for 0-10 seconds,
1100-1300 ° C to room temperature 10-100 ° C / sec
Cooling at the rate of temperature decrease.

In the method of manufacturing a silicon wafer according to the present invention, the oxygen concentration of the nitrogen-doped ingot is 0.5 × 10 ^{18 to} 1.1 × 10 ¹⁸ atoms / c.
m ³ (old ASTM), and when the silicon wafer is composed of either one of the region [P _V ] or the region [P _I ] or a mixed region of both, the silicon cut out from this ingot By subjecting the wafer to the heat treatment (rapid heating and rapid cooling) for a relatively short time as described above, the oxygen precipitation nuclei also appear in the region [P _I ] where the oxygen precipitation nuclei are not introduced during the crystal growth. In the region [P _V ] in which the oxygen precipitation nuclei are introduced, the density of the oxygen precipitation nuclei increases. Therefore, when a wafer subjected to the above heat treatment is subjected to thermal oxidation treatment in a device manufacturing process of a semiconductor device manufacturer, the oxygen precipitate nucleus becomes an oxygen precipitate (Bulk Micro).
Defect, hereinafter referred to as BMD. ), And an IG layer having a gettering ability is formed on the wafer even if the wafer is formed of either the region [P _V ] or the region [P _I ] or a mixed region of both. That is, the entire surface of the wafer exhibits the IG effect.

According to a second aspect of the present invention, there is provided a silicon wafer manufactured by the method according to the first aspect. In the silicon wafer according to the second aspect, after the thermal oxidation treatment in the device manufacturing process, an IG layer having no gettering agglomerates and having a gettering ability is formed on the wafer. The entire surface exhibits the IG effect.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The silicon wafer of the present invention has a C
After the ingot (nitrogen dope) is pulled up from the silicon melt in the hot zone furnace by the Z method with a predetermined pulling speed profile based on the Voronkov theory,
It is produced by cutting out this ingot. Generally, CZ
When a silicon single crystal ingot is pulled up from a silicon melt in a hot zone furnace by a method, point defects and agglomerates (agglomerates: three-dimensional defects) are generated as defects in the silicon single crystal. .
Point defects have two general forms: vacancy type point defects and interstitial silicon type point defects. A vacancy-type point defect is one in which one silicon atom has separated from one of the normal positions in the silicon crystal lattice. Such holes become hole type point defects. On the other hand, if an atom is found at a position (interstitial site) other than the lattice point of the silicon crystal, this becomes an interstitial silicon point defect.

[0009] Point defects are generally formed at the interface between the silicon melt (molten silicon) and the ingot (solid silicon). However, by continuously pulling up the ingot, the portion that was the contact surface starts to cool down with pulling up. During cooling, vacancy-type point defects or interstitial silicon-type point defects merge with each other by diffusion to form vacancy agglomerates or interstitial agglomerates. Is formed. In other words, the aggregate is a three-dimensional structure generated due to the merging of point defects. Aggregates of vacancy-type point defects are LSTDs (Laser Scattering Tomograms) in addition to the COPs described above.
An agglomerate of interstitial silicon-type point defects includes a defect called LD, which includes a defect called aph defects or FPD (Flow Pattern Defects). FPD refers to a silicon wafer manufactured by cutting an ingot into 30 pieces.
Secco etching (HF: K ₂ Cr ₂₎
LSTD is a source of traces exhibiting a unique flow pattern which appears when O ₇ (0.15 mol / l) = 2: 1 mixture is etched). Is a source having a different refractive index from that of scattered light.

Boronkov's theory states that in order to grow a high-purity ingot having a small number of defects, the pulling speed of the ingot is set to V (mm / min), and the temperature gradient in the vertical direction of the ingot near the interface between the ingot and the silicon melt. G (° C / m
m) is to control V / G (mm ² / min · ° C.). In this theory, as shown in FIG.
G is plotted on the abscissa, and the vacancy type point defect concentration and the interstitial silicon type point defect concentration are plotted on the same ordinate, and the relationship between V / G and the point defect concentration is schematically represented. This explains that the boundary of the silicon region is determined by V / G. More specifically, when the V / G ratio is equal to or higher than the critical point, an ingot in which the vacancy type point defect concentration is dominant is formed, while the V / G ratio is increased.
When the G ratio is lower than the critical point, an ingot in which the interstitial silicon type point defect concentration is dominant is formed. In FIG. 1, [I] indicates a region where the interstitial silicon type point defect is dominant and an interstitial silicon type point defect exists ((V / G) ₁ or less), and [V] indicates a region within the ingot. Is the dominant vacancy type point defect, and the region where the aggregate of the vacancy type point defect exists ((V /
G) ₂ or more, and [P] is a perfect region ((V / G) _1- (V / G) ₂ ) in which no aggregate of vacancy type point defects and no aggregate of interstitial silicon type point defects are present. Is shown. Area [P]
The region [V] adjacent to the region [V]
SF] ((V / G) ₂ to (V / G) ₃ ).

The perfect region [P] is further classified into a region [P _I ] and a region [P _V ]. [P _I ] is V / G
The ratio is from (V / G) ₁ to the critical point,
[P _V ] is a region where the V / G ratio is from the critical point to the above (V / G) ₂ . That is, [P _I ] is a region adjacent to the region [I] and having an interstitial silicon type point defect concentration lower than the lowest interstitial silicon type point defect concentration capable of forming an interstitial dislocation, and [P _V] ] Is a region adjacent to the region [V] and having a vacancy-type point defect concentration lower than the lowest vacancy-type point defect concentration capable of forming an OSF. The predetermined pull rate profile of the present invention is such that when the ingot is pulled from the silicon melt in a hot zone furnace, the ratio of the pull rate to the temperature gradient (V / G) reduces the generation of interstitial silicon-type point defect aggregates. The first critical ratio ((V / G) ₁ ) or more, which limits the agglomerates of vacancy-type point defects to a region in the center of the ingot where vacancy-type point defects predominantly exist. It is determined so as to be maintained at 2 critical ratio ((V / G) ₂ ) or less.

The pulling speed profile is determined based on the above-mentioned Boronkov theory by simulation by experimentally cutting out the reference ingot in the axial direction or by combining these techniques. That is, after the simulation, after the simulation, the ingot cut in the axial direction is cut in the transverse direction and the state is confirmed in the wafer state,
This is performed by repeating the simulation.
For the simulation, a plurality of kinds of pulling speeds are determined within a predetermined range, and a plurality of reference ingots are grown. As shown in FIG. 2, the pulling speed profile for the simulation ranges from a high pulling speed (a) of 1.2 mm / min to a low pulling speed (c) of 0.5 mm / min.
And again adjusted to a high pulling speed (d). The low pull rate may be 0.4 mm / min or less, and the change in pull rates (b) and (d) is preferably linear. A plurality of reference ingots pulled at different speeds are individually cut in the axial direction. Optimal V / G
Is determined from the correlation of the results of the axial cutting, wafer verification and simulation, followed by the determination of the optimal pulling speed profile and the production of the ingot with that profile. The actual pulling speed profile will depend on many variables including but not limited to the desired ingot diameter, the particular hot zone furnace used and the quality of the silicon melt.

FIG. 3 shows a cross-sectional view of the ingot when V / G is continuously reduced by gradually lowering the pulling speed. FIG. 3 shows a region [V] in which vacancy type point defects predominantly exist in the ingot, a region [I] in which interstitial silicon type point defects predominantly exist, and a vacancy type point defect. The perfect regions where no aggregates of the above-mentioned and aggregates of interstitial silicon type point defects are present are indicated as [P], respectively. As described above, the perfect area [P] is further classified into an area [P _I ] and an area [P _V ]. The region [P _V ] is a region where vacancy type point defects which do not form an aggregate exist in the perfect region [P], and the region [P _I ] is an interstitial silicon type which does not form an aggregate in the perfect region [P]. This is an area where a point defect exists. Specifically, the axial position of the ingot in FIG. 3 is a region where interstitial silicon type point defects are predominantly present, and the axial position is a region where vacancy type point defects are predominantly present. direction position - is an area according to the present invention, there is provided a perfect area without agglomerates of aggregates and interstitial silicon type point defects vacancy type point defects, the region [P _V] or the region [P _I] of Either one region or a mixed region of both.

Nitrogen is added to the ingot at a rate of 1 × 10 ¹⁰ to 1 × 10
¹⁴ atoms / cm ³ , preferably 5 × 10 ¹² to 1 × 1
By doping at 0 ¹⁴ atoms / cm ³ , aggregates of point defects do not occur in one of the region [P _V ] and the region [P _I ] or a mixed region of both, and the region [P _V ]
As the density of oxygen precipitation nuclei increases, oxygen precipitation nuclei having a desired density or more can be formed in the region [P _I ]. As a method of doping nitrogen into the ingot, it is possible to throw the ingot into polycrystalline silicon mixed with nitride or into a polycrystalline silicon melt having a nitride film formed when the ingot is pulled up, or to pull up the ingot in a nitrogen atmosphere. It is performed by Doping amount of nitrogen is 1 × 10 ¹⁰ to 1 × 10 ¹⁴ atom
s / cm ³ is limited to 1 × 10 ¹⁰ atoms / c
not obtained the effect of promoting the formation of the oxygen precipitates is less than m ^3, since the electrical compensation exceeds 1 × 10 ¹⁴ atoms / cm ³ deviates from a desired resistivity. That is, if the doping amount of nitrogen (which replaces silicon with nitrogen) that makes the wafer N-type becomes large in the wafer which becomes P-type by doping with boron, the P-type and N-type cancel each other, and the resistance becomes higher. This is because the value increases.

Further, a small area (FIG. 1 (V /
G) ₂ to (V / G) ₃ ) are regions where neither COP nor LD occurs in the wafer surface. However, the silicon wafer including this region is subjected to a conventional OSF revealing heat treatment in an oxygen atmosphere at a temperature of 1000 ° C. ± 30 ° C. for 2 hours.
Heat treatment for ５5 hours, followed by heat treatment at a temperature of 1130 ° C. ± 30 ° C. for 1 to 16 hours produces OSF. That is, in the above-mentioned wafer, an OSF ring is generated around a half of the radius of the wafer. COP tends to appear in a region surrounded by the OSF ring and in which vacancy-type point defects are predominantly present.

Incidentally, aggregates of point defects such as COP and LD may have different values of detection sensitivity and detection lower limit depending on the detection method. Therefore, in the present specification, "there is no aggregate of point defects" means the product of the observation area and the etching allowance by an optical microscope after subjecting a mirror-finished silicon single crystal to non-stirring seco etching. When observed as an inspection volume, one agglomerate of flow pattern (vacancy type defect) and dislocation cluster (interstitial silicon type point defect) has one defect per 1 × 10 ⁻³ cm ³ of inspection volume. The lower limit of detection (1 × 10 ³ / cm ³ )
Means that the number of point defect aggregates is equal to or less than the lower limit of detection. The silicon wafer of the present invention is a wafer cut out at the axial position of the ingot described above, and the plan views thereof are shown in FIGS. 4A to 4C, respectively. In order to generate oxygen precipitation nuclei of a desired density or more on the wafer by the heat treatment of rapid heating and rapid cooling of the present invention, the oxygen concentration of the wafer is 0.5 × 10 ^{18 to} 1.1 × 10 ¹⁸ atoms / s. cm
³ (old ASTM).

Next, the heat treatment for rapid heating and rapid cooling of the silicon wafer will be described. In this heat treatment, the wafer is heated from room temperature to 1100 to 1300 under an atmosphere of nitrogen, argon, hydrogen, oxygen or a mixed gas thereof.
To a temperature of 20 to 70 ° C./sec.
Hold at ３００1300 ° C. for 0-10 seconds, then 1100-1
It is performed by cooling from 300 ° C. to room temperature at a cooling rate of 20 to 100 ° C./sec. Here, the holding time of 0 seconds means that the temperature is lowered immediately after the temperature is raised and is not maintained at the predetermined temperature. The wafer is introduced into a heat treatment furnace maintained at room temperature or a heat treatment furnace that has hundreds of degrees of residual heat in the case of continuous operation, and an incandescent lamp, halogen lamp, arc Irradiate with radiation such as lamps, graphite heaters, etc.
The temperature is raised to 1100 to 1300 ° C at a rate of 0 to 100 ° C / sec, preferably 20 to 70 ° C / sec. When the heating rate is less than 10 ° C./second, the number of oxygen precipitation nuclei increases, but the processing ability is inferior and is not practical. If the holding temperature is lower than 1100 ° C., the number of oxygen precipitation nuclei does not sufficiently increase, and the IG effect cannot be sufficiently exhibited when a thermal oxidation treatment is performed in a device manufacturing process of a semiconductor device manufacturer. Holding temperature is 130
If the temperature exceeds 0 ° C. or the holding time exceeds 10 seconds, slips occur or the productivity of the heat treatment decreases. On the other hand, if the temperature rise rate exceeds 100 ° C./sec, there occurs a problem that slip occurs due to its own weight stress and variation in in-plane temperature distribution.

On the other hand, the cooling is performed by stopping or gradually lowering the irradiation of radiation light from an incandescent lamp or the like of the heat treatment furnace maintained at the above-mentioned predetermined temperature, to 10 to 100 ° C./sec, preferably 20 to 100 ° C./sec.
Cool to room temperature at a rate of 100 ° C./sec. If the cooling rate is less than 10 ° C./sec, sufficient oxygen precipitation nuclei are not formed,
If the cooling rate exceeds 100 ° C./sec, the difference in the temperature distribution in the plane becomes large, and there is a problem that slip occurs. As described above, heat treatment in a shorter time than before (the sum of the rapid heating time, the holding time at a predetermined temperature, and the rapid cooling time)
The reason is that nitrogen is doped in the ingot before the wafer is cut out. As a result, no point defect aggregate exists in either one of the region [P _V ] or the region [P _I ] or a mixed region thereof, and the density of oxygen precipitate nuclei in the region [P _V ] is reduced. As the density increases, oxygen precipitation nuclei having a density higher than the desired density are also formed in the region [P _I ]. Therefore, the wafer after the heat treatment is subjected to thermal oxidation treatment in the semiconductor device manufacturing process, so that the wafer has gettering ability. The IG layer is formed, and the wafer can exhibit the IG effect.

By shortening the heat treatment as described above, the haze of the silicon wafer (the degree to which the wafer surface looks whitish when the silicon wafer is illuminated with a spotlight) and the micro-roughness (after mirror-polishing the silicon wafer) 100-100 of the wafer surface
Surface roughness at a pitch of 0 nm), slip (crystal defects caused by slippage in the crystal of the silicon wafer) and contamination (Cu, Fe, Cr, Ni) are reduced. Further, by performing the heat treatment, the oxygen donor killer treatment in the wafer process becomes unnecessary.

[0020]

Next, examples of the present invention will be described together with comparative examples. <Example 1> Diameter 8 using a silicon single crystal pulling apparatus
Inch boron (B) and nitrogen (N) doped p
The mold silicon ingot was pulled up. This ingot has a straight body length of 1200 mm, a crystal orientation of (100),
The resistivity is about 10Ωcm and the oxygen concentration is 0.9 × 10 ¹⁸ at.
oms / cm ³ (old ASTM). The ingot has a V / G during pulling of 0.28 mm ² / min.
^Two seedlings were grown under the same conditions while continuously decreasing the temperature to 16 mm2 / min. One of them is ingot 3
As shown in (1), the center of the ingot was cut in the pulling direction, the position of each region was examined, and a silicon wafer at another axial position in FIG. In this example, the sample wafer has a region [P _V ] at the center,
FIG. 4B is a wafer having a region [P _I ] around the wafer shown in FIG. The wafer was cut from the ingot and mirror-polished.
It was heated at a rate of 0 ° C./sec, kept at 1250 ° C. for 3 seconds, and further cooled at a rate of 50 ° C./sec. In addition, in order to prevent nitriding of the surface, 1% oxygen was flowed simultaneously with nitrogen up to 1250 to 700 ° C.

Example 2 A heat treatment was performed in the same manner as in Example 1 using a wafer which was cut out from the same ingot as in Example 1 at the axial position in FIG. 3 and mirror-polished. <Example 3> A heat treatment was performed in the same manner as in Example 1 by using a wafer cut out from the same ingot as in Example 1 at the axial position in FIG.

<Embodiment 4> A wafer which was cut out from the same ingot as in Embodiment 1 at the axial position shown in FIG. 3 and polished to a mirror surface was subjected to 40 ° C. from room temperature to 1250 ° C. in an argon atmosphere.
/ Second, heated at 1250 ° C. for about 3 seconds, and further cooled at a rate of 50 ° C./second. <Example 5> A wafer which was cut out from the same ingot as in Example 1 at the axial position shown in FIG. 3 and mirror-polished was subjected to 40 ° C./sec from room temperature to 1250 ° C. in an atmosphere of 50% and 50% argon and nitrogen, respectively. Heating at a heating rate,
The temperature was kept at 250 ° C. for about 3 seconds, and then cooled at a temperature decreasing rate of 50 ° C./sec.

Comparative Example 1 Under the same conditions as in Example 1, a wafer was cut from an ingot grown without doping with nitrogen at an axial position shown in FIG. 3 and mirror-polished, from room temperature to 1250.degree. The sample was heated at a rate of temperature increase of 1 ° C./second, kept at 1250 ° C. for 3 seconds, and further cooled at a rate of decrease of 50 ° C./second. <Comparative Example 2> A wafer cut out from the same ingot as in Comparative Example 1 at the axial position in FIG. 3 and mirror-polished is heated in a nitrogen atmosphere from room temperature to 1250 ° C. at a heating rate of 40 ° C./sec. The temperature was maintained for 50 seconds and cooled at a rate of 50 ° C./second.

<Comparative Test and Evaluation> Simulating the heat treatment in the device manufacturing process of a semiconductor device manufacturer, two wafers of each of Examples 1 to 5 and Comparative Examples 1 and 2 were each placed under an oxygen atmosphere at 800 ° C. for 4 hours. After the holding, a heat treatment of holding at 1000 ° C. for 16 hours in an oxygen atmosphere was performed. Next, the haze and microroughness of each of the two wafers were measured. The other wafer of the two is cleaved, the wafer surface is selectively etched with a Wright etchant, and observed by an optical microscope to a depth of 350 μm from the wafer surface.
, The presence or absence of slip, the degree of contamination, the BMD volume density, and the width of a denuded zone (hereinafter referred to as DZ) were measured for portions corresponding to the region [P _V ] and the region [P _I ].

The above haze can be adjusted to a gain of 7 using a particle counter (Surf Scan 6200: manufactured by KLA Tencor).
The micro roughness was evaluated by AF
1000 × 1000 nm using M (atomic force microscope)
The evaluation was performed by measuring the average roughness (Ra) of the measurement region of (1). The presence or absence of slip was evaluated using X-ray topography, and the degree of contamination was evaluated by measuring metal contamination (Cu, Fe, Cr) on the wafer surface using an atomic absorption method. Further, the BMD volume density was determined by observing with an optical microscope the BM of the entire surface of the wafer from the wafer center to the wafer periphery at a depth of 100 μm from the wafer surface.
The D volume width was evaluated by measuring the D volume density, and the Dz width was evaluated by measuring the depth from the wafer surface in a region where no bulk defect was observed by an optical microscope.
Table 1 shows the heat treatment conditions of the wafers of Examples 1 to 5 and Comparative Examples 1 and 2, and the cutout position in FIG. 3, and shows the haze, microroughness, presence / absence of slip, degree of contamination, BMD volume density, and width of Dz. It is shown in FIG. Also, in Table 2, N.P. D. Is an abbreviation of “Not Detect (lower than the lower detection limit)”.

[0026]

[Table 1]

[0027]

[Table 2]

As is clear from Tables 1 and 2, in the nitrogen-doped wafers of Examples 1 to 4, a sufficient amount of oxygen was precipitated even with a heat treatment time (annealing time) as short as 3 seconds. It was found that the Dz width was also secured. On the other hand, in the wafer of Comparative Example 1 not doped with nitrogen, a predetermined BMD volume density could not be secured,
In the wafer of Comparative Example 2 not doped with nitrogen,
Although the heat treatment time (annealing time) was increased to 30 seconds to secure a predetermined BMD volume density, it was found that slip and contamination occurred and the surface roughness of the wafer was increased.

[0029]

As described above, according to the heat treatment method of the present invention, the heat treatment method comprises either the region [P _V ] or the region [P _I ] or a mixed region of both, and has an oxygen concentration of 0.
5 × 10 ^{18 to} 1.1 × 10 ¹⁸ atoms / cm ³ (former A
STM) nitrogen-doped silicon wafer
Heat from room temperature to 1100 to 1300 ° C. at a heating rate of 10 to 100 ° C./sec under an atmosphere of nitrogen or the like.
Hold at 300 ° C. for 0 to 10 seconds, then 1100 to 130
By performing a short-time heat treatment of cooling from 0 ° C. to room temperature at a cooling rate of 10 to 100 ° C./sec, in addition to the absence of point defect aggregates, the density of oxygen precipitation nuclei in the region [P _V ] And the oxygen precipitation nuclei having a density higher than the desired density are formed in the region [P _I ]. As a result, by performing a thermal oxidation process in a semiconductor device manufacturing process on the wafer that has completed the heat treatment, an IG layer having gettering ability is formed on the wafer, and the wafer can exhibit an IG effect. Further, by performing the heat treatment of the present invention, there is also an advantage that the oxygen donor killer treatment conventionally performed becomes unnecessary.

[Brief description of the drawings]

FIG. 1 is a diagram based on Bornkov's theory showing that when the V / G ratio is above the critical point, a vacancy-rich ingot is formed, and when the V / G ratio is below the critical point, an interstitial silicon-rich ingot is formed. .

FIG. 2 is a characteristic diagram showing a change in pulling speed for determining a desired pulling speed profile.

FIG. 3 is a schematic diagram of an X-ray topography showing a region where holes of a reference ingot are predominantly present, a region where interstitial silicon is predominantly present, and a perfect region according to the present invention.

FIG. 4A is a plan view of a wafer in which a [P _V ] region appears on a silicon wafer corresponding to the position in FIG. 3; (B) A plan view of the wafer where the [P _V ] region and the [P _I ] region appear on the silicon wafer corresponding to the position in FIG. (C) A plan view of the wafer in which the [P _I ] region appears on the silicon wafer corresponding to the position in FIG.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takaaki Shiota 1-5-1, Otemachi, Chiyoda-ku, Tokyo Within Mitsubishi Materials Silicon Corporation (72) Inventor Hisashi Furuya 1-chome, Otemachi, Chiyoda-ku, Tokyo No.5-1 Inside Mitsubishi Materials Silicon Co., Ltd. (72) Inventor Jae-gun Park South Korea, Seoul, Songdong-gu, Haendang-dong 17, Hannan University, Olympic Gym 330 F-term (reference) 4G077 AA02 AB01 CF10 FE02 FE03 FE05 FE12 FE13

Claims (2)

[Claims] 1. The method according to claim 1, wherein nitrogen is 1 × 1 by the Czochralski method.
A silicon single crystal ingot doped with 0 ¹⁰ to 1 × 10 ¹⁴ atoms / cm ³ is grown, and a region where interstitial silicon type point defects are predominantly present in the ingot is defined as [I]. When a region where defects are predominantly present is [V], and a perfect region where no aggregate of interstitial silicon type point defects and no aggregate of vacancy type point defects are present is [P], the perfect region [P] A method for producing a silicon wafer free of point defect aggregates cut from an ingot, the method comprising: forming an interstitial dislocation adjacent to the region [I] and belonging to the perfect region [P]. the area below the minimum interstitial silicon concentration of [P _I], the vacancy concentration following areas capable of forming adjacent and the belonging to the perfect region [P] COP or FPD in the region [V] When the P _V], the region [P _V] or the region [P _I either areas or becomes and oxygen concentration from the mixing region of both] 0.5
× 10 ^{18 to} 1.1 × 10 ¹⁸ atoms / cm ³ (old AS
TM), a silicon single crystal ingot is pulled up, and a silicon wafer cut from the ingot is heated from room temperature to 1100 ° C. to 1300 ° C. under an atmosphere of nitrogen, argon, hydrogen, oxygen or a mixed gas thereof.
/ S at a heating rate of 1 / sec.
A method for producing a silicon wafer, wherein the method is held for 10 seconds, and further cooled from 1100 to 1300 ° C. to room temperature at a rate of 10 to 100 ° C./sec. 2. A silicon wafer manufactured by the method according to claim 1.