JP2002009609A - Output port - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an output port by which a current consumed in a level shifter section can be revised, depending on a required state for reducing the current consumption. SOLUTION: The output port, having a level shifter section consisting of a level shifter circuit 22 and having a switching control section in response to an input, is provided with a control means consisting of control P-channel transistors(TRs) 17, 18, 19, 20 that selectively change the drive capability of the level shifter circuit 22 through the control of an active element which consists of operating P-channel TRs 2', 3' that are components of the level shifter circuit 22 depending on an input type by operating speeds.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an output port, and more particularly to an output port having a level shifter circuit and capable of outputting a plurality of events.

[0002]

2. Description of the Related Art An output port having a level shifter circuit and capable of outputting a plurality of events is shown in FIG. In FIG. 3, the level shifter circuit 8 includes an event switching signal 7 and an Nch transistor 5 whose gate receives an event signal 13 selected by the event switching signal 7.
And an inverter 6 operating at a power supply voltage of 3 V, an Nch transistor 4 to which an output signal from the inverter is input to a gate, and two Pch transistors 2 and 3 operating at a power supply voltage of 5 V.

The event switching signal 7 switches between an output port output 9 from an internal circuit operating at 3V and an address output 10, and the selected signal is converted to a 5V operation by the level shifter circuit 8. The converted signal is input to the inverter 11 and the signal is
Is output to However, in order to respond to high-speed events with a short period such as address output, Pc
Large transistors are used for the h transistors 2 and 3.

[0004]

In the above-described circuit, the same level shifter circuit is used in any event. Therefore, even when a high-speed operation is not required at a long period such as a port output, for example, even if a high-speed operation is unnecessary. There is a problem that the current consumed in the level shifter is the same.

An object of the present invention is to make it possible to change the current consumed by the level shifter according to the required situation and to reduce the current consumption in order to solve the above-mentioned problems.

[0006]

According to a first aspect of the present invention, an output port having a level shifter section comprising a level shifter circuit and a switching control section corresponding to an input includes an operation element constituting the level shifter circuit. A control means for controlling and selectively changing the driving capability of the level shifter circuit is provided.

In an output port according to a second aspect of the present invention, in an output port having a level shifter section comprising a level shifter circuit and a switching control section corresponding to an input, an operation element constituting the level shifter circuit is controlled in accordance with an input type. Control means for selectively changing the driving capability of the level shifter circuit.

In an output port according to a third aspect of the present invention, in an output port having a level shifter unit composed of a level shifter circuit and a switching control unit according to an input, an operating element constituting the level shifter circuit according to an input type based on an operation speed In order to selectively change the driving capability of the level shifter circuit.

In the output port according to the fourth aspect of the present invention, the level shifter circuit is connected to the first N input terminal for inputting an input signal to the gate.
a channel transistor, a second Nch transistor whose input signal is input to a gate via an inverter, and first and second Pch transistors operated by the first and second Nch transistors. , A third and fourth P connected in series with each other
a channel transistor is connected in parallel with the first Pch transistor, and a fifth and sixth Pch transistor connected in series with each other are connected in parallel with the second Pch transistor, and the third and fifth Pch transistors are connected. The first and second Pch transistors are controlled by controlling the gate input to the transistor according to the input type.

In an output port according to a fifth aspect of the present invention, in an output port having a level shifter section comprising a level shifter circuit and a switching control section corresponding to an input, an operation of configuring the level shifter circuit in accordance with an operation state caused by input application A control means for controlling the elements to selectively change the driving capability of the level shifter circuit is provided.

[0011] In the output port according to the sixth aspect of the invention, the level shifter circuit may be provided with a first N input signal to a gate.
a channel transistor, a second Nch transistor whose input signal is input to a gate via an inverter, and first and second Pch transistors operated by the first and second Nch transistors. , A third and fourth P connected in series with each other
a channel transistor is connected in parallel with the first Pch transistor, and a fifth and sixth Pch transistor connected in series with each other are connected in parallel with the second Pch transistor, and the third and fifth Pch transistors are connected. The first and second Pch transistors are controlled by controlling a gate input to a transistor in accordance with an operation state by applying the input signal.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Embodiment 1 of the present invention will be described with reference to FIG. FIG. 1 is a connection diagram showing a configuration of an output port according to the first embodiment.
In the figure, 1 is a 5V power supply terminal, 2 'and 3' are Pch transistors, 4 and 5 are Nch transistors, 6 is an inverter, 7 is an event switching signal, 14 is a low-speed event input, 15 is a high-speed event input, and 16 is 3v. Power terminal,
17, 18, 19 and 20 are Pch transistors, 21 is a GND terminal, and 22 is a level shifter circuit.

In FIG. 1, input of a low-speed event 14 such as a long-period signal 14 ′ such as a port output and a high-speed event 15 such as a short-period signal 15 ′ such as an address output are performed by an event switching signal 7. The signal 13 connected according to is input.

An Nch transistor 5, an inverter 6 operating at a power supply voltage of 3V, an Nch transistor 4 to which an output signal from the inverter is input, two Pch transistors 2 ', 3' operating at a power supply voltage of 5V, and parallel to each other. , Two Pch transistors 17, 18 and 19, 20 are connected in series. The Pch transistors 17 and 19 on the power supply side, which are connected in series, are linked to the event switching signal 7, and the signal whose connection is switched to the power supply 3V: 16 during a low-speed event and to the GND: 21 during a high-speed event. Are automatically input to the level shifter circuit 22.

In the conventional level shifter circuit, in order to cope with a high-speed event, the size of the large Pch transistors 2 and 3 is reduced by replacing them in parallel (Pch transistors 2 'and 3').

Next, the operation will be described. For example, when the low-speed event 14 is selected by the event switching signal 7, the switching signal 7 is automatically connected to a 3V power supply in conjunction with the event. Therefore, a power supply voltage of 3 V is input to the two Pch transistors 17 and 19 on the power supply side, so that the driving capability is reduced and the current consumed by the level shifter circuit can be reduced. Conversely, when the high-speed event 15 is selected, the two Pch transistors 1 on the power supply side
The GND level is automatically input to the gates 7 and 19, and the two Pch transistors 17 and 19 on the power supply side are turned on, so that high-speed operation can be supported as in the conventional case.

In response to an event input whose required operation speed is fixed as described above, the current consumed by the level shifter unit is changed in conjunction with each event, so that the current consumption during a low-speed event can be reduced. .

According to the first embodiment of the present invention, in the output port having the level shifter unit including the level shifter circuit 22 and the switching control unit according to the input,
The level shifter circuit 2 according to the input type based on the operation speed
Pc for selectively changing the driving capability of the level shifter circuit 22 by controlling an operation element formed by an operation transistor including Pch transistors 2 ′ and 3 ′ constituting the Pch transistor 2.
The level shifter circuit 22 includes a first Nch transistor 5 to which an input signal is input to a gate, and a control circuit including a control transistor composed of h transistors 17 and 18 and 19 and 20. A second Nch transistor 4 whose signal is input to the gate via an inverter, and first and second Pch transistors 3 ′ and 2 ′ operated by first and second Nch transistors 5 and 4. In this configuration, the third and fourth Pch transistors 19 and 20 connected in series with each other are connected in parallel with the first Pch transistor 3 ′, and the fifth and sixth Pch transistors connected in series with each other are connected.
The first and second Pch transistors 17 and 18 are connected in parallel with the second Pch transistor 2 ′, and the gate inputs to the third and fifth Pch transistors 19 and 17 are controlled in accordance with the type of input, whereby the first and second Pch transistors 17 and 18 are connected. Of the Pch transistors 3 'and 2' are controlled by the level shifter unit in accordance with a situation required by an input type depending on an operation speed such as a high-speed event input or a low-speed event input. Change the current that is
An output port capable of reducing the current consumption can be obtained.

Embodiment 2 Embodiment 2 of the present invention will be described with reference to FIG. FIG. 2 is a connection diagram showing a configuration of an output port according to the second embodiment. In the figure, 1 is a 5V power supply terminal, 2 ′ and 3 ′ are Pch transistors, 4 and 5 are Nch transistors, 6 is an inverter, 7
Is an event switching signal, 14 is a low-speed event input, 1
5 is a high-speed event input, 16 is a 3V power supply terminal, and 17 and 1
8, 19 and 20 are Pch transistors, 21 is a GND terminal, 22 is a level shifter circuit, 23 is an input register switching signal, 24 is an event [1] input terminal, and 25 is an event [2] input terminal.

In FIG. 2, a signal 13 connected according to an input from an event [1] input terminal 24 and an event [2] input terminal 25 is input by an event switching signal 7. An Nch transistor 5 and an inverter 6 operating at a power supply voltage of 3 V; an Nch transistor 4 to which an output signal from the inverter is input; two Pch transistors 2 ′ and 3 ′ operating at a power supply voltage of 5 V; Pch transistors 17, 18 and 1
9, 20 are connected in series. The Pch transistors 17 and 19 on the power supply side, which are connected in series,
As required by the input level switching signal 23, the power supply is set to 3V: 16 during a low-speed event, and to GND:
21 can be switched. In addition, in order to respond to high-speed events in the conventional level shifter circuit,
The size of the large Pch transistors 2 and 3 is reduced by replacing them in parallel (P-type transistors 2 ′,
3 ').

Next, the operation will be described. For example, when the event 1 (24) is selected by the switching signal 7, even if the event is a signal level having a short cycle, if the output does not require a short cycle, the input level switching signal 23 is set to 3V as necessary. Can be connected to the power supply. In that case, two Pch transistors 1 on the power supply side
Since the power supply voltage of 3 V is input to the switches 7 and 19, the driving capability is reduced, and the current consumed by the level shifter circuit can be reduced even when an event having a signal level with a short cycle is output. Conversely, event [1] input terminal 2
4 requires a high-speed signal level change as an output, the input level switching signal 23 is set to GND:
21 and two Pch transistors 1 on the power supply side.
If the GND levels are set to be input to the gates 7 and 19, the Pch transistors 17 and 19 on the two power supply sides are
The state becomes N, and high-speed operation can be handled as in the conventional case. The same can be said for the event [2] input terminal: 25 is selected.

As described above, the current consumption in the level shifter can be changed by freely switching the input level of the control Pch transistor arbitrarily according to the operation state required by the event input individually. And control according to the state required by the system can be performed.

According to the second embodiment of the present invention, in the output port having the level shifter unit including the level shifter circuit 22 and the switching control unit according to the input,
A Pch transistor that selectively changes the driving capability of the level shifter circuit 22 by controlling an operating element formed by an operating transistor including Pch transistors 2 ′ and 3 ′ forming the level shifter circuit 22 in accordance with an operation state generated by an input application. The level shifter circuit 22 includes a first Nch transistor 5 whose input signal is input to a gate, and an inverter whose input signal is an inverter. Nch transistor 4 input to the gate through
And first and second Pch transistors 3 ′, 3 ′ activated by the first and second Nch transistors 5, 4.
2 ', the third and fourth Pch transistors 19 and 20 connected in series with each other are connected in parallel with the first Pch transistor 3', and the fifth and sixth Pch transistors 19 and 20 connected in series with each other are connected. Pch transistors 17 and 18 are connected in parallel with the second Pch transistor 2 ′, and the third and fifth Pch transistors 1
By controlling the gate inputs to the gates 9 and 17 in accordance with the operation state by the application of the input signal, the first and second P
Since the channel transistors 3 'and 2' are controlled, the event [1] input terminal 24 or the event [2]
It is possible to obtain an output port capable of changing the current consumed by the level shifter unit according to a situation required by an operation state caused by application of an input from an input terminal and reducing the consumed current.

[0024]

According to the first aspect of the present invention, in an output port having a level shifter section composed of a level shifter circuit and a switching control section corresponding to an input, an operation element forming the level shifter circuit is controlled to control the level shifter circuit. Since the control means for selectively changing the driving capability is provided, the current consumed by the level shifter unit can be changed according to the required situation, and an output port capable of reducing the consumed current can be obtained.

According to the second invention, in the output port having the level shifter section composed of the level shifter circuit and the switching control section corresponding to the input, the operation element constituting the level shifter circuit is controlled in accordance with the type of the input and the level shifter is controlled. Since control means for selectively changing the driving capability of the circuit is provided, depending on the situation required by the input type,
The current consumed by the level shifter can be changed, and an output port capable of reducing the consumed current can be obtained.

According to the third aspect of the present invention, in an output port having a level shifter section including a level shifter circuit and a switching control section corresponding to an input, an operation element constituting the level shifter circuit is controlled in accordance with an input type based on an operation speed. Control means for selectively changing the drive capability of the level shifter circuit, so that the current consumed by the level shifter unit can be changed according to the situation required by the input type based on the operation speed, and the current consumption Can be obtained.

According to the fourth aspect of the present invention, the level shifter circuit includes a first Nch transistor whose input signal is input to a gate, a second Nch transistor whose input signal is input to a gate via an inverter, In the first and second Pch transistors operated by the first and second Nch transistors, third and fourth Pch transistors connected in series with each other are connected in parallel with the first Pch transistor. And connecting the fifth and sixth Pch transistors connected in series with each other in parallel with the second Pch transistor, and controlling the gate input to the third and fifth Pch transistors according to the input type. In this case, the first and second Pch transistors are controlled. By controlling the first and second Pch transistors with the third and fifth Pch transistors whose inputs are controlled according to the input type, the current consumed by the level shifter unit can be reduced according to the required situation. It is possible to obtain an output port which can be changed and whose current consumption can be reduced.

According to the fifth aspect of the present invention, in an output port having a level shifter section composed of a level shifter circuit and a switching control section according to an input, an operating element constituting the level shifter circuit according to an operation state caused by input application is provided. Since control means for controlling and selectively changing the driving capability of the level shifter circuit is provided, it is possible to change the current consumed by the level shifter section according to the situation required by the operation state caused by the input application. An output port capable of reducing current consumption can be obtained.

According to the sixth aspect of the present invention, the level shifter circuit includes a first N-channel transistor whose input signal is input to a gate, a second N-channel transistor whose input signal is input to a gate via an inverter, In the first and second Pch transistors operated by the first and second Nch transistors, third and fourth Pch transistors connected in series with each other are connected in parallel with the first Pch transistor. And connecting the fifth and sixth Pch transistors connected in series with each other in parallel with the second Pch transistor, and applying a gate input to the third and fifth Pch transistors by applying the input signal. The first and second Pc are controlled according to the operation state.
Since the h transistor is controlled, the gate input is controlled by controlling the first and second Pch transistors with the third and fifth Pch transistors whose gate inputs are controlled according to the operation state by the application of the input signal. It is possible to obtain an output port capable of changing the current consumed by the level shifter unit according to the situation, and reducing the consumed current.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing a configuration of an output port according to a first embodiment of the present invention.

FIG. 2 is a connection diagram showing a configuration of an output port according to a second embodiment of the present invention.

FIG. 3 is a connection diagram showing a configuration of a conventional level shifter circuit and an output port capable of outputting a plurality of events.

[Explanation of symbols]

1 Power supply voltage 5V, 2, 2 ', 3, 3' Pch transistor, 4, 5Nch transistor, 6 inverter, 7 event switching signal, 8 conventional level shifter circuit, 9 port output, 10 address output, 11
Inverter, 12 output terminals, 13 event switched signal, 14 low-speed event input terminal, 15 high-speed event input terminal, 163 V power supply terminal, 17-20 Pc
h transistor, 21 GND terminal, 22 level shifter circuit, 23 input level switching signal, 24 event [1] input terminal, 25 event [2] input terminal.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Sachiko Kawaguchi 3-1-1, Chuo, Itami-shi, Hyogo Mitsubishi Electric System LSI Design Co., Ltd. F-term (reference) 5J056 AA04 AA11 BB17 CC21 DD12 DD28 EE07

Claims (6)

[Claims] 1. An output port having a level shifter section comprising a level shifter circuit and a switching control section corresponding to an input, wherein an operation element constituting the level shifter circuit is controlled to selectively change a driving capability of the level shifter circuit. An output port provided with control means. 2. An output port having a level shifter unit including a level shifter circuit and a switching control unit according to an input, controls an operation element included in the level shifter circuit according to an input type to select a driving capability of the level shifter circuit. An output port provided with control means for changing the output time. 3. An output port having a level shifter section comprising a level shifter circuit, and a switching control section corresponding to an input, controlling an operation element constituting the level shifter circuit in accordance with an input type according to an operation speed to drive the level shifter circuit. An output port provided with control means for selectively changing the ability. 4. A level shifter circuit comprising: a first Nch transistor whose input signal is input to a gate; a second Nch transistor whose input signal is input to a gate via an inverter; and the first and second Nch transistors. The first and second Pch transistors operated by Nch transistors, wherein the third and fourth Pch transistors connected in series to each other are connected to the first Pch transistor.
The fifth P-channel transistor and the fifth P-channel transistor connected in series with each other are connected in parallel with the second P-channel transistor, and the third P-channel transistor is connected in parallel with the second P-channel transistor.
4. The device according to claim 1, wherein the first and second Pch transistors are controlled by controlling a gate input to the fifth and fifth Pch transistors in accordance with an input type. Output port described in. 5. An output port having a level shifter section comprising a level shifter circuit and a switching control section corresponding to an input, controlling an operation element constituting the level shifter circuit in accordance with an operation state caused by application of an input to the level shifter circuit. An output port provided with control means for selectively changing a driving capability. 6. A level shifter circuit comprising: a first Nch transistor whose input signal is input to a gate; a second Nch transistor whose input signal is input to a gate via an inverter; and the first and second Nch transistors. The first and second Pch transistors operated by Nch transistors, wherein the third and fourth Pch transistors connected in series to each other are connected to the first Pch transistor.
The fifth P-channel transistor and the fifth P-channel transistor connected in series with each other are connected in parallel with the second P-channel transistor, and the third P-channel transistor is connected in parallel with the second P-channel transistor.
And controlling the first and second Pch transistors by controlling a gate input to a fifth Pch transistor according to an operation state by applying the input signal. Claim 5
Output port described in.