JP2002009088A - Thin film semiconductor device, method of manufacturing the same, and silicon film - Google Patents

Abstract

(57) Abstract: A method for manufacturing a thin film semiconductor device having good transistor characteristics is provided. SOLUTION: The thickness of a channel is 500 angstroms or less, the gate insulating film is composed of two layers, and the refractive index of the gate insulating film near the channel is larger than the refractive index of the gate insulating film near the electrode. .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film semiconductor device formed on an insulating material, such as a thin film transistor or a three-dimensional LSI device applied to an active matrix liquid crystal display or the like, a method of manufacturing the same, and a silicon film. Yes, the maximum temperature of the manufacturing process is 600
The present invention relates to a method for manufacturing a thin-film semiconductor device formed by a low-temperature process of about not higher than about ° C.

[0002]

2. Description of the Related Art In recent years, with the increase in the screen size and resolution of a liquid crystal display, the driving system has shifted from a simple matrix system to an active matrix system, and it has become possible to display a large amount of information. The active matrix method enables a liquid crystal display having more than hundreds of thousands of pixels, and forms a switching transistor for each pixel. As a substrate for various liquid crystal displays, a transparent insulating substrate such as a fused quartz plate or glass that enables a transmission type display is used.

However, in order to increase the size of the display screen and reduce the cost, it is essential to use inexpensive ordinary glass as the insulating substrate. Accordingly, there has been a demand for a technique capable of forming a thin film transistor for operating an active matrix type liquid crystal display on an inexpensive glass substrate with stable performance while maintaining this economic efficiency.

Amorphous silicon or polycrystalline silicon is usually used for the channel portion semiconductor layer of the thin film transistor. However, when the driving circuit is integrated with the thin film transistor, polycrystalline silicon having a high operation speed is used. It is advantageous.

Conventionally, when such a thin film transistor is formed, after forming a silicon layer in a channel portion, a substrate is formed of oxygen (O ₂ ) and laughing gas (N
_{2 O),} and inserted into an oxidizing atmosphere, including water vapor (H 2 _O), and oxidizing a portion of the channel portion silicon layer the temperature as high as about 1100 ° C. from 800 ° C., to form a gate insulating layer A thermal oxidation method was used. On the other hand, various methods have been attempted to fabricate a thin film semiconductor device using polycrystalline silicon at a process maximum temperature of about 600 ° C. or less, which can withstand the use of an inexpensive ordinary glass substrate. For example, a channel portion semiconductor layer is formed by a low pressure chemical vapor deposition (LP) method.
After the formation by the CVD method, the gate insulating film is formed by the electron cyclotron resonance plasma CVD method (ECR-PECVD method).
And hydrogenation treatment such as hydrogen plasma irradiation. Alternatively, an amorphous silicon thin film is deposited on the semiconductor layer of the channel portion, and then a heat treatment is performed at 600 ° C. for about 24 hours, and then the atmospheric pressure chemical vapor deposition (APC)
VD method) to form a gate insulating film and perform a hydrogenation treatment. (Japanese J, App
1, Phys, 30L 84'91)

[0006]

However, a number of problems have been pointed out in the above-mentioned conventional method. First, in the formation of an SiO ₂ film by a thermal oxidation method, a high-temperature heat treatment of at least 800 ° C. or more is involved in the formation, and thus the heat resistance of the thin film layer and the substrate located below the oxide film becomes a problem. For example, when producing a switching transistor for a large-area liquid crystal display, a substrate other than a very expensive fused silica plate cannot withstand such a high temperature. Further, even in a three-dimensional LSI element, since the lower layer transistor deteriorates at a high temperature, this thermal oxidation method is practically unusable.

Next, a channel portion semiconductor layer is formed by an LPCVD method, a gate insulating film is formed by an ECR-PECVD method, and a method of performing a hydrogen plasma treatment has a mobility of 4 to 5 cm ² / V. sec, which is still insufficient as a thin film semiconductor device. In addition, due to the hydrogenation process performed to improve the characteristics of the thin-film semiconductor device, a part of various thin films constituting the thin-film semiconductor device is etched, and some of the many thin-film semiconductor devices are destroyed. There is a problem that said. Further, a method of depositing an amorphous silicon thin film on a channel portion semiconductor layer, thereafter performing a heat treatment at about 600 ° C., forming a gate insulating film by an APCVD method, and further performing a hydrogenation treatment such as hydrogen plasma irradiation. Is still insufficient as a thin film semiconductor device, for example, has a large interface trap level of about 10 ¹² and exhibits depletion type semiconductor device characteristics. In addition, the problems associated with the Yabari hydrogenation treatment remain as before, and a thin-film semiconductor device cannot be uniformly and stably formed over a large area.

Therefore, there is a demand for a thin-film semiconductor device having a high mobility, a clean MOS interface, a low interface trap level, and no depletion. In addition, such a thin-film semiconductor device is manufactured. There has been a demand for a manufacturing method that does not require a hydrogenation process in the process and that uniformly and stably forms a good thin-film semiconductor device as described above over a large area.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a MIS type thin film semiconductor device which has good semiconductor device characteristics in a low temperature process in which the process maximum temperature is about 600 ° C. or less. And a method for uniformly and stably manufacturing such a thin film semiconductor device over a large area.

[0010]

The object of the present invention is to form a channel silicon film semiconductor layer on one surface of a substrate having at least a surface made of an insulating material, and to form a gate insulating layer and a gate electrode on the semiconductor layer. In the thin film semiconductor device forming the MIS type field effect transistor, a step of depositing a silicon film forming a channel portion silicon film semiconductor layer and then performing a heat treatment at a temperature of 600 ° C. or less, and forming the gate insulating film by ECR-PECVD A manufacturing method including a step of forming by a method, or irradiating oxygen plasma on the amorphous silicon film before forming a gate insulating layer after depositing an amorphous silicon film constituting a channel portion silicon film semiconductor layer. Then, it is achieved by a manufacturing method including a step of performing a heat treatment at a temperature of 600 ° C. or less.

[0011]

(Embodiment 1) Embodiments of the present invention will be described below in detail with reference to the drawings, but the present invention is not limited to the following embodiments.

FIGS. 1A to 1E are sectional views showing the steps of manufacturing a silicon thin-film semiconductor device constituting a MIS field-effect transistor having a self-mismatched staggered structure in the first embodiment. .

In the first embodiment, 2
Although 35 mm square fused quartz glass was used, the type and size of the substrate or base material are not limited as long as the substrate or base material can withstand the maximum process temperature of 600 ° C. For example, usually, in addition to a glass substrate, a semiconductor substrate such as a silicon wafer and an LSI processed therefrom, a three-dimensional LSI, or a silicon substrate.
Ceramic substrates such as carbide, alumina, and aluminum nitride can be used as the base substrate.

First, the base substrate 101 is immersed in an organic solvent such as acetone or methyl ethyl ketone, methyl isobutyl ketone or cyclohexanone, and subjected to ultrasonic cleaning. After the washing, drying is performed in nitrogen or under reduced pressure, ultrasonic cleaning with ethanol is performed, and then water washing is performed with pure water bubbled with nitrogen. Next, the base substrate 101 was immersed in boiling nitric acid at a concentration of 60% for 5 minutes, and further washed in pure water with nitrogen bubbling. When a substance such as a metal that is corroded by an acid or deteriorated by an acid is used as the substrate, the cleaning with nitric acid is not required. Further, in the washing with the strong acid, sulfuric acid and the like can be used as the acid in addition to nitric acid.

On the cleaned quartz substrate, a silicon dioxide film (SiO ₂ film) 102 serving as an underlayer protective film was deposited by 2,000 Å by atmospheric pressure chemical vapor deposition (APCVD). When the above-described various materials are used as the substrate, the base SiO ₂ film 102 is necessary for stabilizing the film quality of a silicon thin film to be deposited later and the performance of a thin film transistor formed using the same. At the same time, for example, when normal glass is used as the substrate 101,
Prevents mobile ions such as sodium contained in the glass from diffusing into the transistor part when sintering aid raw materials and the like added to the substrate when various ceramic plates are used as the substrate 101. Also plays a role. When a metal plate is used as the substrate 101, the underlying SiO ₂ is indispensable to ensure insulation. In a three-dimensional LSI element, it corresponds to an interlayer insulating film between transistors and between wirings. The substrate temperature at the time of depositing the underlayer SiO ₂ film 102 was 300 ° C., and silane 600 SCCM diluted to 20% with nitrogen was deposited by the APCVD method together with 840 SCCM oxygen. At this time, the deposition rate of the SiO ₂ film was 3.9 angstroms / sec.

Subsequently, a silicon thin film 103 containing an impurity serving as a donor or an acceptor was deposited by a low pressure CVD method. In the first embodiment, phosphorus was selected as an impurity for the purpose of forming an n-type transistor.
Group 6 element, group 2 including boron for P type,
Group 3 elements can be added as impurity elements. The silicon thin film 103 containing the impurity is a portion to be a source / drain region, and the impurity is deposited by CVD as in the first embodiment.
In addition to the method of adding by the method, first, an intrinsic silicon film containing no impurities is formed first, and then the impurity is diffused from a gas phase or a solid phase in contact with the intrinsic silicon film, or the impurity is ionized. And implanting it into an intrinsic silicon film. If a method of adding an impurity by a diffusion method or an ion implantation method after forming the intrinsic silicon film is used, it is possible to add an impurity only to a desired portion of the intrinsic silicon film. And a self-aligned transistor whose source end or drain end is self-aligned,
By changing the impurity concentration at each part, it is possible to change the current density and the specific resistance in the silicon film and to flow a current only to a desired part.

In Example 1, since phosphorus was selected as an impurity, a silicon thin film 103 containing an impurity was deposited at 1500 angstrom using a gas obtained by mixing phosphine (PH ₃ ) and silane.

In the first embodiment, 200 SCCM of monosilane, 6 SCCM of a mixed gas of helium and phosphine containing 99.5% of helium and 0.5% of phosphine, and 6 SCCM of 100 SCCM of helium are placed in a reduced pressure CVD furnace having a volume of 184.5 l. The solution was flowed and deposited at a deposition temperature of 600 ° C. and a furnace pressure of 100 mtorr. The deposition rate at this time is 29.6 Å / m.
In, the sheet resistance immediately after the film formation was 2,025 Ω / □.

Next, a resist was formed on the silicon thin film, and the thin film was patterned by a mixed plasma of carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) to form source / drain regions 103. (FIG. 1 (a)). Subsequently, impurities such as residual resist were removed by washing by immersing in boiling nitric acid for 5 minutes, and a natural oxide film on the surface of the source / drain region 103 was removed by immersion in 1.67% hydrofluoric acid for 20 seconds.
Immediately, a silicon thin film serving as a channel portion was deposited by a low pressure CVD method.

At this time, the volume of the reduced pressure CVD reactor is 184.
At 51, the substrate is placed horizontally near the center of the reactor. The raw material gas and a diluent gas such as helium, nitrogen, argon, and hydrogen are introduced into the furnace from the lower part of the reactor as required, and are exhausted from the upper part of the reactor. Outside the reactor made of quartz glass, a heater divided into three zones is installed,
By adjusting them independently, a soaking zone is formed near the center of the reactor at a desired temperature. This tropical zone extends at a height of about 350 mm, and the temperature deviation within that range is, for example, 6 mm.
It is within 0.2 ° C when set to 00 ° C. Therefore, if the interval between the inserted substrates is 10 mm, it is possible to process 35 substrates in one batch. In the first embodiment, 17 substrates were placed at an interval of 20 mm in the soaking zone.

The exhaust was performed by directly connecting a rotary pump and a mechanical booster pump, and the pressure in the reactor was measured by a diaphragm type pressure gauge (MKS Baratron Manometer) whose measured value does not depend on the type of gas. 5 reactors
When the temperature was kept at 50 ° C., the gas introduction valve was closed, and both the pumps were evacuated, the internal pressure of the reactor was 0 mtorr.
Therefore, the background vacuum degree is at most about 10 ^-4 torr or less.

A source / drain region 103 is formed,
The substrate from which the native oxide film on the surface of the region was removed was immediately inserted into a low pressure CVD furnace with its front side facing down. The temperature in the reactor at the time of insertion is maintained at about 395 ° C. to 400 ° C. This is to minimize the formation of a natural oxide film on the source / drain region 103.
It is desirable that the temperature in the reactor at the time of insertion be as low as possible. For example, it is possible to set the temperature in the reactor at the time of insertion to room temperature, but in this case, spend several hours or more to raise the temperature in the reactor to the deposition temperature, and It takes time. Approximately 4SL in the reactor when inserting the substrate
Nitrogen of M to 10 SLM is flown to keep the inside of the reaction furnace in an inert atmosphere. Furthermore, about 6 SLM ~
A nitrogen curtain is formed with 20 SLM of nitrogen to minimize the flow of air into the reactor during substrate insertion.
When moisture or oxygen in the air enters the reaction furnace, they are adsorbed on the Si layer on the inner wall of the reaction furnace or react with Si and remain in the reaction furnace to be removed during the deposition of a silicon film serving as a channel. It appears as a gas and causes the film quality of the deposited silicon film to deteriorate.

After inserting the substrate, vacuum evacuation and leakage inspection were performed. In the leak inspection, all valves connected to the reactor were closed to isolate the reactor completely, and the change in reactor pressure was examined.
In Example 1, the pressure in the reactor was 1 mtorr or less after the reactor temperature was completely isolated at 400 ° C. for 2 minutes. After confirming that there is no abnormality in the leak inspection, the temperature in the reactor is increased from the insertion temperature of 400 ° C. to the deposition temperature. In Example 1, since a silicon thin film serving as a channel portion was deposited at 550 ° C., it took one hour to raise the temperature. It takes only about 35 minutes for the furnace temperature to reach the deposition temperature of 550 ° C., but in order to sufficiently release degassed gas from the reactor wall, a heating period of at least one hour or more, preferably several hours, is desirable. .
During this heating period, the two pumps are in operation and continue to flow at least an inert or reducing gas having a purity of at least 99.995%. These gas species include pure gases such as hydrogen, helium, nitrogen, neon, argon, xenon, and krypton, as well as mixed gases of these gases. In the first embodiment, helium having a purity of 99.9999% or more is
Keep the SCCM flowing and the reactor pressure is 80.7 ± 1.2mtorr
It was.

After the deposition temperature is reached, a predetermined amount of silane as a source gas or a mixed gas of silane and a diluent gas is introduced into the reaction furnace, and a silicon thin film 104 is deposited. As the diluting gas, the same kind of combination as the gas flowing in the previous temperature raising period is possible, but preferably, each gas has a purity of 9%.
9.999% or more is good. In Example 1, a silicon thin film 104 was deposited by flowing 100 SCCM of silane having a purity of 99.999% or more without using a diluent gas. At this time, the pressure inside the reactor is adjusted by opening and closing the conductance valve installed between the reactor and the mechanical booster pump.
It was kept at 398.6 ± 1.9 mtorr. In the first embodiment, the silicon thin film 104 serving as a channel portion was deposited at a deposition rate of 21.2 angstroms / min to a film thickness of 248 angstroms (FIG. 1B).

In the first embodiment, the silicon thin film is deposited by LP
The deposition is performed by the CVD method, and monosilane is used as a raw material gas. However, it is also possible to deposit by a plasma CVD method, an APCVD method, a sputtering method, or the like. The source gas is not limited to monosilane, but may be higher silane such as disilane or trisilane, or dichlorosilane. Of course, it is also possible to deposit a silicon thin film by a combination of the above various CVD methods and the above various raw materials.

Next, the substrate thus obtained was subjected to a heat treatment to promote crystallization of the silicon thin film 104 and increase crystal grains. The heat treatment furnace is a vertical furnace which is usually maintained at 400 ° C., and is supplied with nitrogen gas having a purity of 99.999% or more for 20 SL.
By continuously flowing M, the inside of the heat treatment furnace is maintained in an inert atmosphere. The substrate which reached the temperature equilibrium with the room temperature was inserted into a vertical heat treatment furnace at 400 ° C. over 17 minutes. After the insertion, keep at 400 ° C for 30 minutes.
After reaching a uniform temperature of ℃, the temperature of the heat treatment furnace is raised to 600 ℃. By keeping the substrate at 400 ° C. for 30 minutes, the same heat history can be obtained everywhere regardless of the position of the substrate, and the silicon thin film can be uniformly crystallized. Since 20 SLM of nitrogen continuously flows through the heat treatment furnace and the volume of the heat treatment furnace is about 176 l, this 40
By preheating at 0 ° C., the inside of the heat treatment furnace is completely replaced with a nitrogen atmosphere. The temperature rise from 400 ° C. to 600 ° C. is performed in about 1 hour, and after reaching a temperature equilibrium at 600 ° C., the crystallization of the silicon thin film proceeds by a heat treatment of 7 hours or more. In the first embodiment, after the temperature reaches 600 ° C., 23
Time heat treatment was applied.

After the silicon thin film thus obtained was patterned with a resist, it was etched by a mixed plasma of carbon tetrafluoride (CF ₄ ) and oxygen (O ₂ ) to form a channel silicon thin film 105. (Figure 1
(C)) The silicon thin film formed in Example 1 is a vacuum plasma discharge of 15 Pa having a ratio of CF ₄ and O ₂ of 50 SCCM to 100 SCCM and an output of 700 W is 2.1 Å / sec in etching when the output is 700 W. Had an etching rate.

Next, the substrate is washed with boiling nitric acid having a concentration of 60%, and further washed with a 1.67% aqueous hydrofluoric acid solution.
Immediately after immersion for 0 second to remove the native oxide film on the source / drain region 103 and the channel silicon thin film 105 and a clean silicon surface appears, an electron cyclotron resonance plasma CVD device (ECR-PECVD device)
Deposited an SiO ₂ film 106 to be a gate insulating film.
(FIG. 1D) ECR-PECVD used in Example 1
An outline of the apparatus is shown in FIG. At the time of depositing the gate insulating film, a microwave of 2.45 GHZ is guided to the reaction chamber 202 through the waveguide 201, and oxygen of 100 SCCM introduced from the gas introduction pipe 203 is first turned into plasma. At this time,
The output of the microwave is 2250 W, and the reaction chamber 202 is driven by an external coil 204 installed outside the reaction chamber 202.
A magnetic field of 875 Gauss is applied to the oxygen plasma inside to satisfy the ECR condition for the electrons in the plasma. The oxygen plasma is drawn out of the reaction chamber by the divergent magnetic field, and the substrate 205 placed perpendicular to the plasma is moved to the reaction chamber 1 by one.
Irradiate for 0 seconds. A heater 206 is provided on the back of the substrate 205.
And the whole substrate was kept at 100 ° C. At this time, the pressure in the reaction chamber was 1.85 mtorr. Immediately after the oxygen plasma outlet, another gas introduction tube 207 is provided. After the oxygen plasma is sufficiently stabilized for 10 seconds, silane 60 SCCM having a purity of 99.999% or more is supplied from the gas introduction tube 207 to the oxygen plasma. Mix in. The substrate thus obtained was irradiated with the oxygen-silane mixed plasma thus obtained for 30 seconds to form an SiO ₂ film 106 serving as a gate insulating layer on the substrate for 150 seconds.
0 Å was deposited (FIG. 1D). At this time, the pressure in the reaction chamber was 2.35 mtorr.

Next, chromium was deposited to a thickness of 1500 angstroms by sputtering, and a gate electrode 107 was formed by patterning. At this time, the sheet resistance value is 1.356 ±
0.047Ω / □. Although chromium was used as the gate electrode material in the first embodiment, it is needless to say that other conductive substances can be used, and the formation method is not limited to the sputtering method, but may be a vapor deposition method or a CVD method. Then APC
The SiO ₂ film which becomes the interlayer insulating film 108 by the VD method is 5000
Angstrom deposited. This deposition was performed under exactly the same conditions as those for depositing the underlying SiO ₂ film 102 in the first embodiment, and only the deposition time was changed. After forming the interlayer insulating film, a contact hole is opened and the source / drain extraction electrode 10 is formed.
9 is formed by a sputtering method or the like, and the transistor is completed (FIG. 1E). In Example 1, a source / drain extraction electrode was formed by depositing a film having a thickness of 8000 Å by sputtering using aluminum as a source / drain extraction electrode material. At this time, the sheet resistance of the deposited aluminum film was 42.48 ± 2.02 mΩ / □.
It was.

An example of the characteristics of the thin film transistor (TFT) thus fabricated is shown in FIG.
-A. Here, the source-drain current Ids was measured at a source-drain voltage Vds = 4 V and a temperature of 25 ° C. Transistor size is channel length L = 1
0 μm and width W = 10 μm. Vds = 4V, Vg
When the transistor is turned on at s = 10 V, the on-current is measured at the center of a 235 mm square substrate and five square transistors, and ION = 4.65 ± 0.39 μA. The device was obtained.
Further, the field-effect movement μo obtained from the saturation current region of the transistor and the trapping density Nt (J. Levinson et.
al. J. Appl. Phys 53 . 1193.1
982) is μo = 25.85 ± 0.96 cm ² /
v. sec, Nt = (6.81 ± 0.15) × 10 ¹¹ 1
/ Cm ² . For comparison, FIG. 3B illustrates transistor characteristics of a thin film semiconductor device manufactured according to an example of the prior art. That is, a thin film semiconductor device was produced in the same process as that of the present invention in Example 1 except that a channel silicon thin film was deposited at 600 ° C. by a low pressure CVD method and was not subjected to a heat treatment for 24 hours. . At this time, low pressure CVD
The apparatus for depositing the channel silicon thin film by the method is the same as the apparatus used in the present invention of Example 1, the monosilane as the raw material gas flows at 12.5 SCCM, and the pressure in the reactor is 9.0 m.
torr, deposition rate 11.75 Å / m
in deposited to a thickness of 256 Å. The on-state current of an example of this conventional TFT is Ids = 0.91.
At 0.12 μA, the field effect mobility is μo = 4.75 ±
0.20 cm ² / v. sec, capture density Nt = (5.18
± 0.13) × 10 ¹¹ 1 / cm ² . In addition, a channel silicon thin film is similarly formed by a low pressure CVD method.
After depositing at 0 ° C. monosilane flow rate of 12.5 SCCM and depositing a gate insulating film in the same process as the present invention of the first embodiment,
Hydrogen plasma treatment with ECR-PECVD equipment,
Otherwise, a thin-film semiconductor device was manufactured in the same process as the present invention of the first embodiment. This is also an example of the prior art for performing the hydrotreating. The hydrogenation treatment was performed using the ECR-PECV shown in FIG.
After depositing the gate insulating film with the D apparatus, vacuum evacuation is performed, and the temperature of the substrate 205 is set to 300 ° C. by the heater 206 to 1 ° C.
The test was performed after the temperature was increased over time. 99.9999% purity
The above hydrogen gas 125 SCCM was led into the reaction chamber 202 from the gas introduction pipe 203 to generate hydrogen plasma. The microwave power is 2000 W and the pressure in the reaction chamber is 2.63 mtorr.
r. The hydrogen plasma irradiation was performed for 30 minutes. When the TFT characteristics of the thin film semiconductor device thus prepared were measured, the on-current Ids = 0.96 ± 0.13 μA and the field-effect mobility μo = 4.68 ± 0.22 cm ² / v. sec,
Capture density Nt = (5.12 ± 0.13) × 10 ¹¹ 1 / cm
^{It was 2} . That is, as compared with the conventional technique in which the channel portion silicon film is deposited at 600 ° C. by the low pressure CVD method regardless of the presence or absence of the hydrogen plasma processing, the transistor characteristic of the present invention is that the field effect mobility is increased to about 5 times, for example. Bring significant improvement.

Next, another example of the prior art will be compared with the present invention. That is, as another example of the prior art, the channel portion silicon thin film is formed in the same manner as the present invention of the first embodiment, but the gate insulating film is deposited by the APCVD method and the gate insulating film is deposited by the APCVD method. Later, we see the great advantage of the present invention over the prior art of performing hydrogen plasma processing. APCV is a gate insulating film that is a conventional technology.
In the step of forming a thin film semiconductor device by depositing by the method D, a thin film semiconductor device was formed by the same steps as the present invention of Example 1 except that the gate insulating film was deposited at 1500 Å by the APCVD method. In the APCVD method, the substrate temperature is kept at 300 ° C., and nitrogen containing 20% silane in nitrogen,
Silane mixed gas is flowed at 300 SCCM and oxygen at 420 SCCM,
Approximately 140 SLM of nitrogen for dilution was flowed with these source gases to deposit a SiO ₂ film. The deposition rate was 1.85 Å / sec. The transistor characteristics of the thin film semiconductor device according to the prior art thus prepared are shown in FIG. The ON current of this transistor is I
ON = 1.49 ± 0.05 μA, field effect mobility μo = 2
4.60 ± 0.72 cm ² / v · sec, capture density Nt =
(9.20 ± 0.15) × 10 ¹¹ 1 / cm ² . Comparing this prior art with the present invention, it is clear that the present invention has significantly reduced the trap level and produced an extremely excellent thin-film semiconductor device which rises rapidly near the gate voltage Ov. In the prior art in which the gate insulating film is deposited by the APCVD method, the mobility length can be increased to the same level as that of the present invention, but in fact, the minimum value of the source / drain current is around -11v and the trapping density is high. Is gentle and not practical as a thin film semiconductor device. On the other hand, another example of the related art is shown in FIG. Here, the channel portion silicon thin film is formed in the same manner as in the present invention of the first embodiment, but the gate insulating film is deposited by the APCVD method and then subjected to a hydrogen plasma treatment. A gate insulating film is deposited under the same conditions as described above, and immediately thereafter,
A thin-film semiconductor device was manufactured through the same steps as the present invention of Example 1 except that hydrogen plasma irradiation was performed under the same conditions as described above using an R-PECVD apparatus. T thus obtained
The characteristics of the FT are shown in FIG. ON current is Ids
= 2.91 ± 0.30 μA, field effect mobility μo = 2
4.51 ± 0.67 cm ² / v · sec, capture density Nt =
(7.94 ± 0.15) × 10 ¹¹ 1 / cm ² . It can be seen that the present invention shows good characteristics in all parameters even in comparison with the prior art using this plasma treatment. Also, in the transistor manufactured by the prior art that has been subjected to the hydrogen plasma treatment, one of the five measured transistors has a threshold voltage Vth shifted by about +2 V, and the average value and the standard deviation value of each of the above-described parameters are different from each other. Does not include the value of. That is, although the transistor characteristics are improved in the conventional technology using the hydrogen plasma process as compared with the conventional technology not performing the hydrogen plasma process, it is difficult to form a uniform transistor uniformly over a large area.
In addition, the sample subjected to the hydrogen plasma treatment has a large fluctuation between lots, and it is difficult to stably produce the sample. In particular, the variation of the threshold voltage and the fluctuation of the gate voltage at which the source / drain current is minimized are extremely large between lots. On the other hand, according to the present invention, it can be understood that a hydrogenation treatment which causes variation can be eliminated, and a transistor superior to the conventional one can be uniformly formed on a large area.

(Example 2) All steps were the same as those of the present invention of Example 1, except that the deposition time of the silicon thin film (FIG. 1.104) to be the channel portion was changed to change the thickness of the silicon thin film 104 deposited. Accordingly, a thin film semiconductor device was prepared. Example 2
In this case, the silicon thin film 104 is 190 angstrom, 2
80 angstroms, 515 angstroms, 10
00 angstroms, 1100 angstroms, 1
645 angstroms and six different film thicknesses were prepared for each of the thin film semiconductor devices. FIG. 4 shows the ratio of the on-state current to the off-state current of the thin film semiconductor device thus obtained with respect to the thickness of the channel portion silicon film.
As can be seen from the figure, in the thin film semiconductor device in which the thickness of the channel portion silicon film semiconductor layer is 500 angstrom or less, the on / off ratio is sharply improved and good characteristics showing seven digits or more are obtained.

(Embodiment 3) A thin-film semiconductor device (off-set thin-film semiconductor device) having a structure in which at least one of a source region and a drain region does not overlap with a gate electrode via a gate insulating film is implemented. It was prepared by the same manufacturing method as that of the present invention in Example 1. Example 3
In FIG. 5A, a staggered thin film semiconductor device as shown in FIG. 5 (a) was created by performing alignment with high precision. Things are also possible. For example, as shown in FIG. 5B, the source / drain region 503 is formed by implanting impurity ions into an intrinsic silicon thin film using the gate electrode 504 as a mask.
An inverted staggered thin-film semiconductor device in which the gate electrode 505 shown in (c) is on the lower side and the source / drain region 507 is formed using the mask material 506 is also possible.

In the third embodiment, the base substrate has a diameter of 75 mm.
An off-set type thin-film semiconductor device was manufactured by the same manufacturing method as in the present invention of Example 1 except that the fused silica glass was used.
That is, first, the substrate is washed, and the underlying SiO ₂ film is subjected to APCV.
After deposition by the D method or the like, the silicon film doped with phosphorus is
The source / drain region 501 was formed by depositing by PCVD and further patterning. Here, the distance between the source and drain regions, which will be the channel length L later, is 10.
It was 5 μm. Next, in the same manner as in Example 1 of the present invention, a silicon thin film serving as a channel portion was deposited at a deposition rate of 21.2 Å / min to a film thickness of 248 Å. However, in the present invention of Example 1, the substrate was inserted into the reaction furnace with the front side of the substrate facing downward.
In this example, a substrate having a diameter of 75 mm was placed on a dummy quartz plate of 235 mm square with its front side facing upward and inserted into the reaction furnace. Thereafter, heat treatment was performed by the same manufacturing method as that of the present invention in Example 1, a gate insulating layer was deposited, and a gate electrode 502 was further formed. The width of the gate electrode 502 is 10.0 μm, the center of the source-drain distance 10.5 μm and the gate electrode width 10.
High-precision alignment was performed so that the center of 0 μm coincided. As a result, the distance (offset distance) between the gate electrode end position and the source region end in the channel region is 0.25 μm. Thereafter, an interlayer insulating film was deposited by the same manufacturing method as that of the present invention in Example 1, and wiring was performed using aluminum after opening the contact holes, thereby completing a thin film semiconductor device.

An example of the transistor characteristics of the thin-film semiconductor device thus prepared is shown by a Vgs-Ids curve of FIG.
a. FIG. 6A shows the transistor characteristics of the self-unmatched type staggered structure thin film semiconductor device experimentally manufactured in the first embodiment of the present invention. As can be clearly seen from the figure, in the present invention of the third embodiment, it is possible to greatly reduce the leak current generated when the gate voltage is negative. In fact, in the third embodiment of the present invention, when the gate voltage is -2.5 V or less, the source / drain current is suppressed to about 0.1 pA. 6-b of FIG. 6 shows, for comparison, transistor characteristics obtained when an offset type thin film semiconductor device is manufactured according to the conventional technique of the first embodiment. That is, the channel portion silicon thin film is deposited by a low pressure CVD method at 600 ° C., the center of the source-drain distance is 10.5 μm, and the gate electrode width is 10.
This is a transistor characteristic obtained when an offset type thin film semiconductor device is manufactured by aligning the center of 0 μm with high precision alignment. Therefore, 6-b in FIG. 6 can be directly compared with 3-b in FIG. 6 of the transistor characteristics of the conventional self-unmatched staggered structure thin film semiconductor device. Although it is possible to keep the leak current as low as about 0.1 pA or less in the off-set type thin film semiconductor device according to the prior art, when the offset type thin film semiconductor device is manufactured in the prior art, the on-current and the transfer current are reduced. The positive characteristics of the transistor, such as the degree, also deteriorated and ended, which was not practical. For example, the on-state current of an offset type thin film semiconductor device according to the prior art is Ids = 0.
090 ± 0.01 μA, which is lower than the self-mismatched thin film semiconductor device by one digit or more. The mobility at this time is also degraded by about 30% as in the case of μo = 3.33 ± 0.15 cm ² / v · sec. For this reason, the manufacture of the offset type thin film semiconductor device according to the prior art was not worthwhile. On the other hand, the present invention according to the third embodiment corresponds to 6 in FIG.
As shown in -a, the leak current is kept low and the on-current is kept high. According to the third embodiment of the present invention, Ids = 3.71 ± 0.43 μA is obtained as the ON current, which is almost equal to the ON current of the self-mismatched thin film semiconductor device. In the present invention of Example 3, the mobility also showed a good value of μo = 22.00 ± 0.95 cm ² / v · sec.

(Embodiment 4) In Embodiment 3, an offset type thin film semiconductor device was produced by performing high-precision alignment. However, the present invention is, of course, effective other than this. FIG.
In (b), an offset type thin film semiconductor device was prepared by depositing an intrinsic silicon film, patterning the gate electrode, and adding impurity ions. This method will be described in detail.

FIGS. 7A to 7D show the fourth embodiment.
MIS field-effect transformer with offset staggered structure
Structural process of silicon thin-film semiconductor device
It is a diagram shown in cross section. First, as in the first embodiment, the substrate 701 is used.
After being cleaned, SiO 2 is used as the undercoat protective film 702.₂Membrane 2
Deposit about 2,000 angstroms. Then the first
Deposit a recon film over 300 angstroms or more.
By turning, the silicon film 703 that becomes the pad
Form. In this embodiment, the first silicon film is actually used.
LPCVD with channel silicon film deposited in Example 1
Deposition temperature 600 ° C using equipment silane flow rate 12.5SCCM
Deposited at 1250 angstroms, but besides this
Using the same LPCVD equipment at a deposition temperature of about 550 ° C.
Depositing a silicon film also requires disilane as the source gas.
(Si_TwoH₆) Is deposited at a deposition temperature of about 450 ° C.
Also, the silicon film is deposited at about 250 ° C by PECVD.
It is also possible to pile up. Process maximum temperature does not exceed 600 ° C
Any method may be used as long as it is at the film formation temperature.
Absent. Next, a second silicon film 704 is deposited.
The thickness of the second silicon film is about 300 Å
Above, resistance of source / drain region after impurity implantation
The value is the resistance of the channel region when the transistor is activated.
If the resistance is sufficiently low, the first silicon film or
The silicon film 703 serving as a gate is not required. This embodiment
In the fourth embodiment, the second silicon film 704 is used in the present invention of the first embodiment.
It was deposited by the same method as the silicon thin film to be the channel portion.
That is, monosilane is used as a source gas by the LPCVD method, and deposition is performed.
Temperature 550 ° C., silane flow rate 100 SCCM deposition rate 21.2
250 angstrom / min
Deposited to film thickness. However, the second silicon film formation method is
As with the first silicon film, the process maximum temperature exceeds 600 ° C
Any method is possible if the film formation temperature is
You. For example, the second silicon film is also deposited at a deposition temperature of 600.degree.
Run at a flow rate of 12.5 SCCM and a pressure of 9.0 mtorr in the reactor.
It can be stacked, and disilane or trisila
Film formation at lower temperature using higher order silane such as
It is possible. In this way, the second silicon film
704 was formed (FIG. 7B), and patterning was performed.
Thereafter, the gate insulating layer 70 is formed in the same manner as in the first embodiment of the present invention.
5 was formed. That is, SiO is formed by the ECR-PECVD method.₂
The film was deposited at 1500 Å. Gate insulation layer
As a means for forming 705, the second silicon film 704 is often used.
If it is a crystalline silicon film, it must be formed by APCVD.
You can also. Next, a metal film to be a gate electrode is formed.
You. In the fourth embodiment, a high concentration of phosphorus is used as a gate electrode material.
The added silicon film was used. Here, the LPCVD method
Deposition temperature 600 ° C, monosilane 200 SCCM, helium
Helium phosphine with 99.5% and 0.5% phosphine
6 SCCM of helium mixed gas and 100 SCCM of helium
3000 angstrom membrane at a furnace pressure of 100 mtorr
Thick deposited. Sheet resistance immediately after film formation is 744Ω / □
It was. Subsequently, a resist is applied, and the resist
After turning, CF₄And O₂Mixed plasma
Accordingly, the phosphorus-added silicon film was patterned. CF₄
And O₂Incident wave at 200 SCCM and 200 SCCM respectively
Patterning was performed at an output of 700 W. Add phosphorus at this time
Silicon film etching rate is 15.4 angstroms
Etching for 5 minutes and 57 seconds at
A pole 706 was created. The thickness of the phosphorus-added silicon film is 300
Because it was 0 angstroms, this plasma etch
The gate electrode width is more left than that of the resist 707
Each right is narrowed by about 2500 Angstroms
(FIG. 7 (c)). Next, it was used for forming the gate electrode 706.
With the resist 707 left without being stripped, impurity ions
Is added. In the fourth embodiment, n-type is selected by selecting phosphorus as an impurity.
We aimed at thin film semiconductor devices, but of course other elements
It is possible according to. Example 4 has a mass spectrometer
Impurity ions using a non-implanted ion implanter
Was given. 5% concentration diluted in hydrogen as source gas
3 × 10 3 at an accelerating voltage of 110 kV^Fifteen
1 / cm ^TwoInto the concentration. In this way, the first system
Part of the recon film and the second silicon film are source / drain
A region 708 is formed, and the resist used for forming the gate electrode is formed.
707 has a thickness of about 2 μm, and
No ion is added to the second silicon film to be
(FIG. 7C). Also this
In accordance with the method, an offset type thin film semiconductor device is created.
You. Next, the gate electrode forming resist 707 was removed.
Thereafter, the substrate is subjected to a heat treatment at 600 ° C. for 7 hours or more,
Activation of doped ions and channel silicon film
709 promotes crystallization when the crystallinity is insufficient. Book
In Example 4, nitriding was performed in the same manner as in the heat treatment performed in Example 1 of the present invention.
A heat treatment was performed at 600 ° C. for 23 hours in an elementary atmosphere. Continued
And SiO as an interlayer insulating film_Two710 is APCVD method
5000 Angstrom deposition and mass spectrometer
Accelerates hydrogen with an ion implantation device without a storage
5 × 10 at 80 kV^Fifteen1 / cm^Two After driving in,
Open the tact hole, and make wiring 71 with aluminum etc.
1 to complete the offset type thin film semiconductor device.

When the transistor characteristics of the offset-type thin film semiconductor device thus prepared were measured, L = W = 10 μm
m, Vds = 4 V, ON current is 3.4 μA, and minimum value of source / drain current is 0.09 when Vgs = −3.5 V
The off-state current defined by pA and Vgs = −10 V is 0.2
The leakage current when the transistor was turned off was 8 pA, which was low, and a good on current was obtained.

After the source region and the drain region are formed in the offset type thin film semiconductor device as described in the third and fourth embodiments, a heat treatment is applied to increase the on-current and reduce the leak current. Although it can be made, the present invention is by no means limited to only the method of manufacturing the offset type thin film semiconductor device described in the third and fourth embodiments. For example, in Example 4, a resist having a width wider than the gate electrode width is used as a mask for implantation as a method of manufacturing an offset type thin film semiconductor device, but there are various other methods. For example, an offset-type thin-film semiconductor device can be manufactured by using a metal as a gate electrode, oxidizing the surface and side surfaces thereof, narrowing the gate electrode, and then implanting impurity ions. Also, as shown in FIG. 5C, in the inverted staggered structure, the width of the mask
An offset type thin-film semiconductor device can be obtained by extending the width from 5 or more. The present invention is effective for offset type thin film semiconductor devices manufactured by any of these manufacturing methods.

(Embodiment 5) FIGS. 8A to 8F show the MIS
FIG. 2 is a cross-sectional view showing a manufacturing process of a silicon thin film semiconductor device for forming a field effect transistor.

In the fifth embodiment, as the insulating substrate 801, 2
Although quartz glass of 35 mm square was used, the type and size of the substrate or base material are not limited as long as the substrate or base material can withstand a temperature of 600 ° C. For example, a three-dimensional LSI formed on a silicon wafer can be used as a base substrate. First, a quartz glass substrate 801 that has been subjected to organic cleaning and acid cleaning
An underlying SiO ₂ film 802 is formed on the upper surface by atmospheric pressure chemical vapor deposition (A
(PCVD method). The base SiO ₂ film 802 is formed at a substrate temperature of 300 ° C., a silane flow rate of 120 SCCM, and oxygen of 84
Deposited at 0 SCCM, about 140 SLM nitrogen. At this time, the deposition rate was 3.9 angstroms / sec, and the deposition time was 8 minutes and 33 seconds. Next, a silicon thin film 803 containing impurities serving as donors or acceptors was deposited by a low pressure chemical vapor deposition (LPCVD) method (FIG. 8A). In Example 5, phosphorus was selected as an impurity, and phosphine (PH ₃ ) 0.03 SCCM and silane (SiH ₄ ) 200 SC
1500 Å was deposited at a deposition temperature of 600 ° C. using CM as a source gas. At this time, the deposition rate was 30 Å / min, and the sheet resistance immediately after the film formation was 1951.
Ω / □. Next, a resist is formed on the silicon thin film 803, and carbon tetrafluoride (CF ₄ ), oxygen (O ₂ ),
Patterning with a mixed plasma such as nitrogen (N ₂ )
Source / drain regions 804 were formed. Subsequently, immediately after removing the dirt / natural oxide film on the surface of the region 804, an amorphous silicon thin film 805 was deposited by a low pressure CVD method. (FIG. 8 (b)) Decompression CV in Embodiment 5
The D apparatus is 184.5 l, and the reaction chamber is made of quartz glass. A heater divided into three zones is installed outside the reaction chamber, and an isothermal region is formed at a desired temperature near the center of the reaction chamber by independently adjusting the three heaters. The substrate was placed horizontally in this isothermal area and an amorphous silicon thin film 805 was deposited. For the amorphous silicon thin film 805, disilane (Si ₂ H ₆ ) 100 SCCM was used as a source gas, and helium (He) 100 SCCM was used as a diluent gas. Deposition temperature is 4
It was 50 ° C. The evacuation of the low pressure CVD furnace used for depositing the amorphous silicon thin film 805 of Embodiment 5 is performed by directly connecting a mechanical booster pump and a rotary pump. A conductance valve is mounted between the mechanical booster pump and the reactor, and the pressure in the reaction chamber can be adjusted and maintained at a desired value by adjusting the opening / closing amount of the valve. Example 5
During the deposition of the amorphous silicon thin film 805, the pressure in the reaction chamber was maintained at 306 mtorr. The deposition rate is 18.
An amorphous silicon thin film 805 was deposited at a thickness of 307 Å at a rate of 07 Å / min. Next, a resist is formed on the amorphous silicon thin film 805 formed in this manner, and patterned by a mixed plasma of carbon tetrafluoride, oxygen, nitrogen, etc. 806 remained.

Next, the substrate was boiled at a concentration of 60%.
And then immersed in a 1.67% aqueous hydrofluoric acid solution for 20 seconds to remove the natural oxide film on the amorphous silicon thin film 806 remaining on the source / drain region 804 and the channel which will eventually become a channel. Immediately after the appearance of a clean silicon film, oxygen plasma 807 was irradiated with an electron cyclotron resonance plasma CVD apparatus (ECR-PECVD apparatus). (FIG. 8C) The outline of the ECR-PECVD apparatus used in the fifth embodiment is shown in FIG. Oxygen plasma passes microwaves of 2.45 GHz for 20
1 to the reaction chamber 202, and 100 SCCM of oxygen was introduced from the gas introduction tube 203 to establish oxygen plasma. At this time, the pressure in the reaction chamber was 1.84 mtorr, and the microwave output was 2500 W. An external coil 204 is provided outside the reaction chamber, and 875 Ga
A magnetic field of uss is applied to make the electrons in the plasma satisfy the ECR condition. The substrate 205 is placed perpendicular to the plasma, and the temperature of the substrate is kept at 300 ° C. by the heater 206. Under this condition, oxygen plasma 807 was irradiated for 8 minutes and 20 seconds to oxidize the amorphous silicon thin film 806 remaining at a position to be a channel portion, thereby obtaining a SiO ₂ film 808 to be a part of a gate insulating layer. . At this time, an amorphous silicon thin film 809 which will eventually become a channel portion remains below the SiO ₂ film 808 which is a part of the gate insulating layer. (FIG. 8
(D) Further, an SiO ₂ film 810 to be a gate insulating layer was continuously deposited without breaking vacuum. This SiO ₂ film 81
0 means 2250 W microwave power, 60 SCC silane flow rate
M, oxygen flow rate 100 SCCM, substrate temperature 300 ° C, 18.
Deposited for 75 seconds. The pressure in the reaction chamber during deposition was 2.
It was 62 mtorr. The thus formed multilayer film is subjected to multi-wavelength dispersion ellipsometry (multi-wavelength spectroscopic ellipsometry: MOSS-ES4G manufactured by Sopra), and the remaining amorphous silicon film 80 which will eventually become a channel portion is formed.
9, a SiO ₂ film 808 formed by oxidizing an amorphous silicon film, and ECR-PECVD.
When the film thickness of the SiO ₂ film 810 deposited by the method was measured, the amorphous silicon thin film 809 was 205 Å, the SiO ₂ film 808 was 120 Å, and S
The iO ₂ film 810 was 1500 Å.
At this time, the refractive index of the SiO ₂ film at a wavelength of 632.8 nm is 1.42 for the SiO ₂ film 808 and 1.42 for the SiO ₂ film 8.
10 was 1.40.

Next, the substrate thus obtained was inserted into an electric furnace maintained at 600 ° C., and was subjected to a heat treatment for 48 hours.
At this time, a nitrogen gas having a purity of 99.999% or more was continuously supplied to the electric heating furnace at a flow rate of 20 l / min to maintain an inert atmosphere. By the heat treatment at 600 ° C. in the inert atmosphere, the amorphous silicon thin film remaining in the channel portion is crystallized and changed into a silicon thin film 811 constituting the channel portion. (FIG. 8 (e)) Subsequently, this substrate is again subjected to E
The substrate was placed in a CR-PECVD apparatus, and the substrate subjected to the heat treatment was irradiated with hydrogen plasma using the apparatus. At this time, the substrate temperature was 300 ° C.
A hydrogen plasma was set up by flowing 00 SCCM. In this state, the pressure in the reaction chamber was 1.97 mtorr. The hydrogen plasma irradiation was performed for 45 minutes.

Then, chromium is deposited to a thickness of 1500 angstroms by a sputtering method, and the gate electrode 8 is formed by patterning.
No. 12 was formed. At this time, the sheet resistance value is 1.36Ω / □.
It was. Thereafter, a contact hole is opened in the gate insulating film, a source / drain extraction electrode 813 is formed by a sputtering method or the like, and the transistor is completed by performing patterning. (FIG. 8F) In the fifth embodiment, the source
Aluminum having a film thickness of 8000 angstroms was used as a drain extraction electrode material. At this time, the sheet resistance value of aluminum was 42 mΩ / □.

An example of the characteristics of the thin film transistor (TFT) thus fabricated is shown in FIG.
-A. Where Ids is the source-drain voltage,
The measurement was performed at Vds = 4 V and a temperature of 25 ° C. Transistor
As for the size, the length L = 10 μm and the width W = 10 of the channel portion
It was 0 μm. When the transistor is turned on at Vds = 4V and Vgs = 10V, the ON current is Ids = 34.5.
A thin film semiconductor device having good transistor characteristics of μA was obtained. The field-effect mobility of the transistor determined from the saturation current region was 12.52 cm ² / v · sec. FIG. 9B shows transistor characteristics of a thin-film semiconductor device manufactured according to the conventional technique for comparison. That is, in the prior art, a thin film semiconductor device is formed in the same process as that of the fifth embodiment except that a channel portion silicon thin film is deposited at 600 ° C. by a low-pressure CVD method and oxygen plasma irradiation is not performed. . At this time, the apparatus for depositing the channel silicon thin film by the reduced pressure CVD method is the same as the apparatus for depositing the amorphous silicon thin film in the fifth embodiment, the source gas monosilane flows at 24 SCCM, and the pressure in the reactor is 13.8 mtorr. At a deposition rate of 19.00 Å / min to a thickness of 252 Å. The ON current of this conventional TFT is Ids = 4.6 μm.
At A, the field effect mobility was 4.40 cm / v · sec. In addition, after the channel silicon thin film was similarly deposited at 600 ° C. by the low pressure CVD method, oxygen plasma irradiation was performed before the gate insulating film was deposited, and all other steps were the same as those of the fifth embodiment. A thin film semiconductor device is created with TF
When the T characteristics were measured, the TFT characteristics hardly changed with or without oxygen plasma irradiation.
The FT Vgs-Ids curve was consistent with 9-b in FIG.
At this time, the on current of the TFT was Ids = 4.7 μA, and the field effect mobility was 4.44 cm ² / v · sec. That is, the channel silicon thin film is decompressed at 600 ° C.
In the conventional technique of depositing by the D method, the effect of oxygen plasma irradiation is very small. FIG. 9C illustrates the TFT characteristics of the thin-film semiconductor device manufactured according to another conventional technique. In this prior art, a thin-film semiconductor device is manufactured in the same process as in the present embodiment except that oxygen plasma irradiation is not performed in the fifth embodiment. That is, an amorphous silicon thin film is first deposited as a channel silicon layer, and then heat treatment at 600 ° C. is performed, but oxygen plasma irradiation is not performed before forming the gate insulating layer. According to this conventional technique, the TFTs produced exhibit a depression of -10 V and have poor rising characteristics. The on-state current of this thin film semiconductor device is Vds = 4V, Vgs =
12.1 μA at 10 V and 9.9 field effect mobility
It was 4 cm ² / v · sec.

From these results, as shown in the fifth embodiment, only when the amorphous silicon thin film which will become the channel portion is irradiated with oxygen plasma and then heat-treated to promote the crystallization of the channel silicon thin film, the thin film is formed. It can be seen that the transistor characteristics of the semiconductor device are significantly improved. This is because the surface of the amorphous silicon thin film is first oxidized by oxygen plasma, so that a clean MIS interface is formed, and then crystallization is advanced. Thus, it can be understood that the embodiment of the present invention has remarkably good semiconductor characteristics as compared with the thin film semiconductor device manufactured by the conventional technique.

Example 6 After forming a silicon film and a silicon oxide film on an insulating material, an impurity serving as a donor or an acceptor was added to the silicon film to form a conductive layer based on the silicon film.

In Example 6, a fused quartz substrate having a diameter of 75 mm was used as the substrate. However, any substrate may be used as long as it can withstand a heat treatment at about 600 ° C.
For example, a processed silicon substrate is also possible. First, a base SiO ₂ film is formed on the upper surface of the substrate which has been subjected to the organic cleaning and the acid cleaning.
It was deposited by the PCVD method. The base SiO ₂ film was formed at a substrate temperature of 300 ° C., a silane flow rate of 120 SCCM, oxygen of 840 SCCM,
Deposited with about 140 SLM of nitrogen. The deposition rate at this time is 3.
At 9 Å / sec, the deposition time was 12 minutes and 49 seconds. Next, a silicon film was deposited in the same manner as in Example 1 by using the LPCVD apparatus used for depositing the channel portion silicon film in Example 1. That is, the deposition temperature 55
0 ° C, silane flow rate 100 SCCM, reaction chamber pressure 400 m
A silicon film was deposited at Torr for 11 minutes and 20 seconds. The thickness of the silicon film thus obtained was 252 Å.

Next, the substrate thus obtained is subjected to a heat treatment.
Thus, the crystallinity of the silicon film was improved. This heat treatment method is
Example 1 was performed to increase the crystallinity of the silicon film 104.
Same as heat treatment. That is, at 600 ° C.
Heat treatment was performed for 3 hours. After the heat treatment, this silicon
The film is patterned with a resist, and CF₄And O ₂
Is etched by the mixed plasma of
A line pattern has been created.

Subsequently, this substrate was washed with boiling nitric acid having a concentration of 60%, and further immersed in a 1.67% aqueous hydrofluoric acid solution for 20 seconds to remove a natural oxide film on the silicon film, and a clean silicon surface appeared. Immediately after ECR-PECVD
A silicon oxide film was deposited to a thickness of 1500 angstroms by the apparatus. Here, the silicon oxide film was deposited by exactly the same method as the method of forming the gate insulating film in the present invention of the first embodiment. Next, an impurity serving as a donor or an acceptor was added to a wiring formed using a silicon film using an ion implantation apparatus. In the sixth embodiment, phosphorus is selected as an impurity to form an n-type conductive layer. However, other elements can be used according to the purpose. In Example 6, impurity ions were added using a bucket-type non-mass separation type ion implantation apparatus. As a source gas, phosphine having a concentration of 5% diluted in hydrogen was used, and an acceleration voltage of 110 KV and 3 × 10 ¹⁵ 1
/ Cm ² through a silicon oxide film. Next, this substrate was inserted into a furnace maintained at 300 ° C. in a nitrogen atmosphere to perform a heat treatment. The heat treatment time was just one hour. After the heat treatment at 300 ° C. for one hour, a contact hole was formed in the silicon oxide film, and the electrode was formed using aluminum. When the resistance of the impurity-doped silicon film wiring thus formed was measured, the sheet resistance was found to be 95%
(71 ± 15) kΩ / □ was measured with a confidence coefficient of. Generally, it has been believed that it is impossible to obtain a conductive layer by adding impurity ions to a thin film having a thickness of only several hundred angstroms and activating the added ions at a low temperature of about 300 ° C. However, in the present invention, the film quality of the silicon film subjected to the heat treatment is covered with a silicon oxide film deposited on the silicon film by the ECR-PECVD method, thereby reducing the trapping density of the silicon film surface. Since the improvement was successful, the electron scattering density was reduced, and the thin film conductive layer could be formed for the first time. This is compared with a silicon film according to the prior art to clarify the superiority of the present invention.

First, after depositing a silicon film at 600 ° C. by LPCVD, an impurity is added to a conventional silicon film having a silicon oxide film formed by ECR-PECVD, and activated at a low temperature of 300 ° C. An attempt was made to create a silicon film conductive layer. Here, a silicon film is flowed at 600 ° C., monosilane is flowed at 12.50 SCCM, and the reaction chamber pressure is 9.2 mtorr.
Except that the film was deposited to a thickness of 263 angstroms by r, an impurity-added silicon film wiring was formed in exactly the same steps as the present invention of the sixth embodiment. The sheet resistance of the silicon film of the prior art obtained in this way was measured at five locations in the substrate, and was all 1 G.
At Ω / □ or more, virtually no current flowed.

Second, a silicon film is formed by performing a heat treatment at 600 ° C. in exactly the same manner as the present invention of the sixth embodiment.
An impurity was added to a conventional silicon film having a silicon oxide film formed by a PCVD method, and an attempt was made to form a silicon film conductive layer by activation at a low temperature of 300 ° C. Here, the silicon oxide film is APCV
The substrate temperature is kept at 300 ° C. by the method D, a nitrogen / silane mixed gas containing 20% silane in nitrogen is flowed at 300 SCCM, oxygen is flowed at 420 SCCM, and about 140 SLM of diluent nitrogen is flowed together with these raw materials gas to 1500 angstroms. It deposited to the film thickness of. Except for this, the impurity-added silicon film wiring was formed in exactly the same steps as the present invention of the sixth embodiment. The sheet resistance of the conventional silicon film thus obtained was (175 ± 56) kΩ / □ with a 95% reliability coefficient. Thereafter, the substrate was mounted on the ECR-PECVD apparatus again, and subjected to hydrogen plasma treatment. The hydrogen plasma treatment was performed at a substrate temperature of 300 ° C. and a flow of 125 SCCM of hydrogen at a microwave output of 2000 W for 30 minutes. After the hydrogen plasma treatment, when the resistance values of five places in the substrate were measured, the sheet resistance of two places was 1 GΩ / □ or more, and the average value of the remaining three places was 158 kΩ / □ and the standard deviation value was 68 kΩ / □. It was.

It can be seen that a high-quality silicon film can be obtained by covering the silicon film heat-treated at 600 ° C. or less with a silicon oxide film formed by an ECR-PECVD apparatus. Therefore, as shown in Embodiment 1, the silicon film of the present invention is used for the channel portion of the thin film semiconductor device,
When a silicon oxide film formed by a CR-PECVD apparatus is used as a gate insulating layer, a thin film semiconductor device having excellent characteristics can be obtained.
Further, when impurity ions are added to the silicon film of the present invention as shown in the sixth embodiment, it becomes possible to obtain a low-resistance, low-resistance silicon film conductive layer. Therefore, the silicon film of the present invention is not only effective for a thin film semiconductor device but also for a charge coupled device (C
It can be very effectively used for non-single-crystal silicon films used for all electronic devices such as gate electrodes and wirings of CD).

(Embodiment 7) The step of adding impurity ions to a silicon film using a bucket-type non-separation type ion implantation apparatus according to the present invention in Embodiment 6 is changed to a mass separation type ion implantation apparatus to change the mass number. Except that the monovalent ion of phosphorous 31 was implanted, an attempt was made to form an impurity-doped silicon film conductive layer in exactly the same steps as in the present invention of Example 6. In Example 7, phosphor ions were implanted at 3 × 10 ¹⁵ 1 / cm ² at 90 KV. When the resistance of the impurity-added silicon film thus obtained was measured, substantially no current flowed at 5 G in the substrate at 1 GΩ / □. This is because, in the present invention of Example 6, the impurity is added by using a non-mass separation type ion implantation apparatus and a mixed gas of hydrogen and phosphine is used as a raw material gas. Is simultaneously performed, and defects generated at the time of ion addition are repaired by hydrogen ions. Therefore, a low-resistance silicon conductive layer is formed at a low temperature only for the high-quality silicon film of the present invention.

(Embodiment 8) FIGS. 10A to 10D show the M of the self-aligned staggered structure according to the eighth embodiment.
FIG. 5 is a cross-sectional view showing a manufacturing process of the silicon thin film semiconductor device that forms the IS type field effect transistor. First, the substrate 1001 is cleaned in the same manner as in the first embodiment.
As 02, an SiO ₂ film is deposited to about 2000 angstroms. Subsequently, a first silicon film is deposited on the order of 1500 angstroms and patterned to form a silicon film 1003 serving as a pad (FIG. 10A).
In the eighth embodiment, the first silicon film is deposited at a deposition temperature of 600 ° C. and a silane flow rate of 12.5 SCCM using an LPCVD apparatus in which the channel silicon film is deposited in the first embodiment.
0 Å, but the same L
Deposition of a silicon film at a deposition temperature of about 550 ° C. using a PCVD apparatus can also be performed by using disilane (Si ₂ H
₆ ), deposition at a deposition temperature of about 450 ° C.
It is also possible to deposit a silicon film at about 250 ° C. by the ECVD method. Any method may be used as long as the film formation temperature does not exceed the process maximum temperature of 600 ° C. Next, a second silicon film 1004 is deposited. The thickness of the second silicon film is about 300 angstroms or more, and the resistance of the source / drain regions after impurity implantation is the channel region when the transistor is operated. If the resistance value is sufficiently lower than the resistance value, the first silicon film or the silicon film 1003 serving as a pad is not required. In the eighth embodiment, the second silicon film 1004 is deposited by the same method as the silicon thin film serving as the channel in the first embodiment of the present invention. That is, a monosilane was used as a source gas by the LPCVD method, and the film was deposited to a thickness of 250 Å at a deposition temperature of 550 ° C. and a silane flow rate of 100 SCCM at a deposition rate of 21.2 Å / min. Thereafter, the same heat treatment as that performed in the present invention of Example 1 to increase the crystallinity of the silicon film was performed. That is, heat treatment was performed at 600 ° C. for 23 hours in a nitrogen atmosphere. (FIG. 10 (b)). Next, after patterning the second silicon film, a gate insulating layer 1005 was formed by the same method as that of the present invention in Example 1. That is, ECR-PE
A 1500 angstrom SiO ₂ film was deposited by the CVD method. Next, a metal film or the like serving as a gate electrode is formed. In the eighth embodiment, a chromium film having a thickness of 2000 Å was used as a gate electrode material. The chromium film was formed at a substrate temperature of 180 ° C. by a sputtering method. The sheet resistance of chromium immediately after the film formation was 994 mΩ / □. Was 3000 Å deposited SiO ₂ film at a substrate temperature of chromium on the 300 ° C. in APCVD method subsequently. Thereafter, patterning was performed with a resist to form a gate electrode 1006 and a protective cap layer 1007 made of a SiO ₂ film, and impurity ions were added. In the eighth embodiment, although phosphorus was selected as an impurity and the aim was to produce an n-type thin film semiconductor device, other elements can of course be used according to the purpose. In Example 8, impurity ions were added using an ion implantation device without a mass spectrometer. Phosphine having a concentration of 5% diluted in hydrogen was used as a raw material gas, and was driven into a concentration of 5 × 10 ¹⁵ 1 / cm ² at an acceleration voltage of 110 kV. In this manner, part of the first silicon film and the second silicon film becomes the source / drain region 1008,
Since there is the protective cap layer 1007 based on the iO ₂ film, the second silicon film located thereunder is not ion-added,
The configuration of the channel unit 1009 (FIG. 10
(C)). Next, the substrate was subjected to a heat treatment at 350 ° C. for 2 hours in a nitrogen atmosphere to activate additional impurity ions.
Thereafter, an SiO ₂ film 1010 is formed as an interlayer insulating film by 5000.
Angstrom deposition, contact holes are opened, wiring 1011 is made of aluminum or the like, and a self-aligned thin film semiconductor device is completed (FIG. 10).
(D)).

When the transistor characteristics of the self-aligned thin film semiconductor device thus prepared were measured, it was found that L = W =
10 μm, Vds = 4 V, Vgs = 10 V, ON current is 4.89 μA, and minimum value of source / drain current is Vgs
= -3.5 V, 0.21 pA when Vgs = -10 V, the off-state current is 2.65 pA, and the field-effect mobility μo
= 26.1 cm ² / v · sec, which is a very good self-aligned thin film semiconductor device.

For comparison, the channel portion silicon film was LP
A self-aligned thin-film semiconductor device was produced in exactly the same steps as the present invention of Example 8 except that the device was produced at 600 ° C. by the CVD method. However, as described in detail in the sixth embodiment, in the conventional silicon film, the additional impurity element in the thin film portion is not activated, and the resistance of the impurity added silicon film in the thin film portion is too high. .9 pA, which was impractical. On the other hand, in the present invention of the eighth embodiment, the hydrogenated plasma treatment, which is the main cause of the characteristic fluctuation, was eliminated, and a good self-aligned thin film semiconductor device was successfully formed in a low temperature process. This is because even if the basic semiconductor characteristics are improved by reducing the thickness of the channel silicon film semiconductor layer to 500 Å or less as shown in the second embodiment, the thin film conductor according to the sixth embodiment of the present invention is still required. This is because the formation of the source / drain region of the thin film portion was easily performed at a low temperature by forming the conductive silicon film. That is, the activation of the impurity serving as a donor or an acceptor is conventionally performed on a silicon film having a thickness of about 1000 Å or more.
It could not be achieved unless a heat treatment of about 50 ° C. or more was added.
Therefore, in the self-aligned thin-film semiconductor device, the film thickness of the channel portion was inevitably about 1000 Å or more, and the characteristics were poor. In addition, after the gate insulating layer and the gate electrode are completed, a heat treatment of about 550 ° C. or more is performed for the purpose of activating the additional impurity ions, so that the quality of the gate insulating film deteriorates, and hydrogenation is indispensable. There was. In addition, since it was difficult to use a metal material for the gate electrode, the resistance of the gate line was high, and it was necessary to separately form the gate electrode and the gate line. However, according to the present invention, a metal material can be used as a gate electrode, and at the same time, hydrogen treatment, which is a main cause of variation, is eliminated, and a thin film semiconductor device with high characteristics can be stably manufactured by a simpler manufacturing method. did.

[0058]

As described above, according to the present invention,
Depositing a silicon film on a substrate whose surface is an insulating material,
After subjecting the silicon film to a heat treatment at about 600 ° C.,
By depositing a silicon oxide film by the R-PECVD method, the quality of the silicon film can be improved. For example, according to this, in forming a thin film semiconductor device on a substrate having a surface made of an insulating material, a channel portion silicon film is deposited, and then a heat treatment is performed at a temperature of 600 ° C. or less.
A method for manufacturing a thin film semiconductor device including a step of forming by a PECVD method, or after depositing an amorphous silicon film forming a channel portion silicon film semiconductor layer, and before forming a gate insulating layer, oxygen is deposited on the amorphous silicon film. The transistor characteristics are greatly improved by a manufacturing method including a process of irradiating plasma and then heat-treating at a temperature of 600 ° C. or less, and a thin-film semiconductor device having such excellent transistor characteristics can be uniformly and simply applied to a large area. This method has a great effect of realizing high performance and low cost of an active matrix liquid crystal display using multiple layers of LSIs and thin film transistors.

[Brief description of the drawings]

FIG. 1 is a sectional view of an element in each step of manufacturing a silicon thin film semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an outline of an electron cyclotron resonance plasma CVD apparatus used in an embodiment of the present invention.

FIG. 3 is a diagram showing an effect of the present invention.

FIG. 4 is a diagram showing the effect of the present invention.

FIG. 5 is an element sectional view of a silicon thin film semiconductor device showing one embodiment of the present invention.

FIG. 6 is a diagram showing an effect of the present invention.

FIG. 7 is a cross-sectional view of an element in each step of manufacturing a silicon thin-film semiconductor device according to an embodiment of the present invention.

FIG. 8 is a sectional view of an element in each step of manufacturing a silicon thin film semiconductor device according to an embodiment of the present invention.

FIG. 9 is a diagram showing an effect of the present invention.

FIG. 10 is a sectional view of an element in each step of manufacturing a silicon thin-film semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

101 ... underlying substrate 102 ... underlying protective film 103 ... source / drain region 104 ... silicon thin film 105 ... channel portion silicon thin film 106 ... gate insulating film 107 ... gate electrode 108 ..Interlayer insulating film 109 ... Source / drain extraction electrode 201 ... Waveguide 202 ... Reaction chamber 203 ... Gas introduction tube 204 ... External coil 205 ... Substrate 206 ... Heater 207: gas introduction tube 501: source / drain region 502: gate electrode 503: source / drain region 504: gate electrode 505: gate electrode 506: mask material 507 ...・ Source / drain region 701 ・ ・ ・ Substrate 702 ・ ・ ・ Primary protective film 703 ・ ・ ・ Silicon film to be a pad 704 ・ ・ ・ Second Silicon film 705 gate insulating layer 706 gate electrode 707 resist 708 source / drain region 709 channel silicon film 710 interlayer insulating film 711 wiring 801 ..Insulating substrate 802 base SiO ₂ film 803 impurity-containing silicon thin film 804 source / drain region 805 amorphous silicon thin film 806 amorphous silicon thin film 807 is left ... oxygen plasma 808 ... amorphous silicon thin film becomes SiO ₂ film 809 ... one channel portion formed by oxidizing the residual to that amorphous silicon thin film 810 ..・ SiO ₂ deposited by ECR-PECVD method
Film 811 ··· Silicon thin film constituting channel portion 812 ··· Gate electrode 813 ··· Source / drain extraction electrode 1001 ··· Substrate 1002 ··· Underlayer protective film 1003 ··· Silicon film to be a pad 1004. ..Second silicon film 1005 gate insulating layer 1006 gate electrode 1007 protective cap layer 1008 source / drain region 1009 channel silicon film 1010 interlayer insulating film 1011 ... wiring

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[Procedure amendment]

[Submission date] April 26, 2001 (2001.4.2
6)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction contents]

[0010]

According to a method of manufacturing a thin film semiconductor device of the present invention, a silicon oxide film is formed on a substrate, an amorphous silicon thin film is formed on the silicon oxide film, and the amorphous silicon thin film is formed on the silicon oxide film. Forming a gate insulating film, and thereafter crystallizing the amorphous silicon thin film. In the method for manufacturing a thin film semiconductor device according to the present invention, the first gate insulating film may be formed by oxidizing the amorphous silicon thin film.
Silicon oxide film and second deposited by ECR-PECVD method
It is characterized by comprising two layers of a silicon oxide film.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0058

[Correction method] Change

[Correction contents]

[0058]

As described above, according to the present invention, the amorphous silicon thin film is sandwiched between the silicon oxide film formed below the amorphous silicon thin film and the silicon oxide film formed above the amorphous silicon thin film. Since the crystallization is performed in a state where the semiconductor device is in a state of being removed, a high-quality silicon thin film can be obtained, and the characteristics of the semiconductor device can be improved.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 627G F-term (Reference) 4M104 BB02 BB13 CC05 DD34 DD37 DD43 EE03 EE11 5F052 AA17 DA02 DB01 DB02 DB03 DB07 JA01 5F058 BA20 BC02 BF03 BF09 BF23 BF29 BH20 5F110 AA16 AA17 AA28 AA30 BB01 BB11 CC05 CC06 DD01 DD02 DD03 DD05 DD13 EE04 EE09 EE43 EE44 EE45 FF02 FF05 FF09 FF25 FF31 FF23 GG25 GG13 GG25 GG13 HL23 HM14 NN02 NN04 NN23 NN35 PP01 PP10 PP13 QQ11 QQ25

Claims (9)

[Claims] 1. A channel portion silicon film semiconductor layer is formed on one surface of a substrate having at least a surface made of an insulating material,
A gate insulating layer and a gate electrode formed on the semiconductor layer;
In a thin film semiconductor device constituting an IS type field effect transistor, a step of depositing a silicon film constituting a channel portion silicon film semiconductor layer on an insulating material; A method of manufacturing a thin film semiconductor device, comprising: a step of performing a heat treatment at a temperature; and a step of forming a gate insulating layer formed on a channel portion silicon film semiconductor layer by an electron cyclotron resonance plasma CVD method. 2. The thin film semiconductor device according to claim 1, wherein the thickness of the channel portion silicon film semiconductor layer is 500 Å or less. 3. A gate electrode formed so as to face the channel region with a channel region, a source region, a drain region, and a gate insulating layer formed on at least one surface of a substrate having at least a surface made of an insulating material. In a thin film semiconductor device having a structure in which at least one of a source region and a drain region does not overlap with a gate electrode via a gate insulating film, a channel portion silicon film semiconductor A step of depositing a silicon film constituting a layer, a step of forming a source region and a drain region, and a step of heat-treating the substrate on which the channel region and the source and drain regions are formed at a temperature of 600 ° C. or less. A method for manufacturing a thin film semiconductor device, comprising: 4. A channel portion silicon film semiconductor layer is formed on one surface of a substrate having at least a surface made of an insulating material,
A gate insulating film and a gate electrode formed on the semiconductor layer;
In a thin film semiconductor device constituting an IS type field effect transistor, after depositing an amorphous silicon film constituting a channel silicon semiconductor layer on an insulating material, a gate insulating layer is formed on the amorphous silicon film Before you do
A method of manufacturing a thin film semiconductor device, comprising: a step of irradiating an oxygen plasma on the amorphous silicon film; and a step of heat-treating the substrate irradiated with the oxygen plasma at a temperature of 600 ° C. or less. 5. A silicon film formed on a substrate having at least a surface made of an insulating material, wherein said silicon film has a thickness of 60%.
A silicon film which has been subjected to a heat treatment at a temperature of 0 ° C. or lower and a part of the silicon film is covered with a silicon oxide film formed by an electron cyclotron resonance plasma CVD method. 6. A silicon film containing an impurity serving as a donor or an acceptor, characterized by including the following steps. (1) A step of depositing a silicon film and a step of heat-treating the substrate on which the silicon film is formed at a temperature of 600 ° C. or less. (2) A step of forming a silicon oxide film after the above steps. (3) After passing through the above-mentioned steps, the silicon film is converted into an impurity serving as a donor or an acceptor using a mixture of a hydride and hydrogen of the impurity element as a source gas by using a bucket type non-separable ion implantation apparatus. The process of driving. 7. The silicon film according to claim 6, wherein the silicon oxide film is formed by an electron cyclotron resonance plasma CVD method. 8. A channel portion silicon film semiconductor layer is formed on one surface of a substrate having at least a surface made of an insulating material,
A gate insulating layer and a gate electrode formed on the semiconductor layer;
A method of manufacturing a thin film semiconductor device comprising a thin film semiconductor device constituting an IS type field effect transistor, comprising the following steps. (1) A step of depositing a silicon film on an insulating material and a step of heat-treating the substrate on which the silicon film is formed at a temperature of 600 ° C. or lower. (2) A step of forming a gate insulating layer after the above steps. (3) a step of forming a gate electrode on the gate insulating film so as to cover a portion which will later become a channel region after the above steps. (4) After the above steps, using a gate electrode as a mask, an impurity serving as a donor or an acceptor is used, and a mixture of a hydride and hydrogen of the impurity element is used as a source gas, using a bucket-type mass non-separable ion implantation apparatus. Forming a source region and a drain region by implantation. 9. The method according to claim 8, wherein the gate insulating layer is formed by an electron cyclotron resonance plasma CVD method.
A manufacturing method of the thin film semiconductor device according to the above.