JP2002009074A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a technique capable of increasing the brightness of a projector by improving the light shielding property of a liquid crystal light valve. The A light incident, the first insulating film 13 and the laminated film made of the second insulating film 14 that is provided on the second sidewall of the metal film M _2, and the sidewalls of the fourth metal film M ₄ By transmitting the light through a laminated film including the third insulating film 19 and the fourth insulating film 20 provided, light leakage to the pixel driving MOS device is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a pixel driving M for a liquid crystal projector.
The present invention relates to a technology that is effective when applied to a semiconductor device having a MOSIC (MOS Integrated Circuit) provided with an OS (Metal Oxide Semiconductor) device.

[0002]

2. Description of the Related Art A silicon (Si) chip based liquid crystal light valve utilizing light reflection is a pixel driving MOS.
Since the device is built under the reflection mirror, it has a feature that the light use efficiency is higher than that of the transmission type liquid crystal.

The above-mentioned liquid crystal light valve is disclosed in, for example, “Nikkei Micro Device” 1999, published by Nikkei McGraw-Hill.
As shown in FIG.
The liquid crystal layer is sandwiched between the IC substrate and the counter electrode glass substrate. A flattened mirror electrode is formed on the surface of the MOSIC substrate, and an extraction electrode for extracting the pixel electrode to the mirror electrode is the same as a light-shielding layer provided to prevent light from entering the pixel driving MOS device. It is composed of one layer of a metal film.

[0004]

However, if a high-output light source is used to increase the brightness of the projector,
The present inventors have found that light leakage from a gap between the extraction electrode and the light-shielding layer causes a characteristic change of the pixel driving MOS device. That is, the incident light generates electrons in the substrate, and the electrons shift the holding voltage of the pixel driving MOS device. As a result, the voltage of the mirror electrode fluctuates, causing fluctuations in the brightness of the liquid crystal.

In order to increase the light-shielding ability, it is necessary to reduce the distance between the extraction electrode and the light-shielding layer. However, since the distance between the extraction electrode and the light-shielding layer is determined by the layout rule, it is smaller than the minimum space of the layout rule. Can not do it. For this reason, there remains a problem that a high-output light source cannot be used and the brightness of the projector is limited.

An object of the present invention is to provide a technique capable of increasing the brightness of a projector by improving the light-shielding properties of a liquid crystal light valve.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, when a metal layer having a light shielding function is formed on a substrate, after forming a first layer composed of a first metal film on the substrate, An insulating film and a second metal film are sequentially deposited on the first layer, and then the surface of the second metal film is polished to fill the gap between the adjacent first layers with the second metal film. .

According to the above means, the incident light passes through the insulating film provided on the side wall of the first layer made of the first metal film, and the amount of light shielding is controlled by this film thickness. It becomes possible. Therefore, by reducing the thickness of the insulating film, the light transmission path can be narrowed, and light leakage to the semiconductor device can be reduced.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) A method for manufacturing a MOSIC substrate according to an embodiment of the present invention will be described with reference to cross-sectional views of essential parts of a semiconductor substrate shown in FIGS.

First, as shown in FIG. 1, after an insulating film 2 for element isolation is formed on a main surface of a substrate 1 made of, for example, p-type silicon single crystal, a gate insulating film 3 is formed on the surface of the substrate 1.
To form Next, for example, a CVD (Chem
After depositing a polycrystalline silicon film to which phosphorus (P) is added by an ical vapor deposition method, and subsequently depositing a tungsten silicide (WSi) film by, for example, a sputtering method,
W by dry etching using resist pattern as mask
The Si film and the polycrystalline silicon film are sequentially processed to form a WSi
A gate electrode 4 made of a film and a polycrystalline silicon film is formed.

Next, an n-type impurity, for example, P or arsenic (As) is implanted into the substrate 1 by ion implantation using the gate electrode 4 as a mask, thereby forming an n-type semiconductor region 5 constituting a source and a drain. .

Next, a BPSG (Boron-doped
After depositing the Phospho Silicate Glass film 6, the insulating film of the same layer as the BPSG film 6 and the gate insulating film 3 is sequentially etched using the resist pattern as a mask to form a contact hole 7 reaching the n-type semiconductor region 5. Next, after a tungsten (W) film, an aluminum (Al) film, and a W film are sequentially deposited on the substrate 1 from the lower layer, the W film, the Al film, and the W film are sequentially etched using the resist pattern as a mask, and the W film, the Al film, forming a formed pixel electrode 8 in the first metal film M ₁ of a laminated structure comprising a film and a W film.

Thereafter, a first interlayer insulating film 9 is formed on the substrate 1. The first interlayer insulating film 9 has a laminated structure in which, for example, a TEOS oxide film, a SOG (Spin On Glass) film, and a TEOS oxide film are sequentially deposited from the lower layer. First, a TEOS (Tetra Ethyl Ortho Silicate) gas and an oxygen (O ₂ ) gas are used to form a TEOS by a plasma CVD method.
After forming the oxide film, an SOG film is applied by a spin coating method to smooth its surface, and a TEOS oxide film is formed by a plasma CVD method using a TEOS gas and an O ₂ gas.

Next, as shown in FIG. 2, the first interlayer insulating film 9 is etched using the resist pattern as a mask to form a contact hole 10 reaching the pixel electrode 8. Next, after a W film, an Al film, and a W film are sequentially deposited on the substrate 1 from the lower layer, the W film is formed using the resist pattern as a mask.
Sequentially etching the Al film and the W film, W film, thereby forming a light-shielding layer 11 and the extraction electrode 12 comprised of the second metal film M ₂ of a laminated structure consisting of an Al film and a W film. Next, a first insulating film 13, for example, a TEOS oxide film and a second insulating film 14, for example, a silicon nitride film, are sequentially deposited on the substrate 1 by a plasma CVD method.

Next, as shown in FIG. 3, to form the buried layer 15 composed of the third metal film M ₃ into the gap between the second metal film M ₂ adjacent. The buried film 15 is formed by depositing a third metal film M ₃ , for example, a W film on the substrate 1, and then forming a CMP (C
by polishing the third metal film M ₃ in hemical Mechanical Polishing) method, it is embedded between the second adjacent metal film M _2. Note that the second insulating film 14 functions as a stopper film during polishing.

Next, as shown in FIG.
An interlayer insulating film 16 is formed. Second interlayer insulating film 16 is formed of, for example, a TEOS oxide film. First, TE
TE by plasma CVD using OS gas and O ₃ gas
After forming the OS oxide film, the surface of the TEOS oxide film is flattened by the CMP method, and the TEOS oxide film is formed by the plasma CVD method using a TEOS gas and an O ₃ gas.

Next, the second interlayer insulating film 16 is etched using the resist pattern as a mask to form a contact hole 17 reaching the extraction electrode 12. Then substrate 1
After a titanium (Ti) film and an Al film are sequentially deposited from the lower layer on the upper side, the Al film and the Ti film are sequentially etched using the resist pattern as a mask to form a fourth metal film M ₄ having a laminated structure including the Al film and the Ti film. Mirror electrode 1 composed
8 is formed. Next, a third insulating film 19 is formed on the substrate 1.
For example, a TEOS oxide film and a fourth insulating film 20, for example, a silicon nitride film are sequentially deposited by a plasma CVD method.

Next, as shown in FIG. 5, to form the buried layer 21 composed of a fifth metal film M ₅ into the gap between the fourth metal film M ₄ adjacent. The buried film 21 is formed by depositing a fifth metal film M ₅ , for example, a W film, on the substrate 1 and then polishing the fifth metal film M ₅ by a CMP method to form an adjacent fourth film M ₅ .
Embedded between the metal film M _4. The fourth insulating film 20
Functions as a stopper film during polishing.

Thereafter, a MOSIC substrate is substantially completed by forming a surface insulating film 22 on the substrate 1. The surface insulating film 22 has a laminated structure in which, for example, a TEOS oxide film and a SiN film are sequentially deposited from a lower layer by a plasma CVD method.

In the first embodiment, the adjacent second
The buried film 15 for filling the gap between the metal films M ₂ is
The third metal film M ₃ deposited on the upper surface was formed by polishing by a CMP method.
The resist pattern is formed by negative reverse using the mask pattern, by processing the third metal film M ₃ deposited on the substrate 1 using the resist pattern as a mask, may be formed above the buried layer 15. The same applies with respect to the production method of the fourth metal film embedded fill the gap between M ₄ film 21 adjacent.

As described above, according to the first embodiment, M
Light not reflected out of the light entering the OSIC substrate, the light blocking layer 11 and the lead electrode 1 composed of the second metal film M ₂
Third insulating film provided on the side wall of the configured mirror electrode 18 and the first insulating film 13 provided on the second sidewall with a second insulating film 14 and the laminated film, and the fourth metal film M ₄ Since the light passes through the laminated film of the first insulating film 19 and the fourth insulating film 20, the light-shielding amount can be controlled by these film thicknesses. Therefore, by reducing the thickness of the stacked film of the first insulating film 13 and the second insulating film 14 and the thickness of the stacked film of the third insulating film 19 and the fourth insulating film 20, the light transmission path is reduced. The width can be reduced, and light leakage to the pixel driving MOS device can be reduced.

(Embodiment 2) A method of manufacturing a MOSIC substrate according to another embodiment of the present invention will be described with reference to cross-sectional views of essential parts of a semiconductor substrate shown in FIGS.

First, in the first embodiment, FIG.
As in the manufacturing method described with reference to FIG.
After forming a pixel electrode 8 composed of a device (not shown) and the first metal film M ₁ , a first interlayer insulating film 9 is formed on the substrate 1.

Next, as shown in FIG.
After depositing a film, an Al film and a W film in order from the lower layer, the W film, the Al film and the W film are sequentially etched using the resist pattern as a mask, and a sixth metal film having a laminated structure including the W film, the Al film and the W film is formed. forming a composed light shielding layer 23 in the M _6. Next, a fifth insulating film 24, for example, a TEOS oxide film is deposited on the substrate 1 by a plasma CVD method.

Next, as shown in FIG. 7, the fifth insulating film 24 and the first interlayer insulating film 9 are sequentially etched using the resist pattern as a mask to form a contact hole 25 reaching the pixel electrode 8.

Next, as shown in FIG.
After depositing a film, an Al film, and a W film in order from the lower layer, the W film, the Al film, and the W film are sequentially etched using the resist pattern as a mask, and a seventh metal film having a laminated structure including the W film, the Al film, and the W film is formed. composed of M ₇ lead electrode 26
Is formed in contact with the pixel electrode 8 through the contact hole 25.

Next, as shown in FIG.
An interlayer insulating film 27 is formed. Second interlayer insulating film 27 is formed of, for example, a TEOS oxide film. First, TE
TE by plasma CVD using OS gas and O ₃ gas
After forming the OS oxide film, the surface of the TEOS oxide film is flattened by the CMP method, and the TEOS oxide film is formed by the plasma CVD method using a TEOS gas and an O ₃ gas.
Next, using the resist pattern as a mask, the second interlayer insulating film 27 is etched to form a contact hole 28 reaching the extraction electrode 26.

Next, as shown in FIG.
After the i film and the Al film are sequentially deposited from the lower layer, the Al film and the Ti film are sequentially etched using the resist pattern as a mask, and the eighth structure of the laminated structure including the Al film and the Ti film is formed.
The mirror electrode 29 made of a metal film M ₈ is formed. After that, the surface insulating film 30 is formed on the substrate 1.

As described above, according to the second embodiment, M
Light not reflected out of the light entering the OSIC substrate, will be transmitted through the fifth insulating film 24 provided on the side wall of the configured light-shielding layer 23 in the sixth metal film M _6, shielded by this film thickness The amount can be controlled. Therefore, the light transmission path can be narrowed by reducing the thickness of the fifth insulating film 24, and light leakage to the pixel driving MOS device can be reduced.

(Embodiment 3) A method for manufacturing a MOSIC substrate according to another embodiment of the present invention will be described with reference to the cross-sectional views of essential parts of a semiconductor substrate shown in FIGS.

First, in Embodiment 1, FIG.
As in the manufacturing method described with reference to FIG.
Forming a formed pixel electrode 8 on the device (not shown) and the first metal film M _1.

Next, as shown in FIG. 11, a first interlayer insulating film 31 is formed on the substrate 1. The first layer insulating film 31 has a laminated structure in which, for example, a TEOS oxide film, an SOG film, and a TEOS oxide film are sequentially deposited from the lower layer. First, plasma CVD using TEOS gas and O ₃ gas
After forming a TEOS oxide film by the SOG method,
A TEOS oxide film is formed by plasma CVD using a TEOS gas and an O ₃ gas. Alternatively, first interlayer insulating film 31 is formed of, for example, a TEOS oxide film. First, TE
TE by plasma CVD using OS gas and O ₃ gas
After forming the OS oxide film, the surface of the TEOS oxide film is flattened by the CMP method, and the TEOS oxide film is formed by the plasma CVD method using a TEOS gas and an O ₃ gas.

Next, the first interlayer insulating film 31 is etched using the resist pattern as a mask to form a contact hole 32 reaching the pixel electrode 8.

Next, as shown in FIG.
After depositing a film, an Al film, and a W film in order from the bottom, the W film, the Al film, and the W film are sequentially etched using the resist pattern as a mask, and a ninth metal film having a laminated structure including the W film, the Al film, and the W film is formed. the first light-shielding layer 33a composed of M ₉
To form Next, a sixth insulating film 34 having a thickness of about 200 to 400 nm, for example, a TEOS oxide film is deposited on the substrate 1 by a plasma CVD method.

Next, as shown in FIG.
After depositing a film, an Al film, and a W film in order from the bottom, the W film, the Al film, and the W film are sequentially etched using the resist pattern as a mask, and a tenth metal film having a laminated structure including the W film, the Al film, and the W film is formed. the second shielding layer 33 consists of M ₁₀
b is formed.

Next, as shown in FIG. 14, a second interlayer insulating film 35 is formed on the substrate 1. The second insulating film 35
For example, it has a laminated structure in which a TEOS oxide film, an SOG film, and a TEOS oxide film are sequentially deposited from a lower layer. First, plasma CVD using TEOS gas and O ₃ gas
After forming a TEOS oxide film by the SOG method,
A TEOS oxide film is formed by plasma CVD using a TEOS gas and an O ₃ gas. Alternatively, the second interlayer insulating film 33 is composed of, for example, a TEOS oxide film. First, TE
TE by plasma CVD using OS gas and O ₃ gas
After forming the OS oxide film, the surface of the TEOS oxide film is flattened by the CMP method, and the TEOS oxide film is formed by the plasma CVD method using a TEOS gas and an O ₃ gas.

Next, as shown in FIG. 15, using the resist pattern as a mask, the second interlayer insulating film 35 is etched to form a contact hole 36 reaching the first light shielding layer 33a connected to the pixel electrode 8. Then after depositing sequentially a Ti film and an Al film on the substrate 1 from the lower layer, the resist pattern Al film and a Ti film are sequentially etched as a mask, in the 11th metal film M ₁₁ of a laminated structure consisting of an Al film and a Ti film The formed mirror electrode 37 is formed. After that, a surface insulating film 38 is formed on the substrate 1.

As described above, according to the third embodiment, M
Light not reflected out of the light entering the OSIC substrate, it will be transmitted through the sixth insulating film 34 provided on the side wall of the first light-shielding layer 33a formed of the ninth metal film M _9, the thickness Thus, the amount of light shielding can be controlled by reducing the thickness of the sixth insulating film 34, so that the light transmission path can be narrowed, and light leakage to the pixel driving MOS device can be achieved. Can be reduced.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, the present invention is applied to a method of manufacturing a MOSIC substrate constituting a liquid crystal light valve for a projector. However, the present invention is also applicable to a method of manufacturing a light shield of an IC substrate requiring light resistance.

[0044]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, light leakage to the pixel driving MOS device can be reduced, and the light shielding property of the liquid crystal light valve can be improved. This makes it possible to increase the brightness of the projector.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a MOSIC substrate according to Embodiment 1 of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MOSIC substrate according to the first embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MOSIC substrate according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MOSIC substrate according to the first embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MOSIC substrate according to the first embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MOSIC substrate according to the second embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MOSIC substrate according to the second embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MOSIC substrate according to the second embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MOSIC substrate according to the second embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MOSIC substrate according to the second embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MOSIC substrate according to the third embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MOSIC substrate according to the third embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MOSIC substrate according to the third embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MOSIC substrate according to the third embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MOSIC substrate according to the third embodiment of the present invention;

DESCRIPTION OF SYMBOLS 1 Substrate 2 Element isolation insulating film 3 Gate insulating film 4 Gate electrode 5 N-type semiconductor region 6 BPSG film 7 Contact hole 8 Pixel electrode 9 First interlayer insulating film 10 Contact hole 11 Light-shielding layer 12 Extraction electrode 13 First insulating film 14 second insulating film 15 buried film 16 second interlayer insulating film 17 contact hole 18 mirror electrode 19 third insulating film 20 fourth insulating film 21 buried film 22 surface insulating film 23 light shielding layer 24 5 insulating film 25 contact hole 26 extraction electrode 27 second interlayer insulating film 28 contact hole 29 mirror electrode 30 surface insulating film 31 first interlayer insulating film 32 contact hole 33a first light shielding layer 33b second light shielding layer 34 sixth insulation Film 35 second interlayer insulating film 36 contact hole 37 mirror electrode 38 surface Enmaku M ₁ first metal film M ₂ second metal film M ₃ third metal film M ₄ fourth metal film M ₅ fifth metal film M ₆ 6 metal film M ₇ 7 metal film M ₈ 8 metal film M ₉ 9 metal film M ₁₀ 10 metal film M ₁₁ 11 metal film

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroki Sakai 3-16-6 Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. (72) Katsumi Matsumoto 3681 Hayano, Mobara-shi, Chiba Prefecture Hitachi Device Engineering In-house F-term (reference) 2H091 FA34Y FB08 FC10 FC26 FD04 GA13 LA03 MA07 2H092 JA25 JA46 JB07 JB54 JB56 KA03 KA10 KA15 KB25 MA05 MA08 MA15 MA18 MA19 MA27 NA22 NA25 PA09 RA05 5F033 HH04 HH18 KK18H19 KK LL04 MM07 MM08 NN06 NN29 PP06 PP15 QQ08 QQ09 QQ10 QQ25 QQ37 QQ48 RR06 RR09 RR15 SS04 SS15 SS21 TT02 VV00 XX32 5F040 DB01 DC01 EC01 EC07 EC13 EH01 EH02 EJ02 EJ03 EJ07 EK01 EK01 A0313

Claims (4)

[Claims] 1. A method for manufacturing a semiconductor device, wherein a metal layer having a light-shielding function is formed on a substrate, comprising: (a) forming a pattern of a first layer made of a first metal film on the substrate; (B) a step of sequentially depositing an insulating film and a second metal film on the first layer, and (c) polishing the surface of the second metal film to form an adjacent first interlayer. Filling the second metal film in the gaps of the semiconductor device. 2. A method for manufacturing a semiconductor device in which a metal layer having a light-shielding function is formed on a substrate, comprising: (a) forming a pattern of a first layer made of a first metal film on the substrate; (B) sequentially depositing an insulating film and a second metal film on the first layer, and (c) forming a resist pattern using a negative inversion mask of the pattern of the first layer. Processing the second metal film using the resist pattern as a mask. 3. A method for manufacturing a semiconductor device, comprising forming a metal layer having a light-shielding function on a substrate, comprising: (a) forming a pattern of a first layer comprising a first metal film on the substrate; Depositing a first insulating film on the first layer, and (b) depositing a second metal film on the first layer and then forming a second metal film on the second layer. (C) depositing a second insulating film on the second layer, and (d) sequentially processing the second insulating film and the first insulating film. Forming a connection hole reaching the first layer; and (e) forming a third metal film on the second insulating film, and then forming the third metal film. (F) forming a third insulating film as an upper layer of the third layer, Forming a connection hole reaching the third layer by processing the third insulating film; and (g) depositing a fourth metal film on the third insulating film and then forming the fourth metal film. And patterning a fourth layer reaching the third layer. 4. A method for manufacturing a semiconductor device in which a metal layer having a light-shielding function is formed on a substrate, comprising: (a) forming a pattern of a first layer made of a first metal film on the substrate; (B) forming a first insulating film on the first layer and then processing the first insulating film to form a connection hole reaching the first layer; (c) Depositing a second metal film on the first insulating film and then patterning a second layer constituted by the second metal film; and (d) forming a second insulating film on the second metal film. Forming a film; and (e) forming a third metal film on the second insulating film, and then forming a third metal film and filling the gap between the adjacent second layers with a third metal film. Patterning a layer, and (f) forming a third insulating film on the third layer, Forming a connection hole reaching the second layer by sequentially processing an insulating film and the second insulating film; and (g) depositing a fourth metal film on the third insulating film. Patterning a fourth layer formed of a fourth metal film and reaching the second layer.