JP2002083928A - Semiconductor device and trimming method thereof - Google Patents

Abstract

(57) Abstract: A semiconductor device and a trimming method for selecting and adjusting a switch element connected to a node of a resistance circuit network by fusing and non-fusing of a fuse are provided. A trimming means has a resistor network and switch elements connected to nodes p1 to pm-1 of the resistor network, and the switch elements s1 to sm-1 are connected to the nodes. Conduction / non-conduction control of 1 and designated node in resistance network 6
selection circuit 5 for selecting the output of px and a plurality of fuses F
And a fusing switch SW1 for controlling the fusing of the fuse F. A control signal is supplied to the selection circuit 5 when the fuse is blown or not blown.
Trimming state storage circuit 41 that outputs d1 to d4 and d1B to d4B
Input the serial data DATA with ~ 44 and this serial data DATA
Serial interface circuit 3 which forms various signals adr3 for controlling the operation of trimming state storage circuits 41 to 44 from
And.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of handling an analog amount in an internal circuit of the semiconductor device and performing fine adjustment (trimming) of the analog amount.

[0002]

2. Description of the Related Art When an analog quantity is handled in an internal circuit of a semiconductor device incorporated in an integrated circuit (IC) and a fine adjustment of the analog quantity is desired to be performed, the conventional technique requires a characteristic variation in an IC manufacturing process. To hold it small
Adjustments are made at the wafer process stage. But IC
In a post-process, for example, after molding or the like, it is necessary to perform adjustment in consideration of the fluctuation in advance in order to avoid the influence of stress.

In FIG. 9, according to Japanese Patent Application Laid-Open No. H11-204740, "Semiconductor Device", in a semiconductor device 110 in which trimming means is added to resistance networks Ra to Rd, the trimming means includes fuses 105, 106, and 107. Fuse 105,
Switching means 115, 116, 11 for switching the connection destination of 106, 107 to one of resistance networks Ra to Rd and fuse current supply line c.
7 is provided.

[0004] With this configuration, the data of the microprocessor MPU-118b of the trimming jig 118 is transferred to the P / S converter 118c.
Then, the data is converted into serial data and transmitted to the semiconductor device 110. In the semiconductor device 110, the serially transmitted data is
4b, is converted to parallel data by the S / P converter 114a, latches this data in the register 114, and
3 and, for example, the designated switching means 115 (116,
117) to switch the fuse 105 (106, 107) to the fuse current supply line c. As a result, fuse 105 (106, 10
7) is blown, and the trimming resistor Rb can be added to and added to the resistor Rd to perform trimming adjustment.

[0005]

As described above, when trimming adjustment is performed at the wafer process stage, the IC
It is necessary to make adjustments in advance in consideration of the influence on the characteristics in the subsequent process (for example, molding) by taking into account the variation. However, in the case where there is variation in the amount of variation due to the mold processing, or in the case where higher accuracy is required, there is a limit in trimming adjustment at the wafer process stage.

In the semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 11-204740, "semiconductor device", the trimming of the resistor network is adjusted by adjusting the resistance network of the individual resistors short-circuited by the fuse via the switching means. Among them, the fuse having a specific resistance is selectively blown and opened. Therefore, from the viewpoint of the stability of the trimming adjustment, a sufficiently high resistance value is required for the sum of the resistance of the fuse and the ON resistance of the switching means (for example, a semiconductor (FET) switch). It is used to form a resistance network by connecting resistance elements of up to several MΩ in series.

An object of the present invention is to adjust the integrated circuit (IC) at the final stage of the product, and to use a fuse as a trimming means without short-circuiting a trimming resistor.
Even if a relatively low resistance element is used, it has a highly accurate and stable trimming adjustment means, and it can be confirmed that the trimming has been adjusted to the optimal trimming state. An object of the present invention is to provide a semiconductor device capable of preventing the device from entering the trimming mode again even if it enters, and a trimming method therefor.

[0008]

According to the present invention, there is provided a semiconductor device having trimming means in a resistance network, wherein the trimming means is connected to the resistance network and each node of the resistance network. It has a switching element, and controls the conduction and non-conduction of this switching element,
A selection circuit for selecting an output of a designated node; a plurality of fuses; and a first switch for controlling the fusing of the fuses. Trimming state storage for outputting a control signal to the selection circuit when the fuses are blown or not blown. It is provided with a circuit and a serial interface circuit which receives serial data and forms various signals for controlling the operation of the trimming state storage circuit from the serial data.

In the test mode, the trimming means operates the serial data of the serial interface circuit, and outputs a control signal of conduction / non-conduction to a selection circuit from a test signal as a simulated fuse fusing signal, thereby setting an optimum trimming state. An optimal trimming detecting means for testing and detecting;
In the fusing mode, there may be provided fusing command means for manipulating the serial data, instructing the fusing required fuse detected by the optimum trimming detecting means among the fuses, and fusing the relevant fuse.

Further, the trimming means may include fuse blowout determining means for operating the serial data in the blowout determination mode and determining whether or not the fuse at the corresponding location has blown out by the blowout instruction means. . Further, the trimming means includes a re-trimming prevention circuit, and after confirming that the fuse blowing determination means has reliably blown the fuse at the corresponding location, operates the serial data and blows the fuse of the re-trimming prevention circuit to prevent re-trimming. Means.

With this configuration, the trimming adjustment of the semiconductor device is performed by transmitting various data of the test signal, the fusing command, the confirmation signal, and the fusing command for preventing re-trimming to the serial interface circuit of the semiconductor device, and performing the trimming state by the simulation test signal. Is changed to detect the optimum trimming state of the analog amount inside the semiconductor device, and the fusing command controls the fusing and non-fusing of the fuse corresponding to the detected optimum trimming state to fix the optimum trimming state, and the confirmation signal signal After confirming that the fusing / non-fusing control of the fuse is performed reliably, and after confirming the fusing / non-fusing control, a re-trimming prevention fusing command prohibits re-trimming from entering the trimming state again. The fuse of the prevention circuit is blown to prevent intrusion into the re-trimming state.
The optimal trimming state can be fixed.

Further, the serial interface circuit includes a shift register for converting serial data into parallel data, and, among the parallel data of the shift register, a write area for remaining data by a control data written in a predetermined bit area. A first logic circuit to be defined, and at least a trimming latch circuit that latches remaining data of parallel data in a write area specified by the first logic circuit output can be provided.

The first logic circuit outputs the control output only when the control data written in the predetermined bit area specifies the trimming latch circuit and the fuse of the retrimming prevention circuit is not blown. There is a second logic circuit for the trimming circuit to be output, and the trimming latch circuit can take the corresponding data out of the serial data transmitted by the output of the second logic circuit into the trimming latch circuit.

With this configuration, after the final trimming adjustment is completed, even if a pulse signal in any mode invades the product, it can be prevented from entering the re-trimming mode. Further, the trimming state storage circuit has a number of state storage circuits in a binary system representing the number of switch elements connected to each node of the resistance network, and each state storage circuit includes a fuse connected to a power supply and a fuse connected to a power supply. A first switch connected in series with the fuse and connected between the power supply 0V to control the fusing of the fuse, a second switch connected from the node A of the fuse and the first switch to the power supply 0V via a resistor, and The first NAND element for controlling the second switch by taking the NAND of the second switch and the node B of the resistor and the confirmation signal from the serial interface circuit, and the test signal from the serial interface circuit NOT operation is performed, and this NOT signal is compared with the blown / non-blown signal of the relevant fuse from node B.
A second NAND element for taking NAND, and an output of the second NAND element and a NOT signal of the output can be output as a control signal to the selection circuit.

With this configuration, the trimming state storage circuit selectively turns on the switch element connected to each node of the resistance network by the blown fuse information or the simulated fuse blown signal represented in a binary system. Detect the optimal trimming state in the test mode, blow the relevant fuse that needs to be blown in the fusing mode, and store and retain the optimal trimming state by detecting that the fuse at the corresponding location has been blown reliably in the fusing determination mode. Can be.

Further, the selection circuit (5A) includes a switch element connected to each node of the resistance network, and a switch element forming a decoder circuit using the same element as the switch element. , The output of the preceding switch element is connected as a set of two and output to the next stage through the switch element, and the output of the last stage is connected as a set of two switch element outputs to be a trimming selection output, H and L signals of the same bit of the control signal can be connected to a pair of switch elements at the same stage.

With this configuration, a decoder circuit can be formed using the same switch element, and a node output of the resistor network selected by the control signal of the trimming state storage circuit can be extracted as a trimming output. Further, the selection circuit (5B) includes a switch element connected to each node of the resistance network, and a third logic circuit for decoding a control signal of the trimming state storage circuit, and outputs the output of the third logic circuit. The switching elements can be individually connected.

With this configuration, the control signal of the trimming state storage circuit can be directly decoded by the third logic circuit to perform ON / OFF control of the switch element, and the output of the node of the selected resistor network can be output by one. It can be detected by the ON resistance of the switch element. The selection circuit (5D) includes a switch element connected to each node of the resistance network, fourth and fifth logic circuits for dividing and decoding a control signal of the trimming state storage circuit, and a fifth logic circuit. And a selection switch element to be selectively controlled. The switch elements are grouped for each output number of the fourth logic circuit, and selection of each node in the group is controlled by an output of the fourth logic circuit. The selection can be controlled by the output of the fifth logic circuit.

With this configuration, this selection circuit (5D)
A node output of the resistor network selected by the control signal of the trimming state storage circuit can be extracted as a trimming output. In particular, the number of control signal wires on the selection circuit (5D) depends on the selection circuit (5B)
On the other hand, since the grouped wirings can be wired in a triangular manner, the number of wirings can be reduced to the number of wirings equal to or close to the selection circuit (5A), and the node output of the selected resistance network can be reduced by 2%.
It can be detected by the ON resistance of the switch elements.

The second logic circuit which causes the trimming latch circuit to latch the remaining data, converts the specific data in the predetermined bit area out of the parallel data of the shift register to H when the re-trimming prevention circuit does not blow the fuse. A third switch element for inputting a level signal to the AND element of the second logic circuit; and a third switch element for inputting specific data to the AND element by an H level signal by fuse blowing of the retrimming prevention circuit and inputting an L level signal. A common point where the third and fourth switch elements are connected to the inputs of the AND element can be output to the IC terminal.

The second logic circuit which causes the trimming latch circuit to latch the remaining data is used to transfer specific data in a predetermined bit area from the parallel data of the shift register to H when the fuse is not blown by the retrimming prevention circuit. A third switch element for inputting a level signal to the AND element of the second logic circuit; and a third switch element for inputting specific data to the AND element by an H level signal by fuse blowing of the retrimming prevention circuit and inputting an L level signal. It is possible to provide a means for reading and writing the parallel data D11 at the common point where the inputs of the third and fourth switch elements and the AND elements are connected, and read the parallel data.

With this configuration, by outputting this common point to the IC terminal and reading the signal level of this terminal, it is possible to confirm the presence or absence of trimming adjustment of the trimming state storage circuit. Further, the trimming method for a semiconductor device includes a test mode step of inputting a test signal, outputting a conduction / non-conduction control signal to a selection circuit from a test signal as a simulated fuse fusing signal, and detecting an optimal trimming state. A fusing command is input, and among the above fuses, a fusing mode step of instructing a fusing required fuse corresponding to the optimal trimming state detected in the test mode and fusing the corresponding fuse, and a confirmation signal are transmitted. Input, determine whether or not the fuse at the corresponding location has been reliably blown by the fusing mode.If the blow of the fuse is uncertain, a step of a fusing determination mode for blowing the corresponding fuse again in the fusing mode; and After confirming that the fuse at the corresponding location has been blown securely in the discrimination mode, input a blow command to prevent re-trimming. A step of re-trimming prevention mode for blowing the fuse trimming prevention circuit may have.

[0023]

FIG. 1 is a main part block circuit diagram for explaining a semiconductor device according to one embodiment of the present invention and a trimming method thereof, FIG. 2 is a block circuit diagram of a semiconductor device according to another embodiment, and FIG. FIG. 4 is a block circuit diagram of a semiconductor device according to another embodiment, FIG. 4 is a circuit diagram of a trimming state storage circuit,
5 is a block diagram illustrating the serial interface circuit and its operation, FIG. 6 is a circuit diagram of the selection circuit illustrated in FIG. 1, FIG. 7 is a circuit diagram of the selection circuit illustrated in FIG. 2, and FIG. It is a circuit diagram of a selection circuit illustrated.

FIG. 1 shows a semiconductor device 1 according to the present invention.
In the semiconductor device 1 having the trimming means 2 in the resistance network 6, the trimming means 2 includes the resistance network 6,
The resistor circuit (r1 to rm) has switch elements (s1 to sm-1) connected to each node of the network 6, and the switch elements (s1 to sm-1)
a selection circuit 5 for selecting the output of the designated node pi in the resistance network 6 by controlling the conduction / non-conduction of the sm-1), a plurality of fuses F (F1 to F4) and this fuse F A first switch SW (SW1 to SW4) for controlling fusing; a trimming state storage circuit 4 for outputting control signals d1 to d4 and dB1 to dB4 to a selecting circuit 5 when the fuse F is blown or not; (DATA)
1B, and various signals ((F1-F4), FC, (T1-T4) for controlling the operation of the trimming state storage circuit 4 from the serial data 1B.
4), a serial interface circuit 3 forming CH),
It is comprised including.

In the test mode, the trimming means 2 outputs the serial data (T1 to T1) of the serial interface circuit 2.
T4) to control the conduction / non-conduction of the test signal as the simulated fuse fusing signal (T1 to T4) to the selection circuit 5.
Outputs d1 to d4 and dB1 to dB4 to test and detect the optimal trimming state.Optimal trimming detection means for operating the serial data (F1 to F4) in the fusing mode and detecting fuses F1 to F4. A fusing command means for outputting a fusing command (H level signal) to the fusing required fuse detected by the means and fusing the corresponding fuse.

Further, the trimming means 2 includes a fuse blowing determining means for operating the serial data (CH) in the blowing determining mode and determining whether or not the fuse at the corresponding location has blown reliably by the blowing command means. Prepare. Further, the trimming means 2 is provided with a re-trimming prevention circuit 4C. After confirming that the fuse blowing determination means has surely blown the fuse at the corresponding portion, the serial data (FC) is operated and the fuse of the re-trimming prevention circuit 4C is operated. Means for preventing re-trimming for fusing,
Is provided.

With this configuration, when trimming adjustment is performed at the final stage of the product of the semiconductor device 1, a test signal (T1 to T4), a fusing command (F1 to F4), a confirmation signal (CH) are sent to the serial interface circuit 3 of the semiconductor device 1. A trimming jig (not shown) for transmitting various data 1B of the fusing command (FC) for preventing re-trimming, for example, a personal computer, and a measuring means (not shown) for detecting an optimum trimming state are set, and the following trimming is performed. Can be adjusted.

In the test mode step, the trimming jig operates the serial data (test signals) (T1 to T4) to the H or L level to simulate the fuse fusing signals (T1 to T4).
The control signal d1 to d4 and dB1 to dB4 for conducting / non-conducting are output from the test signal to the selection circuit 5 to detect the optimal trimming state. In the fusing mode step, serial data (fusing command) (F1 to F4 ) Is operated to the H or L level, and among the fuses F1 to F4, the corresponding required fuse detected by the optimum trimming detecting means is instructed to be blown (H level) to blow the corresponding fuse. In the step of the discrimination mode, the serial data (confirmation signal) (CH) is operated to the H level, and it is determined whether or not the fuse at the corresponding location has been reliably blown by the fusing command means. The corresponding fuse is blown again in the blowing mode, and in the step of the re-trimming prevention mode, after confirming that the fuse blowing determination means has blown the fuse at the corresponding position without fail, the serial data (re-trimming) is performed. Fusing Directive for Prevention of Thrust) (FC)
At the H level to blow the fuse of the retrimming prevention circuit 4C.

[0029]

(Embodiment 1) A semiconductor device according to the present invention will be supplementarily described. In FIG. 1, a semiconductor device 1 includes a semiconductor circuit 1A for handling an analog amount in an internal circuit, and a trimming unit 2 for finely adjusting (trimming) the analog amount.

As an application example of such a semiconductor device 1, there is, for example, a charge control circuit of a lithium ion battery mounted on a portable device. For such a purpose, for example, a trimming circuit is inserted between an input signal and a feedback signal in the circuit configuration of the bandgap reference voltage and the operational amplifier, and fine adjustment is performed to secure precise accuracy. Semiconductor circuit shown
As 1A, for example, a bandgap reference voltage is input to the (+) input terminal of the operational amplifier, an output signal of the operational amplifier is taken out from a terminal 1c, and resistors R1, R2,
The voltage is divided by R3, and a trimming resistor network (r1 to rm) consisting of a series circuit is connected to both ends of the resistor R2, and each node (p1
To pm-1), and control signals (d1 to d4) and (d1) of the trimming state storage circuit 4 by selecting and decoding the switch elements (s1 to sm-1).
B1 to dB4), the H level output switch element is turned on, whereby the control signal (d1 to d4), the divided potential of the node px selected by (dB1 to dB4) is selected, and the semiconductor circuit 1A And here, it is fed back to the (-) input terminal of the operational amplifier to obtain a predetermined reference output. (Embodiment 2) Next, a serial interface circuit 3 as an embodiment of the present invention will be described with reference to FIG.

In FIG. 1, the serial interface circuit 3 uses a trimming jig (not shown) to trim data (DATA) 1B when trimming the semiconductor device 1.
And clock signal (CLK) 1C and strobe signal (STB) 1D
Is transmitted, and the semiconductor device 1 is incorporated in an electronic device, for example, a portable telephone. In such a case, the data (DATA)
And clock signal (CLK) 1C and strobe signal (STB) 1D
Send The operation of this data will be described in detail with reference to FIG. 5. The control data written to a part of the data (DATA) 1B causes the remaining data to be written to the latch circuits Q32, Q33, and Q34, The data can execute a predetermined operation in the semiconductor circuit 1A as the address data adr1 and adr2. For example, by setting the H level to the ON, OFF, INC, and DEC bit positions of the latch circuit Q33 in FIG. 5, the power switch is turned ON when it is ON, the power switch is turned OFF when it is OFF, and the volume is increased when INC and DEC are used. A reduction can be set.

In the embodiment of the present invention, the address data adr3 of the latch circuit Q34 is used exclusively for trimming adjustment. In FIG. 5, a serial interface circuit 3 includes a shift register Q31 for converting serial data (DATA) 1B into parallel data (D1 to D16),
Of the parallel data (D1 to D16) of this shift register Q31,
A first logic circuit (Q35 to Q39) that defines a write area (latch circuits Q32, Q33, and Q34 in the illustrated example) of remaining data (D1 to D11) by control data written to a predetermined bit area (D12 to D16) , Q35T to Q37T) and the write area specified by the first logic circuit output (for example, Q32 when (D12 to D16) is 11111, Q33 when 01111, and Q34 when 10111)
Remaining data (D1 to D11) of parallel data in Q32, Q33, Q34
In the illustrated example of latching the latches Q32 and Q33, a trimming latch circuit Q34 is provided.

Here, the first logic circuits (Q35 to Q39, Q35T
QQ37T), the control data (10111) written in the predetermined bit area (D12 to D16) designates the trimming latch circuit Q34, and the fuse F of the retrimming prevention circuit 4C is not blown. A second logic circuit (Q39, Q35T to Q37T) for a trimming circuit which outputs a control output only when there is a certain logic;
The serial data transmitted by the outputs of (Q39, Q35T to Q37T) is configured so that the corresponding data can be taken into the trimming latch circuit Q34.

Specifically, the signal of D12 is applied to the switches SW3 and SW
When the fuse F of the re-trimming prevention circuit 4C is not blown, the signal COMP is at H level and the switch SW3 is turned on.When the fuse F of the re-trimming prevention circuit 4C is blown, the signal COMPB is at H level. The switch SW4 is turned on, and the switch SW3 is turned off when the signal COMP is at the L level. As a result, after the fuse F of the re-trimming prevention circuit 4C is blown, data cannot be written to the trimming latch circuit Q34. That is, even if the pulse signal in any mode enters the product after the final trimming adjustment is completed, it is possible to prevent the re-trimming mode from being entered.

As described above, while the fuse F of the retrimming prevention circuit 4C is not blown, the second logic circuit (Q3
9, Q35T to Q37T), the data allocated to the trimming latch circuit Q34 can be written. In the embodiment of the present invention, when trimming adjustment is performed at the final stage of the product of the semiconductor device 1, a test signal (T1 to T4) and a fusing command (F1 to F4) are sent to the serial interface circuit 3 of the semiconductor device 1.
These operations can be executed by inputting the H level to the position of the confirmation signal (CH) and the re-trimming prevention fusing command (FC). (Embodiment 3) Next, a trimming state storage circuit 4 as an embodiment of the present invention will be described with reference to FIG. FIG. 4A shows trimming state storage circuits 41 to 44 for storing the optimum trimming state in a fuse. In this embodiment, 4-bit data is used to trim the optimum position of 16 nodes. (B) shows a re-trimming prevention circuit 4C for preventing re-trimming after confirming that the fuse blowing determination means has reliably blown the fuse at the corresponding location.

In FIG. 4A, a trimming state storage circuit (41-44) converts the number of switch elements (m-1) connected to each node (p1-pm-1) of a resistor network into a binary number. Since the number expressed by the method is 16 in the embodiment, four state storage circuits 41 are used.
~ 44. Hereinafter, the trimming state storage circuit 41 will be described as a representative, and the other trimming state storage circuits will also be described in parentheses (42 to 44). Trimming state storage circuit 41, (42 to 44)
Is the fuse F connected to the power supply VCC and this fuse F
Connected in series with F and connected between 0V (GND)
0 F (GN) from the first switch SW1 that controls the fusing of the fuse F and the node A of the fuse F and the first switch SW1 via the resistor R5.
D) a second switch SW2 connected between the second switch SW2, the node B of the resistor R5, and the confirmation signal (CH) of the address data adr3 from the serial interface circuit 3.
First NAND element Q4 that takes NAND and controls second switch SW2
The NOT element Q1 performs a NOT operation on the test signals T1, (T2 to T4) of the address data adr3 from the serial interface circuit 3, and the NOT signal and the melting of the corresponding fuse from the node B
A second NAND element Q2 that takes NAND with the non-fusing signal,
The output of the second NAND element Q2 and the NOT signal of this output are used as control signals d1B, (d2B to d4B), d1, (d2 to d
4) can be output as

With such a configuration, the trimming state storage circuits 41, (42 to 44) are provided with the blown fuse information (blown / non-blown) or the simulated fuse blow signals (H of T1 to T4) expressed in a binary system. (L level), the switch elements connected to the respective nodes p1 to pm-1 of the resistance network 6 are selectively turned on, the optimum trimming state is detected in the test mode, and the corresponding required fuse is blown in the fusing mode. In the fusing determination mode, it is possible to store and retain the optimum trimming state by detecting that the fuse at the corresponding location has been reliably blown.

Next, each operation mode of the trimming state storage circuit 41 will be described. First, the case where the fuse F is not blown will be described. Here, it is assumed that the ON resistance of the second switch SW2 is larger than the resistance value of the sum of the fuse F and the resistance R5. Under this condition, since the ON resistance of the second switch SW2 is larger than the resistance value of the sum of the fuse F and the resistor R5, the potential of the node B is high for the second NAND element Q2 regardless of the operation of the first NAND element Q4. It becomes H level.

In the test mode step, the simulated fuse fusing signal T1 / H is changed to serial data (T1 is set to H level).
The level is given to NOT element Q1. Since the output of the NOT element Q1 is at the L level, regardless of the state of the node B, the NAND element Q2
Of the trimming state storage circuit 41, d1B becomes H level and d1 becomes L level. When serial data (T1 is at L level), NA
The inputs of the ND element Q2 are both at H level, so that the output of the trimming state storage circuit 41 is such that d1B is at L level and d1B is at L level.
Becomes H level. Therefore, by setting the H / L level for each of the serial data (T1 to T4), an arbitrary switch element connected to each of the nodes p1 to pm-1 of the resistance network 6 can be selectively made conductive. Can be. Therefore, control signals (d1B to d4B) and (d1 to d4) for conducting / non-conducting are output from the test signals (T1 to T4) to the selection circuit 5 to detect the potential of any node px of the resistor network 6. By returning the signal to the terminal 1d of the semiconductor circuit 1A, the optimum trimming state px predetermined as the semiconductor circuit 1A can be detected.

Next, in the step of the fusing mode, the optimum trimming state px detected in the above-described test mode is blown by the fuse F of the trimming state storage circuits 41 to 44.
This optimum trimming state px is fixed and stored. According to this method, for the serial data (fusing command: F1 to F4), the portion corresponding to the H level portion of the test signal (T1 to T4) corresponding to the optimum trimming state px in the previous test mode is set to the H level. You can do this by doing That is, the serial data (the corresponding position of the fusing command: F1 to F4 is set to the H level), and the corresponding portion of the fuse blowing command F1 to F4 of the trimming state storage circuits 41 to 44 is set to the H level. As a result, the first switch SW1 of the corresponding portion at the H level becomes conductive, and the connection between the power supply VCC and 0V (GND) is made between the fuse F and the first switch SW1.
The current divided by the ON resistance of SW1 flows, generates heat, and can blow the fuse at the corresponding location. After the fuse at the corresponding location is blown, the test signals (T1 to T4) are set to L level, and the first switch SW1 is turned off.

Next, in the step of the fusing determination mode, the serial data (T1 to T4) is set to the L level, the serial data (confirmation signal CH) is manipulated, and the fusing command means surely blows the corresponding portion. It is determined whether or not. The confirmation signal CH is a power-on reset signal, and is a signal that outputs an L level after a circuit power is input, and changes to an H level with a delay of several hundred μsec.

That is, when the fuse is not blown,
The potential of node A indicates a potential close to VCC, and the confirmation signal initial CH
Is at the L level, the output of the NAND element Q4 is at the H level,
The switch SW2 is turned on. Since the ON resistance is larger than the sum of the resistance of the fuse F and the resistance R5, the potential of the node B becomes H level. Subsequently, the confirmation signal CH changes to H level, the output of the NAND element Q4 changes to L level, and the second switch SW
Even if 2 is OFF, the node B is at the H level and the serial data (T1 to T4) is at the L level, so the output of the NOT element Q1 is at the H level, and the second NAND element Q2 is at the L level of the node B. And d1 (d2, d3, d4) becomes H level, and dB1 (dB2, dB
3, dB4) is at the L level.

When the fuse is blown, the potential at the node A is floating, the initial confirmation signal CH is at the L level, the output of the NAND element Q4 is at the H level, and the second switch SW2 is turned on. The potential at the node B becomes L level. Subsequently, even if the confirmation signal CH changes to the H level, the output of the NAND element Q4 is at the H level, the second switch SW2 continues to be ON, the node B is at the L level, and the serial data (T1 to
T4) is at the L level, the output of the NOT element Q1 is at the H level, the second NAND element Q2 is at the H level at the node B,
d1 (d2, d3, d4) becomes L level, and dB1 (dB2, dB3, dB4) becomes H level.
Level.

That is, when the fuse is not blown, the current of the power supply VCC does not increase and the output d1 (d2, d3, d4) is at the H level because the second switch SW2 is OFF. Fuse is not blown, and when the fuse is blown, the second switch SW
2 is ON, but since node A is floating,
No increase in power supply VCC current and output d1 (d2, d3, d4)
Is L level, it can be confirmed that the corresponding fuse is blown.

In the step of the retrimming prevention mode, the following processing is performed after confirming that the above-mentioned fuse blowing determination means has blown the fuse at the corresponding portion without fail.
In FIG. 4B, the re-trimming prevention circuit 4C is different from the trimming state storage circuits 41 to 44 in that test signals (T1 to T4) for detecting an optimum trimming state are unnecessary. . Therefore, the NOT element Q1 is deleted and the second
NAND element Q2 is replaced with NOT element Q5, and the fusing command (F1
F4) becomes the fusing command FC.

In this fusing operation, the serial data FC is operated to set the fusing command FC to the H level. As a result, the fuse
Fusing current flows from the power supply VCC to F, and the fuse F can be blown. Whether or not the fuse F of the re-trimming prevention circuit 4C has been reliably blown can be confirmed in the same manner as the trimming state storage circuits 41 to 44. The output of the retrimming prevention circuit 4C after the fuse F has been blown is such that the output comp is at the L level and the output compB is at the H level since the node B is at the L level. The outputs comp and compB of the re-trimming prevention circuit 4C are connected to the second logic circuit (Q39, Q3
5T to Q37T), when the fuse F of the re-trimming prevention circuit 4C is not blown, comp is at the H level and compB is at the L level.
3 turns ON, and switch element SW4 turns OFF. Accordingly, the control signal (10111) for latching the data of adr3 of the trimming latch circuit Q34 can be used because the data of the serial data D12 is input to the logic element Q37 via the switch element SW3 to form a decoder circuit. By manipulating the serial data, the trimming state storage circuit 4 can be controlled.

On the other hand, the fuse of the re-trimming prevention circuit 4C
After blowing F, the output comp becomes L level and compB becomes H level.
Since the level is at the level, the switch element SW3 is turned off and the switch element SW4 is turned on. That is, the data of the serial data D12 is blocked by the switching element SW3, and is always low by the switching element SW4.
Locked to level, control signal (0xxxx) (where x is D1
3 to D16) and does not constitute the control signal (10111) that causes the latch circuit Q34 to latch data. That is, once the fuse F of the re-trimming prevention circuit 4C has been blown after the trimming adjustment, the re-trimming state can be prevented even if any serial data is input.

A second logic circuit (Q39, Q3) for causing the trimming latch circuit Q34 to latch the remaining data (D1 to D11).
5T to Q37T) are the parallel data (D1 to
D16), the specific data (D1
2) is connected to the third switch element SW3 which is input to the AND element Q37T of the second logic circuit by the H level signal without the fuse F of the re-trimming prevention circuit 4C, and the H level signal by the fuse F blowing of the re-trimming prevention circuit 4C. AND specific data (D12)
A fourth switch element SW4 for blocking the input to the element Q37T and inputting an L level signal; and a resistor R6.
The common point (BLK) where the inputs of the fourth switch elements SW3 and SW4 and the input of the AND element Q37T are connected can be output to the IC terminal.

A second logic circuit (Q39, Q3) for causing the trimming latch circuit Q34 to latch the remaining data (D1 to D11).
5T to Q37T) are the parallel data (D1 to
D16), the specific data (D1
2) is connected to the third switch element SW3 which is input to the AND element Q37T of the second logic circuit by the H level signal without the fuse F of the re-trimming prevention circuit 4C, and the H level signal by the fuse F blowing of the re-trimming prevention circuit 4C. AND specific data (D12)
A fourth switch element SW4 that blocks the input to the element Q37T and inputs an L level signal, a resistor R6, and a common point where the third and fourth switch elements SW3 and SW4 and the input of the AND element Q37T are connected ( BLK) to the parallel data D11, and means for reading the parallel data.

With this configuration, by outputting this common point to the IC terminal and reading the signal level of this terminal, it is possible to confirm the presence or absence of trimming adjustment of the trimming state storage circuit. (Embodiment 4) In FIGS. 1 and 6, the selection circuit 5A
A switch element (s1 to s16) connected to each node (p1 to p16) of the resistance network 6 and a switch element (s17 to form a decoder circuit using the same element as the switch element (s1 to s16)
S30), and the decoder circuit connects the output of the preceding switch element as a set of two and outputs it to the next stage via the switch element, and the final stage outputs two outputs of the switch elements s29 and s30. H and L signals of the same bit of the control signals d1 to d4 and d1B to d4B of the trimming state storage circuit 4 are connected as one set to be a trimming selection output 1d, and a pair of switch elements in the same stage, for example, The H and L signals of (d1, d1B) are the switch elements (s
1, s2), (s3, s4), ... (s15, s16).

With this configuration, the same switch elements s1 to s1
By using s30 to form a decoder circuit, the output of the node px of the resistor network 6 selected by the control signals d1 to d4 and d1B to d4B of the trimming state storage circuit 4 can be extracted as a trimming output. (Embodiment 5) Referring to FIGS.
5B is a switch element (s1 to s16) connected to each node (p1 to p16) of the resistance network 6, and a third logic circuit for decoding control signals d1 to d4 and d1B to d4B of the trimming state storage circuit 4.
5C, and outputs the output of the third logic circuit 5C to a switch element.
(s1 to s16) can be individually connected.

With this configuration, the third logic circuit 5C can directly decode the control signals d1 to d4 and d1B to d4B of the trimming state storage circuit 4 to perform ON / OFF control of the switch elements (s1 to s16). The output of the node px of the selected resistor network 6 can be detected by the ON resistance of one switch element sx. (Embodiment 6) Referring to FIGS.
5D is a circuit for dividing and decoding the switch elements (s1 to s16) connected to the respective nodes (p1 to p16) of the resistance network 6 and the control signals d1 to d4 and d1B to d4B of the trimming state storage circuit 4. 4
A logic circuit 5E, a fifth logic circuit 5F, and a selection switch element (s17 to s20) selectively controlled by the fifth logic circuit 5F. The switch elements s1 to s16 are connected to the number of outputs of the fourth logic circuit 5E (4 Each) (s1 ~ s4), (s5 ~ s8), (s9 ~ s12), (s13 ~ s1
6), the selection of each node in the group can be controlled by the output of the fourth logic circuit 5E, and the selection for each group unit can be controlled by the output of the fifth logic circuit 5F.

With this configuration, the selection circuit 5D can take out the output of the node px of the resistor network 6 selected by the control signals d1 to d4 and d1B to d4B of the trimming state storage circuit 4 as the trimming output 1d. . In particular, the number of control signal wires on the selection circuit 5D depends on each switch element (s1 to s1
For the selection circuit (5B) that is individually wired to 6), the grouped wiring can be wired in a pot-like manner, so that the number of wirings equivalent to or close to the selection circuit 5A can be reduced and selected. The output of the node px of the resistance network can be detected by the ON resistance of the two switch elements.

In the trimming adjustment of the semiconductor device according to the present invention, a switch element is connected to each node of the resistive network, and conduction of the switch element can be controlled to select a designated node output. That is, the trimming adjustment does not perform the trimming adjustment by short-circuiting the resistance elements constituting the resistance network, but selects the output of the designated node. Therefore, the trimming adjustment changes the total resistance value of the resistance network. Instead, a potentiometer that can select any node output can be configured. That is, since the total resistance value of the resistance network is constant, it is possible to configure so that the current distribution of the resistance network does not change by trimming adjustment.
The present invention can be applied to more general trimming adjustment for applications requiring high precision.

[0055]

According to the present invention, the fuse of the trimming state storage circuit is blown and controlled by inputting the serial data, and the conduction of the switch element connected to each node of the resistance network by blowing and non-blown of the fuse is controlled. -Trimming adjustment is enabled by selecting a designated node output by performing non-conduction control, and after completion of trimming adjustment, the fuse of the re-trimming prevention circuit is blown to prevent subsequent re-trimming.

As a result, the adjustment of the integrated circuit (IC) at the final stage of the product becomes possible, and the fuse for trimming does not short-circuit the resistor for trimming. It has accurate and stable trimming adjustment means to confirm that it has been adjusted to the optimum trimming state, and after the final trimming adjustment is completed, will not enter the re-trimming mode even if a pulse signal in any mode enters the product And a method for trimming the same can be provided.

[Brief description of the drawings]

FIG. 1 is a main part block circuit diagram illustrating a semiconductor device and a trimming method thereof according to an embodiment of the present invention;

FIG. 2 is a block circuit diagram of a semiconductor device according to another embodiment.

FIG. 3 is a block circuit diagram of a semiconductor device according to another embodiment.

FIG. 4 is a circuit diagram of a trimming state storage circuit.

FIG. 5 is a block circuit diagram illustrating a serial interface circuit and its operation;

FIG. 6 is a circuit diagram of a selection circuit shown in FIG. 1;

FIG. 7 is a circuit diagram of a selection circuit shown in FIG. 2;

FIG. 8 is a circuit diagram of a selection circuit shown in FIG. 3;

FIG. 9 is a block circuit diagram of a conventional semiconductor device.

[Explanation of symbols]

 1,110 semiconductor device 1A semiconductor circuit 1B data 1C clock 1D strobe signal 1a-1d terminal 2 trimming means 3 serial interface circuit 4 trimming state storage circuit 41-44 trimming state storage circuit 4C re-trimming prevention circuit 5 selection circuit 5A decoder circuit 5B Selection circuit 5C Third logic circuit 5D Selection circuit 5E Fourth logic circuit 5F Fifth logic circuit 6 Resistor network adr1 to adr3 Address data comp, compB Adjustment completion signals d1 to d4, d1B to d4B Control signals R1 to R6, r1 to rm resistance s1 to s30, sm-1, SW3, SW4 switch element SW1 first switch SW2 second switch p1 to pm-1, p16 node px optimal trimming state nodes A, B, C nodes D1 to D16 parallel data F fuse F1 ~ F4 Fusing command FC Fusing command for re-trimming prevention T1 ~ T4 Test signal CH confirmation signal Q1, Q3, Q5 NOT element Q2, Q4 NAND element Q31 Shift register Q32, Q33 Latch circuit Q34 Trimming latch circuit Q 35 to Q38 First logic circuit Q35T to Q37T, Q39 Second logic circuit Ra to Rd Resistance network 105,106,107 Fuse 115,116,117 Switching means 118 Trimming jig 118b Microprocessor 118c P / S converter 114a S / P converter 114 Register 113 Decoder c Fuse current supply line VCC Power supply voltage GND Power supply 0V

Claims (13)

[Claims] In a semiconductor device having a trimming means in a resistance network, the trimming means has a resistance network and a switch element connected to each node of the resistance network. A selection circuit that controls conduction and selects an output of a designated node in the resistance network; a plurality of fuses; and a first switch that controls fusing of the fuses.
A trimming state storage circuit that outputs a control signal to the selection circuit when a fuse is blown or not blown, and a serial interface circuit that receives serial data and forms various signals that control the operation of the trimming state storage circuit from the serial data A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein the trimming means operates the serial data of the serial interface circuit in the test mode, and switches the conduction / non-conduction to the selection circuit from the test signal as the simulated fuse blowing signal. An optimal trimming detecting means for outputting a control signal to test and detect an optimal trimming state; and operating the serial data in a fusing mode, and fusing the required fuse detected by the optimal trimming detecting means among the fuses. And a fusing instruction means for instructing the fuse to blow. 3. The semiconductor device according to claim 1, wherein the trimming means operates the serial data in the fusing determination mode, and determines whether or not the fuse at the corresponding location has been reliably blown by the fusing command means. Fuse blowing determining means for determining
A semiconductor device, comprising: 4. The semiconductor device according to claim 1, wherein the trimming means includes a re-trimming prevention circuit, and the fuse blowing determination means surely blows the fuse at the corresponding location. After confirming, re-trimming prevention means for operating the serial data and blowing the fuse of the re-trimming prevention circuit;
A semiconductor device, comprising: 5. The semiconductor device according to claim 1, wherein said serial interface circuit comprises: a shift register for converting serial data into parallel data; A first logic circuit for determining a write area for remaining data by control data written to a predetermined bit area, and at least latching the remaining data of the parallel data in the write area specified by the output of the first logic circuit And a trimming latch circuit. 6. The semiconductor device according to claim 5, wherein the first logic circuit specifies the trimming latch circuit with the control data written in the predetermined bit area, and the fuse of the re-trimming prevention circuit. Has a second logic circuit for a trimming circuit that outputs a control output only when the signal is not blown, and the trimming latch circuit trims the data out of the serial data transmitted by the output of the second logic circuit. A semiconductor device, wherein the semiconductor device is incorporated in a latch circuit for use. 7. The semiconductor device according to claim 1, wherein the trimming state storage circuit represents the number of switch elements connected to each node of the resistance network in a binary system. A plurality of state storage circuits, each of the state storage circuits including a fuse connected to a power supply, a first switch connected in series with the fuse and connected between a power supply of 0 V to control the fusing of the fuse, Second connected from switch node A to power supply 0V via resistor
A first NAND element for controlling a second switch by taking a logical AND (hereinafter abbreviated as NAND) of the switch, the second switch, a node B of the resistor and a confirmation signal from the serial interface circuit, and a serial interface circuit And a second NAND element that performs a NOT operation on the test signal from the second NAND element and NANDs the NOT signal with the fusing / non-fusing signal of the fuse from the node B. The output of the second NAND element and the NOT signal of this output are provided. And outputting the control signal as a control signal to a selection circuit. 8. The semiconductor device according to claim 1, wherein the selection circuit uses a switch element connected to each node of the resistance network and the same element as the switch element. And a switch element that constitutes a decoder circuit. The decoder circuit connects the output of the preceding switch element as a set of two and outputs it to the next stage via the switch element. H, L signals of the same bit of the control signal of the trimming state storage circuit are connected to a pair of switch elements in the same stage, respectively. Semiconductor device. 9. The semiconductor device according to claim 1, wherein the selection circuit includes a switch element connected to each node of the resistor network and a control signal for the trimming state storage circuit. A third logic circuit for decoding, and an output of the third logic circuit is individually connected to the switch element. 10. The semiconductor device according to claim 1, wherein the selection circuit includes a switch element connected to each node of the resistor network and a control signal for the trimming state storage circuit. And fourth and fifth logic circuits for dividing and decoding, and a selection switch element selectively controlled by the fifth logic circuit, wherein the switch elements are grouped according to the number of outputs of the fourth logic circuit. A semiconductor device, wherein selection of each node is controlled by an output of a fourth logic circuit, and selection of each group is controlled by an output of a fifth logic circuit. 11. The semiconductor device according to claim 6, wherein the second logic circuit that causes the trimming latch circuit to latch the remaining data includes, among parallel data of the shift register, specific data of a predetermined bit area. A third switch element which is input to the AND element of the second logic circuit by an H level signal when the fuse of the re-trimming prevention circuit is not blown, and the specific data is input to the AND element by an H level signal when the fuse of the re-trimming prevention circuit is blown; A fourth switch element for inputting an L level signal while blocking the input of the third and fourth switch elements, and outputting a common point where the inputs of the third and fourth switch elements and the AND element are connected to an IC terminal; A semiconductor device characterized by the above-mentioned. 12. The semiconductor device according to claim 6, wherein the second logic circuit that causes the trimming latch circuit to latch the remaining data includes, among parallel data of the shift register, specific data of a predetermined bit area. A third switch element which is input to the AND element of the second logic circuit by an H level signal when the fuse of the re-trimming prevention circuit is not blown, and the specific data is input to the AND element by an H level signal when the fuse of the re-trimming prevention circuit is blown; , A fourth switch element for inputting an L level signal while blocking the input of the
Means for enabling a common point where the input of the fourth switch element and the input of the AND element are connected to be readable and writable in the parallel data D11, and for reading the parallel data. 13. A method for trimming a semiconductor device using the semiconductor device according to claim 1, wherein a test signal is input, and a selection circuit is selected from a test signal as a simulated fuse fusing signal. A test mode step of outputting a conduction / non-conduction control signal to detect an optimal trimming state, and a fusing command being input, and a fuse required for the fuse corresponding to the optimal trimming state detected in the test mode. A step of a fusing mode in which a fuse is instructed to blow and a corresponding fuse is blown, and a confirmation signal is input, and it is determined whether or not the fuse at the corresponding location has blown reliably by the fusing mode. If uncertain, the step of the fusing determination mode in which the corresponding fuse is blown again in the fusing mode; After confirming that the fuse at the location has been reliably blown, inputting a blow command for preventing re-trimming, and blowing the fuse of the re-trimming prevention circuit in a re-trimming prevention mode. .