JP2002076009A - Pin diode and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PIN diode, which can make a capacitance small without increasing a series resistance, or the series resistance small without increasing the capacitance, and to provide its manufacturing method. SOLUTION: For example, a semi-insulative i-layer 2 is formed on an n-type semiconductor substrate 1 by an epitaxial growth process, and a p-type region 3 is formed on the i-layer 2. Then, an insulation region 4 is formed around the p-type region so as to be deeper than the p-type region and not to get to the semiconductor substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PIN diode used for an antenna switch of a cellular phone, particularly a switch element of a high-frequency product, and a method of manufacturing the same. More specifically, a PI in which the junction capacitance is reduced in order to increase the switching speed and the operating resistance is reduced
The present invention relates to an N diode and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, a PIN diode has, for example, a structure as shown in FIG. That is, n ⁺⁺
A semi-insulating i-layer 22 is epitaxially grown on a semiconductor substrate 21 and, for example, ap-type impurity is diffused on the surface of the i-layer to form ap ^{+ -type} region 23. And p on the surface
The side electrode 27 is formed by providing the n-side electrode 28 on the back surface of the semiconductor substrate 21. 29 is an n ⁺ region for a channel stopper.

When a forward voltage is applied to the PIN diode, a current flows and the PIN diode functions as a diode.
The characteristic of this diode is that the semiconductor substrate 21 of the depletion layer 26
Series resistance Rf of the i-layer 22 on the side of the
It has a junction capacitance Ct due to the portion. If the forward series resistance is large, power consumption is increased due to loss during operation, and if the voltage drop due to the resistance is large, the drive voltage must be increased accordingly, and the battery capacity of portable products must be increased, which is preferable. Absent. In addition, the capacitance Ct corresponds to the residual charge when the capacitor is off, and the capacitance Ct is preferably as small as possible to increase the switching speed in the high-frequency circuit.

[0004] The capacitance Ct of the PIN diode is proportional to the area of the depletion layer 26 and inversely proportional to its thickness. on the other hand,
The forward resistance Rf decreases as the area of the depletion layer increases, and is inversely proportional to the area. Therefore, the relationship between the forward series resistance Rf and the capacitance Ct has a trade-off relationship as shown in FIG.

[0005]

As mentioned above, the PIN
There is a trade-off relationship between the forward voltage and the capacitance of the diode, and there is a problem that both cannot be reduced. Particularly, in the actually manufactured PIN diode, the capacitance Ct becomes larger than the theoretical value, and the junction area between the p-layer and the i-layer must be reduced accordingly, and the forward series resistance Rf becomes large.

The present invention has been made to solve such a problem. For example, as shown by a target value in FIG. 7, without reducing the capacitance without increasing the series resistance or without increasing the capacitance. An object of the present invention is to provide a PIN diode capable of reducing series resistance and a method for manufacturing the same.

[0007]

The inventor of the present invention obtained the calculated theoretical value of the PIN diode capacitance and compared it with the actually measured value of an actually manufactured PIN diode. As a result, the calculated value P was obtained as shown in FIG. As a result, it has been found that the capacitance Ct increases with the actually measured value Q. Further, as a result of diligently studying the cause of the increase in the capacity of the PIN diode, FIG.
As shown by Q, the depletion layer Q of the actual PIN diode spreads laterally from the theoretical depletion layer 26 (P), and the depletion layer on the bottom side of the p-type region is formed thin. I found that there is. By forming an insulating region on the side surface of the p-type region to prevent the depletion layer from spreading laterally, the area of the depletion layer is reduced, and the depletion layer on the bottom side is thickened, so that the capacitance is greatly increased. Found that it can be made smaller.

A PIN diode according to the present invention comprises a semiconductor substrate of a first conductivity type, a semi-insulating i-layer provided on the semiconductor substrate, and a second conductivity type region provided in the i-layer. An insulating region is formed around the two-conductivity-type region and deeper than the second-conductivity-type region and formed so as not to reach the semiconductor substrate.

With this structure, there is almost no i-layer on the side of the second conductivity type region and no depletion layer is formed, so that the area of the depletion layer is reduced and the capacitance is reduced. On the other hand, the area of the depletion layer serving as the current path (the area of the junction between the bottom surface of the second conductivity type region and the i-layer) does not change, and the forward resistance does not decrease. Therefore, the forward resistance does not increase.
In addition, the depletion layer on the bottom surface is formed thicker than the depletion layer on the side of the second conductivity type region. Therefore, the capacity is further reduced.

It is more preferable that the insulating region is formed substantially in contact with the second conductivity type region, because a depletion layer on the side of the second conductivity type region can be almost eliminated.

The insulating region may be, for example, an air layer formed by a trench formed substantially perpendicular to a main surface of the second conductive type region in the i-layer or the second conductive type region, or an insulating layer provided in the trench. Can be formed.

The method for manufacturing a PIN diode according to the present invention is as follows.
Growing a semi-insulating i-layer on the first conductivity type semiconductor substrate and introducing a second conductivity type impurity on the surface side of the i-layer to form a second conductivity type region; And etching the second conductivity type region or the i-layer around it so as to be deeper than the second conductivity type region and not to reach the semiconductor substrate.

The breakdown voltage is improved by forming an insulating film on the side wall of the second conductivity type region or the i-layer exposed by the etching, or by burying an insulating material in a groove formed by the etching.

[0014]

Next, a PIN diode of the present invention and a method for manufacturing the same will be described with reference to the drawings. In a PIN diode according to the present invention, a semi-insulating i-layer 2 is epitaxially grown on a first conductivity type (for example, n-type) semiconductor substrate 1 as shown in FIG. The i-layer 2 has a second conductivity type (p-type) region 3 formed therein. And
An insulating region 4 is formed around the p-type region 3 so as to be deeper than the p-type region 3 and not to reach the semiconductor substrate 1.
Reference numeral 6 denotes a depletion layer formed when a voltage is applied to both electrodes.

In the example shown in FIG. 1A, the insulating region 4 is formed by forming a trench 5 on the outer periphery of the p-type region 3 and providing an oxide film on the surface by thermal oxidation or the like.
Is formed. The trench 5 is formed, for example, by forming a mask on the surface of the p-type region 3 and the i-layer 2 using a photoresist or the like and performing physical etching such as reactive ion etching (RIE) to form the semiconductor substrate 1 (p-type). It is formed substantially perpendicular to the surface of the region 3). That is, when the etching is performed by wet etching, the width of the side wall exposed by the etching (when the planar shape of the p-type region 3 is a circle, the diameter thereof) becomes divergent and becomes a curved shape that becomes large on the bottom side, and becomes a curved shape on the bottom side. Although the depletion layer 6 is likely to be formed on the side wall side, according to the physical etching, a recess is formed almost perpendicular to the substrate surface.
This is preferable because the depletion layer 6 is hardly formed on the side wall.

However, even by wet etching,
Even if a depletion layer is formed slightly on the bottom surface side, the area of the depletion layer is much smaller than in the conventional structure, and the capacitance Ct can be reduced.

This trench 5 is formed along the outer periphery of p-type region 3. In the example shown in FIG. 1, the p-type region 3 has a circular outer shape as shown in a plan view in FIG. 1B, and is in contact with the p-type region 3 on the outer periphery of the circle. A trench 5 is formed. If formed so as to be in contact with p-type region 3, no depletion layer is formed on the side surface thereof, which is effective and preferable for lowering the capacitance. Therefore, a structure may be employed in which the p-type region 3 is formed relatively large and a part of the p-type region is also etched. However, even if the i-layer 2 is interposed with a narrow width, the effect is provided if the width of the i-layer is smaller than the width of the depletion layer. Therefore, it does not need to be completely in contact with the p-type layer 3. Alternatively, the width of the trench 5 may be increased, and dicing may be performed at the trench portion to form a chip.

The insulating region 4 is formed by the trench 5 in the above-described example.
Although an oxide film formed by thermal oxidation is formed therein, even if an oxide film formed by thermal oxidation is not formed, in the case of an element used at a low voltage of about several volts which does not require a high withstand voltage, the trench 5
The air layer forms an insulating region even when spontaneous oxidation is performed in the state in which is formed, and the depletion layer can be prevented from spreading. After the trench 5 is formed, CVD is performed.
An insulating film such as SiO _x or SiN _y may be deposited by a method or the like.

The depth b of the insulating region 4 is formed to be deeper than the depth a of the p-type region 3 described later and smaller than the thickness c of the i-layer 2. That is, they are formed so as to satisfy a <b <c. If b is smaller than a, the formation of a depletion layer on the side surface on the bottom surface side of the p-type region 3 cannot be prevented. If b is larger than c, the depletion layer 6 easily reaches the semiconductor substrate. This is because the withstand voltage is less than 10 V, and it is not preferable because it is easily broken by static electricity or the like even for a product used at a low voltage.

As the semiconductor substrate 1, a substrate made of, for example, n.sup. ^{++ type} Si is used. The i-layer 2 is grown by undoping Si to have a thickness c of about 5 to 15 .mu.m.
Formed. p-type region 3, an open mask only place to form a p-type region 3 is formed by the grown i layer 2 of the surface resist mask such as boron (B) and under N _2, 1,050 to 1,150 ° C. By performing the heat treatment for about 5 to 40 minutes, a p-type region 3 having a depth a of about 2 to 5 μm and a diameter of about 100 μm is formed. The introduction of the p-type impurity is not limited to the diffusion method, but may be performed by ion implantation and heat treatment.

By providing Al or the like on the surface of the p-type region 3, a p-side (anode-side) electrode 7 is formed, and by providing Au or the like on the entire back surface of the semiconductor substrate 1, the n-side is formed. By dicing the (cathode side) electrode 8 to a size of about 300 μm on one side, a PIN diode having the structure shown in FIG. 1 is obtained. Reference numeral 9 denotes an n ^{+ type} channel stopper.

[0022] To manufacture the PIN diode, the impurity concentration put 1 × about 10 ¹⁹ cm ^-3 n ⁺⁺ type silicon substrate 1 to the epitaxial growth furnace, like a normal epitaxial growth, epitaxial growth of silicon undoped Thereby, i-layer 2 is grown to about 10 μm.
Thereafter, a resist film is formed on the surface, removing the resist film only formed where the p-type region 3 by a photolithography process an open mask provided, from 1,050 to 1,100 ° C. in a gas atmosphere such as N ₂ in a diffusion furnace By performing heat treatment for about 5 to 40 minutes, the p-type region 3 is formed to a depth of about 5 μm.

Thereafter, the resist film is removed, a new resist film is provided again, an opening having a width of about 20 μm is provided on the outer periphery of the p-type region 3, the i-layer 2 is etched by RIE, and the trench 5 is formed. For example, it is formed to a depth of about 7 μm. Thereafter, with the resist film attached, 900 to 100
By performing a heat treatment at about 0 ° C. for about 30 minutes, an oxide film is formed in the trench 5 to form the insulating region 4. Then, Al or the like is deposited on the surface of the p-type region 3 to form a p-side electrode 7.
Is formed, and an n-side electrode 8 is formed by evaporating Au or the like on the back surface of the semiconductor substrate, and a chip is formed by dicing to obtain the PIN diode shown in FIG.

In this example, a trench 5 is formed,
After thermal oxidation of the inside, the p-side electrode 7 was formed.
In the case where an insulating film is formed by a degree of natural oxidation or a CVD method without performing thermal oxidation, the trench 5 may be formed after the p-side electrode 7 is formed.

The relationship (A) of the capacitance Ct with respect to the reverse voltage Vr of the PIN diode having this structure is compared with the relationship (B) with the capacitance Ct of the conventional structure as shown in FIG.
It can be seen that at 10 V, it is reduced to about 60% of the conventional structure. The depth b of the insulating region 4 is set to b = 3 μm
When the same measurement is performed for the reverse voltage Vr when the voltage is changed to (C) and 7 μm (D), the results are as shown in FIG. 3, and it is understood that the deeper the capacitance, the better.
However, if the insulating region 4 is too close to the semiconductor substrate 1, the withstand voltage decreases, and the depth is set by the capacitance Ct and the withstand voltage required according to the application.

On the other hand, when it is not necessary to lower the capacitance Ct so much, the depletion layer formed on the side wall in the conventional structure is reduced by p.
It can be increased to the bottom side of the p-type region 3, that is, the plane area of the p-type region 3 can be increased accordingly. For example, FIG.
As shown in FIG. 1A, a cross-sectional explanatory view similar to that of FIG. 1A shows that the p-type region 3 is made wider (about the end side of the depletion layer of the conventional structure (p-type region shown by a broken line)) Diameter of 100μ
m to about 160 μm). By increasing the area of the p-type region 3 in this manner, p
The junction area between the layer and the i-layer increases, and the forward resistance Rf can be reduced.

When the area of the p-type region 3 is increased (E), the forward resistance Rf with respect to the forward current If of the PIN diode is compared with the forward resistance Rf of the conventional structure (F) in FIG. This is shown in b). As is clear from FIG. 4B, the forward resistance can be reduced to about 1/3 (when If = 0.1 mA) as compared with the conventional structure.
The capacitance Ct at this time is almost the same as that of the conventional structure. As described above, by adjusting the size of the p-type region 3, the capacitance Ct and the forward resistance Rf can be adjusted, and the values can be adjusted according to desired characteristics depending on the application.

According to the PIN diode of the present invention, since the insulating region is formed around the side wall of the p-type region, almost no depletion layer is formed on the side wall. Therefore, as shown in FIGS. 2 to 4, the capacitance Ct formed by the depletion layer can be made much smaller than the conventional structure, or the capacitance can be made the same as the conventional structure, and the forward resistance can be reduced.
As a result, conventionally, when one of them was made smaller, the other became larger, and both characteristics could not be satisfied at the same time. However, according to the present invention, both are made smaller while having a trade-off relationship. Can also
Depending on the application, only the capacitance or the forward resistance can be further reduced.

[0029]

In the conventional structure, the relationship between the forward resistance and the capacitance is in a trade-off relationship. If one of them is to be lowered, the other characteristic is deteriorated. According to the present invention, while it was impossible to reduce the other characteristic while maintaining one characteristic as it is depending on the application, according to the present invention, both the characteristics are reduced or the forward resistance is made the same, and the capacitance is reduced. Or
The forward resistance can be reduced while the capacitance is kept as it is. In particular, even when a high-frequency PIN diode having a small forward voltage is required, it can be easily realized.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of one embodiment of a PIN diode according to the present invention.

FIG. 2 is a characteristic diagram of the capacitance of the PIN diode having the structure of FIG. 1;

FIG. 3 is a diagram illustrating a change in capacitance with respect to the depth of an insulating region of the PIN diode according to the structure of FIG. 1;

FIG. 4 is a diagram illustrating an example of reducing the forward resistance in the structure of FIG. 1;

FIG. 5 is a diagram showing a state where the capacitance of a PIN diode differs between an actually measured value and a theoretical value.

FIG. 6 is a diagram illustrating the structure of a conventional PIN diode.

FIG. 7 shows a capacitance Ct of a PIN diode and a forward resistance Rf.
FIG. 4 is a diagram for explaining that the characteristics are in a trade-off relationship.

[Description of Signs] 1 n-type semiconductor substrate 2 i-layer 3 p-type region 4 insulating region 5 trench

Claims (5)

[Claims] A first conductivity type semiconductor substrate; a semi-insulating i-layer provided on the semiconductor substrate; and a second conductivity type region provided on the i-layer. A PIN diode comprising: an insulating region formed around the semiconductor substrate so as to be deeper than the second conductivity type region and not to reach the semiconductor substrate. 2. The PIN diode according to claim 1, wherein said insulating region is formed so as to substantially contact said second conductivity type region. 3. An air layer formed by a trench formed substantially perpendicularly to a main surface of the second conductivity type region, wherein the insulation region is formed in the i-layer or the second conductivity type region or an insulation layer provided in the trench. The PIN diode according to claim 1, wherein: 4. A semi-insulating i-type semiconductor substrate on a first conductivity type semiconductor substrate.
Growing a layer, forming a second conductivity type region by introducing a second conductivity type impurity to the surface side of the i layer, and forming the second conductivity type region around the second conductivity type region or the i layer. Is etched by etching so as to be deeper than the second conductivity type region and not to reach the semiconductor substrate. 5. The method according to claim 4, wherein an insulating film is formed on the side wall of the second conductivity type region or the i-layer exposed by the etching, or an insulator is buried in a groove formed by the etching.