CN106876256B - SiC double-groove UMOSFET device and preparation method thereof - Google Patents

Abstract

The invention relates to a preparation method of a SiC double-slot UMOSFET device, which is characterized by comprising: selecting a SiC substrate; growing a drift layer, an epitaxial layer and a source layer on the continuous surface of the SiC substrate; , the epitaxial layer and the drift layer are etched to form a gate trench; ion implantation is performed on the gate trench to form a gate dielectric protection zone; the source region layer, the epitaxial layer and the drift layer are etched forming a source trench; performing ion implantation on the source trench to form a source trench corner protection area; growing a gate dielectric layer and a gate layer in the gate trench to form a gate; passivation treatment and preparing electrodes to form the SiC dual slot UMOSFET device. By forming a Schottky contact at the interface between the source electrode, the drift layer and the epitaxial layer, the present invention reduces additional Schottky diodes and improves the reliability of the device while ensuring that the "power-on deterioration" problem of the body diode is not caused. And reduce the complexity and cost of device design.

Description

SiC double-groove UMOSFET device and preparation method thereof

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a SiC double-groove UMOSFET device and a preparation method thereof.

Background

The wide band gap semiconductor material SiC has the excellent physical and chemical characteristics of larger forbidden band width, higher critical breakdown electric field, high thermal conductivity, high electron saturation drift velocity and the like, and is suitable for manufacturing high-temperature, high-voltage, high-power and anti-irradiation semiconductor devices. In the field of power electronics, power MOSFETs have been widely used, and have the characteristics of simple gate drive, short switching time, and the like. Compared with the MOSFET with a transverse structure, the UMOSFET with the vertical structure has the advantages of small on-resistance and small cell size, and has wide application prospect.

However, in UMOSFETs, the electric field concentration at the trench gate corners can easily cause premature breakdown of the oxide layer there, which is even more severe for SiC materials. A layer of P + type doped region, namely a P + gate dielectric protection region, is designed at the bottom of the gate groove, so that a peak electric field at the bottom of the groove is transferred from the gate oxide layer to a PN junction formed by the P + gate dielectric protection region and the N-drift layer, and the reliability problem caused by a gate oxide electric field is further relieved. And the UMOSFET with the double-groove structure is used for further improving the breakdown characteristic of the device by notching the source electrode, wherein the depth of the region extending into the N-drift layer is greater than the depth of the gate oxide in the N-drift layer, and the electric field at the oxide layer is transferred to the corner of the source groove due to the existence of the source groove. Meanwhile, when a body diode of the MOSFET, which is used as a freewheeling path to continuously pass forward current, is used as a power switch in the converter, the MOSFET generates a "power-on degradation" phenomenon, which increases the on-resistance and the forward-conduction voltage drop of the diode and causes a reliability problem.

Therefore, in practical applications, a schottky diode with a turn-on voltage lower than that of a body diode is generally connected in parallel across the source and drain of the device to provide a free-wheeling path. It is clear that this approach greatly increases the complexity and cost of the circuit design.

Disclosure of Invention

Therefore, in order to solve the technical defects and shortcomings in the prior art, the invention provides a preparation method of a SiC double-groove UMOSFET device.

Specifically, a method for manufacturing a SiC double-trench UMOSFET device according to an embodiment of the present invention includes:

step 1, selecting a SiC substrate;

step 2, growing a drift layer, an epitaxial layer and a source region layer on the continuous surface of the SiC substrate;

step 3, etching the source region layer, the epitaxial layer and the drift layer to form a gate groove;

step 4, performing ion implantation on the gate groove to form a gate dielectric protection region;

step 5, etching the source region layer, the epitaxial layer and the drift layer to form a source groove;

step 6, performing ion implantation on the source groove to form a source groove corner protection area;

step 7, growing a gate dielectric layer and a gate layer in the gate groove to form a gate;

and 8, passivating and preparing electrodes to form the SiC double-groove UMOSFET device.

In one embodiment of the present invention, step 2 comprises:

step 21, growing the drift layer on the surface of the SiC substrate by using an epitaxial growth process;

step 22, growing the epitaxial layer on the surface of the drift layer by using an epitaxial growth process;

and 23, epitaxially growing the source region layer on the surface of the epitaxial layer by using an epitaxial growth process.

In one embodiment of the present invention, step 3 comprises:

and etching the surface of the source region layer by using an ICP (inductively coupled plasma) etching process and a first mask to form the gate groove in the source region layer, the epitaxial layer and the drift layer.

In one embodiment of the present invention, step 4 comprises:

and performing Al ion implantation on the gate groove by using a self-aligned implantation process and adopting a first mask to form the gate dielectric protection region in the drift layer.

In one embodiment of the present invention, step 5 comprises:

and etching the surface of the source region layer by using an ICP (inductively coupled plasma) etching process and a second mask to form the source groove in the source region layer, the epitaxial layer and the drift layer.

In one embodiment of the present invention, step 6 comprises:

and performing Al ion implantation on the source groove by using a self-aligned implantation process and a second mask to form the corner protection region of the source groove in the drift layer.

In one embodiment of the present invention, the Al ion implantation of the source trench includes:

using an implantation energy of 450keV, 7.97X 10¹³cm^-2For the source ofCarrying out first Al ion injection in the groove;

using an implantation energy of 300keV, 4.69X 10¹³cm^-2Performing second Al ion implantation on the source groove;

using an implantation energy of 200keV, 3.27X 10¹³cm^-2Performing third Al ion implantation on the source groove;

using an implantation energy of 120keV, 2.97X 10¹³cm^-2The fourth Al ion implantation is performed on the source trench.

In one embodiment of the present invention, step 7 comprises:

growing SiO in the gate trench by dry oxygen process₂Material to form the gate dielectric layer;

growing a poly-Si material in the gate trench to form the gate layer using a HWLPCVD process;

in one embodiment of the present invention, step 8 comprises:

growing a passivation layer on the upper surface of the substrate including the grid electrode;

etching the passivation layer on the surface of the grid electrode by using an etching process to form an electrode contact hole;

growing a metal material in the source groove and the electrode contact hole by using an electron beam evaporation process to form a source electrode and a gate electrode;

and growing a metal material on the lower surface of the substrate by using an electron beam evaporation process to form a drain electrode so as to finally form the SiC double-groove UMOSFET device.

In another embodiment of the invention, a SiC double-trench UMOSFET device is provided, which is prepared by the method provided in the above embodiment.

In the embodiment, the Schottky contact is formed on the interface of the source electrode, the N-drift layer and the epitaxial layer to replace an external Schottky diode as a follow current path, so that the problem of 'power-on degradation' of a body diode is avoided, the additional Schottky diode is reduced, the reliability of the device is improved, and the complexity and the cost of the device design are reduced. In addition, the invention utilizes the double-groove structure of the double-groove UMSFET, forms a P + grid medium protection region and a P + source groove corner protection region through an ion self-alignment process without photoetching, further improves the breakdown characteristic of a device, and realizes better device performance with smaller process cost.

Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention, for which reference should be made to the appended claims. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.

Drawings

The following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a SiC double-trench UMOSFET device according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a method for manufacturing a SiC double-trench UMOSFET device according to an embodiment of the present invention;

fig. 3a to fig. 3k are schematic process diagrams of a SiC double-trench UMOSFET device according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Example one

Referring to fig. 1, fig. 1 is a schematic structural diagram of a SiC double-trench UMOSFET device according to an embodiment of the present invention. The SiC double-groove UMOSFET device comprises a drain electrode 11, an N + substrate 1, an N-drift layer 2, a P-epitaxial layer 3, an N + source region layer 4, a source electrode 10, a P + source groove corner protection region 6, a groove gate dielectric 7, polycrystalline silicon 8, a P + gate dielectric protection region 5 and a gate electrode 9.

Preferably, the depth of the source trench is greater than that of the gate trench, and the width of the source trench is equal to the width of the P + source trench corner protection region 6; the width of the gate groove is equal to the width of the P + gate dielectric protection region 5, the interface between the source electrode 10 and the N-drift layer 2 and the P-epitaxial layer 3 is Schottky contact, and the rest is ohmic contact.

Alternatively, the source trench has a depth of 3 μm, the gate trench has a depth of 2.5 μm, and the source trench is formed by Inductively Coupled Plasma (ICP) etching. The widths of the source groove corner protection region 6 and the P + source groove corner protection region are respectively 1 mu m, and the widths of the gate groove corner protection region 5 and the P + gate dielectric protection region are respectively 1.5 mu m.

Optionally, the N + substrate 1 has a thickness of 200 μm to 500 μm and a nitrogen ion doping concentration of 5 × 10¹⁸cm^-3～1×10²⁰cm^-3An N-type SiC substrate 1. The N-drift layer 2 has a thickness of 10-20 μm and a nitrogen ion doping concentration of 1 × 10¹⁵cm^-3～6×10¹⁵cm^-3N-type SiC epitaxial layer.

Optionally, the thickness of the P + source trench corner protection region 6 is 0.5 μm, and the doping concentration of Al ions is 3 × 10¹⁸cm^-3. The thickness of the P + gate dielectric protection region 5 is 0.5 μm, and the Al ion doping concentration is 3 × 10¹⁸cm^-3。

Optionally, the P-epitaxial layer 3 has a thickness of 1 μm to 1.5 μm and an Al ion doping concentration of 1 × 10¹⁷cm^-3P-type SiC epitaxial layer. The N + source region layer 4 has a thickness of 0.5 μm and a nitrogen ion doping concentration of 5X 10¹⁸cm^-3N-type SiC epitaxial layer.

Optionally, the trench gate dielectric 7 is silicon dioxide with a thickness of 100nm, and is formed by a dry oxygen process. The polysilicon 8 is poly Si with a depth of 2.4 μm and a width of 1.3 μm, and fills the entire gate trench structure by deposition. Depositing field oxide layer or Si₃N₄The layer is used as a passivation layer, and the passivation layer is etched to form an electrode hole. The gate electrode 9, the drain electrode 11 and the source electrode 10 and their schottky contacts are formed by electron beam evaporation of metal.

According to the embodiment of the invention, the Schottky diode is introduced into the source groove to replace an externally-connected Schottky diode as a follow current path, so that the problem of 'power-on degradation' of the body diode is avoided, the extra Schottky diode is reduced, the reliability of the device is improved, and the complexity and the cost of the device design are reduced.

The gate electrode in the present invention refers to an integral structure including a gate dielectric layer and a gate material layer, for example, the gate electrode is an integral structure made of a gate oxide material and a polysilicon material. The gate electrode referred to in the present invention means a metal material deposited on the surface of the gate electrode of the present invention for the purpose of metallization interconnection, and similarly expressed, for example, a source electrode and a drain electrode.

Example two

Referring to fig. 2, fig. 2 is a schematic diagram of a method for manufacturing a SiC double-trench UMOSFET device according to an embodiment of the present invention. The preparation method can comprise the following steps:

step 1, selecting a SiC substrate;

step 2, growing a drift layer, an epitaxial layer and a source region layer on the continuous surface of the SiC substrate;

step 3, etching the source region layer, the epitaxial layer and the drift layer to form a gate groove;

step 4, performing ion implantation on the gate groove to form a gate dielectric protection region;

step 5, etching the source region layer, the epitaxial layer and the drift layer to form a source groove;

step 6, performing ion implantation on the source groove to form a source groove corner protection area;

step 7, growing a gate dielectric layer and a gate layer in the gate groove to form a gate;

and 8, passivating and preparing electrodes to form the SiC double-groove UMOSFET device.

Optionally, for step 2, the method may include:

step 21, growing the drift layer on the surface of the SiC substrate by using an epitaxial growth process;

step 22, growing the epitaxial layer on the surface of the drift layer by using an epitaxial growth process;

and 23, epitaxially growing the source region layer on the surface of the epitaxial layer by using an epitaxial growth process.

Specifically, for step 21, the method comprises the following steps:

on an N-type SiC substrateA drift layer doped with nitrogen ions with the doping concentration of 1 multiplied by 10 and grown on the substrate with the thickness of 10 to 20 mu m¹⁵cm^-3～6×10¹⁵cm^-3The epitaxy temperature is 1600 ℃, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen;

specifically, for step 22, the method comprises the following steps:

growing an epitaxial layer doped with 1 mu m-1.5 mu mAl ions on the drift layer doped with nitrogen ions, wherein the doping concentration is 1 multiplied by 10¹⁷cm^-3～1×10¹⁸cm^-3The epitaxy temperature is 1600 ℃, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is trimethyl aluminum;

specifically, for step 23, the method comprises the following steps:

growing a source region layer doped with 0.5 mu m nitrogen ions on the epitaxial layer, wherein the doping concentration is 5 multiplied by 10¹⁸cm^-3The epitaxy temperature is 1600 ℃, the pressure is 100mbar, the reaction gas is silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen;

optionally, for step 3, the method may include:

and etching the surface of the source region layer by using an ICP (inductively coupled plasma) etching process and a first mask to form the gate groove in the source region layer, the epitaxial layer and the drift layer.

Specifically, for step 3, the method comprises the following steps:

etching to form a gate groove with a width of 1.5 μm and a depth of 2.5 μm by ICP process, wherein the ICP coil power is 850W, the source power is 100W, and the reaction gas SF is₆And O₂48sccm and 12sccm, respectively;

optionally, for step 4, the method may include:

and performing Al ion implantation on the gate groove by using a self-aligned implantation process and adopting a first mask to form the gate dielectric protection region in the drift layer.

Specifically, for step 4, the method comprises the following steps:

multiple Al ion self-alignment injection on drift layer by using etching mask of gate trenchIn, the depth of formation is 0.5 μm, and the concentration is 3X 10¹⁸cm^-3The injection temperature of the gate dielectric protection region is 650 ℃.

Optionally, for step 5, the method may include:

and etching the surface of the source region layer by using an ICP (inductively coupled plasma) etching process and a second mask to form the source groove in the source region layer, the epitaxial layer and the drift layer.

Specifically, for step 5, the method comprises the following steps:

forming a source groove by ICP process etching, wherein the width is 1 μm, the depth is 3 μm, the ICP coil power is 850W, the source power is 100W, and the reaction gas SF₆And O₂48sccm and 12sccm, respectively;

optionally, for step 6, the method may include:

and performing Al ion implantation on the source groove by using a self-aligned implantation process and a second mask to form the corner protection region of the source groove in the drift layer.

Wherein, carrying out Al ion implantation on the source groove comprises:

using an implantation energy of 450keV, 7.97X 10¹³cm^-2The first Al ion implantation is carried out on the grid groove;

using an implantation energy of 300keV, 4.69X 10¹³cm^-2Performing second Al ion implantation on the gate trench;

using an implantation energy of 200keV, 3.27X 10¹³cm^-2Performing third Al ion implantation on the gate trench;

using an implantation energy of 120keV, 2.97X 10¹³cm^-2And performing fourth Al ion implantation on the gate trench.

Specifically, for step 6, the method comprises the following steps:

performing multiple Al ion self-aligned implantation on the drift layer by using the etching mask of the source trench to form a layer with a depth of 0.5 μm and a concentration of 3 × 10¹⁸cm^-3The injection temperature of the source groove corner protection area is 650 ℃;

optionally, for step 7, it may include:

growing SiO in the gate trench by dry oxygen process₂Material to form the gate dielectric layer;

growing a polycrystalline Si material in the gate groove by using a Hot Wall Low Pressure Chemical Vapor Deposition (HWLPCVD) process to form the gate layer;

specifically, step 7 includes:

preparation of SiO by dry oxygen process at 1150 deg.C₂The thickness of the gate dielectric layer is 100nm, and then annealing is carried out at 1050 ℃ under the NO atmosphere to reduce SiO₂Roughness of the film surface;

growing poly Si by adopting an HWLPCVD process to fill the gate groove, wherein the deposition temperature is 600-650 ℃, the deposition pressure is 60-80 Pa, the reaction gas is silane and phosphine, and the carrier gas is helium;

optionally, for step 8, it may include:

growing a passivation layer on the upper surface of the substrate including the grid electrode;

etching the passivation layer on the surface of the grid electrode by using an etching process to form an electrode contact hole;

growing a metal material in the source groove and the electrode contact hole by using an electron beam evaporation process to form a source electrode and a gate electrode 9;

and growing a metal material on the lower surface of the substrate by using an electron beam evaporation process to form a drain electrode so as to finally form the SiC double-groove UMOSFET device.

Specifically, step 8 comprises:

depositing a layer of field oxygen or Si on the surface of the device₃N₄Layer, then opening electrode contact holes;

evaporating Ti/Ni/Au by electron beams, preparing an electrode, and finally, rapidly annealing for 3min in Ar atmosphere at 1050 ℃. Because the doping concentration of the drift layer and the epitaxial layer is low, Schottky contact is formed at the interface of the source electrode, the drift layer and the epitaxial layer, and ohmic contact is formed at other interfaces.

According to the embodiment of the invention, the Schottky diode is introduced into the source groove to replace an externally-connected Schottky diode as a follow current path, so that the problem of 'power-on degradation' of the body diode is avoided, the extra Schottky diode is reduced, the reliability of the device is improved, and the complexity and the cost of the device design are reduced. In addition, the embodiment of the invention utilizes the double-groove structure of the double-groove UMSFET, forms the gate dielectric protection region and the source groove corner protection region through the ion self-alignment process without photoetching, further improves the breakdown characteristic of the device, and realizes better device performance with smaller process cost.

Example two

Referring to fig. 3, fig. 3 provides another SiC double-trench UMOSFET device manufacturing method for this embodiment, where the manufacturing method includes the following steps:

step a, epitaxially growing an N-drift layer 2 on an N-type SiC substrate 1, as shown in fig. 3 a.

Firstly, the thickness is 200 μm, the nitrogen ion doping concentration is 5 × 10¹⁸cm^-3The N-type SiC substrate of (1) was subjected to RCA standard cleaning, and then epitaxially grown to a thickness of 10 μm and a nitrogen ion doping concentration of 1X 10 over the entire SiC substrate 1¹⁵cm^-3And an N-drift layer 2. The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was liquid nitrogen.

And step b, epitaxially growing a P-epitaxial layer 3, as shown in FIG. 3 b.

A layer with the thickness of 1 μm and the Al ion doping concentration of 1 × 10 is grown on the N-drift layer 2¹⁷cm^-3P-epitaxial layer 3. The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was tri-methyl aluminum.

And c, epitaxially growing an N + source region layer 4 as shown in FIG. 3 c.

A layer with the thickness of 0.5 μm and the nitrogen ion doping concentration of 5 x 10 is grown on the P-epitaxial layer 3¹⁸cm^-3N + source region layer 4. The process conditions are as follows: the temperature is 1600 ℃, the pressure is 100mbar, the reaction gases are silane and propane, the carrier gas is pure hydrogen, and the impurity source is liquid nitrogen。

And d, etching to form a gate groove as shown in fig. 3 d.

Firstly, magnetron sputtering a layer

The Ti film is used as an ICP etching mask, then glue is coated for photoetching, ICP etching is carried out, the width of an etched groove is 1.5 mu m, the depth of the etched groove is 2.5 mu m, finally glue is removed, the etching mask is removed, and a polished section is cleaned. The process conditions are as follows: ICP coil power 850W, source power 100W, and reaction gas SF₆And O₂48sccm and 12sccm, respectively.

And e, performing multiple times of Al ion self-alignment injection on the N-drift layer 2 by using the etching mask of the gate groove, as shown in FIG. 3 e.

The implantation energies of 450keV, 300keV, 200keV and 120keV are adopted successively, and the implantation dosage is 7.97 x 10¹³cm^-2、4.69×10¹³cm^-2、3.27×10¹³cm^-2And 2.97X 10¹³cm^-2Is implanted into the implanted region of the N-drift layer 2 in four times to a depth of 0.5 μm and a concentration of 3X 10¹⁸cm^-3The injection temperature of the P + gate dielectric protection region 5 is 650 ℃.

Step f, etching to form a source groove as shown in FIG. 3 f.

Firstly, magnetron sputtering a layer

The Ti film is used as an ICP etching mask, then glue is coated for photoetching, ICP etching is carried out, the width of an etched groove is 1 mu m, the depth of the etched groove is 3 mu m, finally glue is removed, the etching mask is removed, and a polished section is cleaned. The process conditions are as follows: ICP coil power 850W, source power 100W, and reaction gas SF₆And O₂48sccm and 12sccm, respectively.

And g, carrying out multiple times of Al ion self-alignment injection on the N-drift layer 2 by utilizing the etching mask of the source groove, as shown in figure 3 g.

Firstly, the implantation energies of 450keV, 300keV, 200keV and 120keV are adopted in sequence, and the implantation dosage is 7.97 multiplied by 10¹³cm^-2、4.69×10¹³cm^-2、3.27×10¹³cm^-2And 2.97X 10¹³cm^-2Is implanted into the implanted region of the N-drift layer 2 in four times to a depth of 0.5 μm and a concentration of 3X 10¹⁸cm^-3The implantation temperature of the P + source trench corner protection region 6 is 650 ℃.

And cleaning the SiC surface by adopting an RCA cleaning standard, drying, manufacturing a C film for protection, and then carrying out ion activation annealing for 10min in an argon atmosphere at 1700-1750 ℃.

Step h, preparing the groove gate dielectric 7 by using SiO as a material₂As shown in fig. 3 h.

Preparation of SiO by dry oxygen process at 1150 deg.C₂The thickness of the gate dielectric layer is 100nm, and then annealing is carried out at 1050 ℃ under the NO atmosphere to reduce SiO₂Roughness of the film surface.

Step i, preparing a poly Si gate, as shown in FIG. 3 i.

And growing poly Si by adopting a low-pressure hot-wall chemical vapor deposition method to fill the gate groove, wherein the deposition temperature is 600-650 ℃, the deposition pressure is 60-80 Pa, the reaction gases are silane and phosphine, the carrier gas is helium, then coating glue and photoetching are carried out, the poly Si layer is etched, a polysilicon gate is formed, and finally, the glue is removed and cleaning is carried out.

Step j, preparing a passivation layer as shown in fig. 3 j.

Depositing a layer of field oxygen or Si on the surface of the device₃N₄And coating glue and photoetching, corroding the passivation layer to form an electrode contact hole, and finally removing the glue and cleaning.

Step k, preparing the electrode, as shown in fig. 3 k.

Firstly, manufacturing a grid and a source electrode by electron beam evaporation Ti/Ni/Au on the front surface, then coating glue and photoetching, corroding metal to form the grid and the source electrode, removing the glue and cleaning.

And evaporating Ti/Ni/Au by electron beams on the back surface to manufacture a drain electrode, and finally, rapidly annealing for 3min in Ar atmosphere at 1050 ℃. Because the doping concentration of the N-drift layer 2 and the P-epitaxial layer 3 is low, Schottky contact is formed between the source electrode 10 and the interface of the N-drift layer 2 and the P-epitaxial layer 3, and ohmic contact is formed at other interfaces.

EXAMPLE III

Referring to fig. 3, fig. 3 provides another SiC double-trench UMOSFET device manufacturing method for this embodiment, where the manufacturing method includes the following steps:

step a, epitaxially growing an N-drift layer 2 on an N-type SiC substrate 1, as shown in fig. 3 a.

Firstly, the thickness is 500 μm, the doping concentration of nitrogen ion is 1 × 10²⁰cm^-3The N-type SiC substrate 1 was subjected to RCA standard cleaning, and then epitaxially grown to a thickness of 20 μm and a nitrogen ion doping concentration of 3X 10 over the entire SiC substrate 1¹⁵cm^-3And an N-drift layer 2. The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was liquid nitrogen.

And step b, epitaxially growing a P-epitaxial layer 3, as shown in FIG. 3 b.

A layer with the thickness of 1.5 μm and the Al ion doping concentration of 1 × 10 is grown on the N-drift layer 2¹⁷cm^-3P-epitaxial layer 3. The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was tri-methyl aluminum.

And c, epitaxially growing an N + source region layer 4 as shown in FIG. 3 c.

A layer with the thickness of 0.5 μm and the nitrogen ion doping concentration of 5 x 10 is grown on the P-epitaxial layer 3¹⁸cm^-3N + source region layer 4. The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was liquid nitrogen.

And d, etching to form a gate groove as shown in fig. 3 d.

Firstly, magnetron sputtering a layer

The Ti film is used as an ICP etching mask, then glue is coated for photoetching, ICP etching is carried out, the width of an etched groove is 1.5 mu m, the depth of the etched groove is 2.5 mu m, finally glue is removed, the etching mask is removed, and a polished section is cleaned. The process conditions are as follows: ICP coil power 850W, source power 100W, and reaction gas SF₆And O₂48sccm and 12sccm, respectively.

And e, performing multiple times of Al ion self-alignment injection on the N-drift layer 2 by using the etching mask of the gate groove, as shown in FIG. 3 e.

The implantation energies of 450keV, 300keV, 200keV and 120keV are adopted successively, and the implantation dosage is 7.97 x 10¹³cm^-2、4.69×10¹³cm^-2、3.27×10¹³cm^-2And 2.97X 10¹³cm^-2Is implanted into the implanted region of the N-drift layer 2 in four times to a depth of 0.5 μm and a concentration of 3X 10¹⁸cm^-3The injection temperature of the P + gate dielectric protection region 5 is 650 ℃.

Step f, etching to form a source groove as shown in FIG. 3 f.

Firstly, magnetron sputtering a layer

The Ti film is used as an ICP etching mask, then glue is coated for photoetching, ICP etching is carried out, the width of an etched groove is 1 mu m, the depth of the etched groove is 3 mu m, finally glue is removed, the etching mask is removed, and a polished section is cleaned. The process conditions are as follows: ICP coil power 850W, source power 100W, and reaction gas SF₆And O₂48sccm and 12sccm, respectively.

And g, carrying out multiple times of Al ion self-alignment injection on the N-drift layer 2 by utilizing the etching mask of the source groove, as shown in figure 3 g.

Firstly, the implantation energies of 450keV, 300keV, 200keV and 120keV are adopted in sequence, and the implantation dosage is 7.97 multiplied by 10¹³cm^-2、4.69×10¹³cm^-2、3.27×10¹³cm^-2And 2.97X 10¹³cm^-2Is implanted into the implanted region of the N-drift layer 2 in four times to a depth of 0.5 μm and a concentration of 3X 10¹⁸cm^-3The implantation temperature of the P + source trench corner protection region 6 is 650 ℃.

And cleaning the SiC surface by adopting an RCA cleaning standard, drying, manufacturing a C film for protection, and then carrying out ion activation annealing for 10min in an argon atmosphere at 1700-1750 ℃.

Step h, preparing a trench gate dielectric7, the material is SiO₂As shown in fig. 3 h.

Preparation of SiO by dry oxygen process at 1150 deg.C₂The thickness of the gate dielectric layer is 100nm, and then annealing is carried out at 1050 ℃ under the NO atmosphere to reduce SiO₂Roughness of the film surface.

Step i, preparing a poly Si gate, as shown in FIG. 3 i.

And growing poly Si by adopting a low-pressure hot-wall chemical vapor deposition method to fill the gate groove, wherein the deposition temperature is 600-650 ℃, the deposition pressure is 60-80 Pa, the reaction gases are silane and phosphine, the carrier gas is helium, then coating glue and photoetching are carried out, the poly Si layer is etched, a polysilicon gate is formed, and finally, the glue is removed and cleaning is carried out.

Step j, preparing a passivation layer as shown in fig. 3 j.

Depositing a layer of field oxygen or Si on the surface of the device₃N₄And coating glue and photoetching, corroding the passivation layer to form an electrode contact hole, and finally removing the glue and cleaning.

Step k, preparing the electrode, as shown in fig. 3 k.

Firstly, manufacturing a grid and a source electrode by electron beam evaporation Ti/Ni/Au on the front surface, then coating glue and photoetching, corroding metal to form the grid and the source electrode, removing the glue and cleaning.

And evaporating Ti/Ni/Au by electron beams on the back surface to manufacture a drain electrode, and finally, rapidly annealing for 3min in Ar atmosphere at 1050 ℃. Because the doping concentration of the N-drift layer 2 and the P-epitaxial layer 3 is low, Schottky contact is formed between the source electrode 10 and the interface of the N-drift layer 2 and the P-epitaxial layer 3, and ohmic contact is formed at other interfaces.

Example four

Referring to fig. 3, fig. 3 provides another SiC double-trench UMOSFET device manufacturing method for this embodiment, where the manufacturing method includes the following steps:

step a, epitaxially growing an N-drift layer 2 on an N-type Si substrate 1, as shown in fig. 3 a.

Firstly, the thickness is 300 μm, the doping concentration of nitrogen ion is 1 × 10¹⁹cm^-3The N-type SiC substrate of (1) was subjected to RCA standard cleaning, and then epitaxially grown to a thickness of 15 μm and a nitrogen ion doping concentration of 6X 10 over the entire SiC substrate 1¹⁵cm^-3And an N-drift layer 2. The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was liquid nitrogen.

And step b, epitaxially growing a P-epitaxial layer 3, as shown in FIG. 3 b.

A layer with the thickness of 1.3 μm and the Al ion doping concentration of 1 × 10 is grown on the N-drift layer 2¹⁷cm^-3P-epitaxial layer 3. The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was tri-methyl aluminum.

And c, epitaxially growing an N + source region layer 4 as shown in FIG. 3 c.

A layer with the thickness of 0.5 μm and the nitrogen ion doping concentration of 5 x 10 is grown on the P-epitaxial layer 3¹⁸cm^-3N + source region layer 4.

The process conditions are as follows: the temperature was 1600 ℃, the pressure was 100mbar, the reaction gases were silane and propane, the carrier gas was pure hydrogen, and the impurity source was liquid nitrogen.

And d, etching to form a gate groove as shown in fig. 3 d.

Firstly, magnetron sputtering a layer

The Ti film is used as an ICP etching mask, then glue is coated for photoetching, ICP etching is carried out, the width of an etched groove is 1.5 mu m, the depth of the etched groove is 2.5 mu m, finally glue is removed, the etching mask is removed, and a polished section is cleaned. The process conditions are as follows: ICP coil power 850W, source power 100W, and reaction gas SF₆And O₂48sccm and 12sccm, respectively.

And e, performing multiple times of Al ion self-alignment injection on the N-drift layer 2 by using the etching mask of the gate groove, as shown in FIG. 3 e.

The implantation energies of 450keV, 300keV, 200keV and 120keV are adopted successively, and the implantation dosage is 7.97 x 10¹³cm^-2、4.69×10¹³cm^-2、3.27×10¹³cm^-2And 2.97X 10¹³cm^-2Is implanted into the N-drift layer 2 in four timesA region formed to a depth of 0.5 μm and having a concentration of 3X 10¹⁸cm^-3The injection temperature of the P + gate dielectric protection region 5 is 650 ℃.

Step f, etching to form a source groove as shown in FIG. 3 f.

Firstly, magnetron sputtering a layer

The Ti film is used as an ICP etching mask, then glue is coated for photoetching, ICP etching is carried out, the width of an etched groove is 1 mu m, the depth of the etched groove is 3 mu m, finally glue is removed, the etching mask is removed, and a polished section is cleaned. The process conditions are as follows: ICP coil power 850W, source power 100W, and reaction gas SF₆And O₂48sccm and 12sccm, respectively.

And g, carrying out multiple times of Al ion self-alignment injection on the N-drift layer 2 by utilizing the etching mask of the source groove, as shown in figure 3 g.

Firstly, the implantation energies of 450keV, 300keV, 200keV and 120keV are adopted in sequence, and the implantation dosage is 7.97 multiplied by 10¹³cm^-2、4.69×10¹³cm^-2、3.27×10¹³cm^-2And 2.97X 10¹³cm^-2Is implanted into the implanted region of the N-drift layer 2 in four times to a depth of 0.5 μm and a concentration of 3X 10¹⁸cm^-3The implantation temperature of the P + source trench corner protection region 6 is 650 ℃.

And cleaning the SiC surface by adopting an RCA cleaning standard, drying, manufacturing a C film for protection, and then carrying out ion activation annealing for 10min in an argon atmosphere at 1700-1750 ℃.

Step h, preparing the groove gate dielectric 7 by using SiO as a material₂As shown in fig. 3 h.

Preparation of SiO by dry oxygen process at 1150 deg.C₂The thickness of the gate dielectric layer is 100nm, and then annealing is carried out at 1050 ℃ under the NO atmosphere to reduce SiO₂Roughness of the film surface.

Step i, preparing a poly Si gate, as shown in FIG. 3 i.

And growing poly Si by adopting a low-pressure hot-wall chemical vapor deposition method to fill the gate groove, wherein the deposition temperature is 600-650 ℃, the deposition pressure is 60-80 Pa, the reaction gases are silane and phosphine, the carrier gas is helium, then coating glue and photoetching are carried out, the poly Si layer is etched, a polysilicon gate is formed, and finally, the glue is removed and cleaning is carried out.

Step j, preparing a passivation layer as shown in fig. 3 j.

Depositing a layer of field oxygen or Si on the surface of the device₃N₄And coating glue and photoetching, corroding the passivation layer to form an electrode contact hole, and finally removing the glue and cleaning.

Step k, preparing the electrode, as shown in fig. 3 k.

Firstly, manufacturing a grid and a source electrode by electron beam evaporation Ti/Ni/Au on the front surface, then coating glue and photoetching, corroding metal to form the grid and the source electrode, removing the glue and cleaning.

And evaporating Ti/Ni/Au by electron beams on the back surface to manufacture a drain electrode, and finally, rapidly annealing for 3min in Ar atmosphere at 1050 ℃. Because the doping concentration of the N-drift layer 2 and the P-epitaxial layer 3 is low, Schottky contact is formed between the source electrode 10 and the interface of the N-drift layer 2 and the P-epitaxial layer 3, and ohmic contact is formed at other interfaces.

In summary, the present invention has been described with specific examples to describe embodiments of a SiC double-trench UMOSFET device and a method for manufacturing the same according to embodiments of the present invention, and the description of the above examples is only used to help understanding the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention, and the scope of the present invention should be subject to the appended claims.

Claims (6)

1. A preparation method of a SiC double-groove UMOSFET device is characterized by comprising the following steps:

step 1, selecting a SiC substrate;

step 2, growing a drift layer, an epitaxial layer and a source region layer on the continuous surface of the SiC substrate;

step 3, etching the source region layer, the epitaxial layer and the drift layer to form a gate groove;

step 4, performing ion implantation on the gate groove to form a gate dielectric protection region;

step 4 comprises the following steps:

performing Al ion implantation on the gate trench by using a self-aligned implantation process and a first mask to form the gate dielectric protection region in the drift layer;

performing Al ion implantation on the gate trench to form the gate dielectric protection region in the drift layer, including:

the implantation energies of 450keV, 300keV, 200keV and 120keV are adopted successively, and the implantation dosage is 7.97 x 10¹³cm^-2、4.69×10¹³cm^-2、3.27×10¹³cm^-2And 2.97X 10¹³cm^-2Injecting the Al ions into the drift layer for four times to form the gate dielectric protection region;

step 5, etching two ends of the source region layer, the epitaxial layer and the drift layer to respectively form source grooves, wherein the depth of each source groove is greater than that of each gate groove, and each gate groove is positioned between two source grooves;

step 6, performing ion implantation on the source groove to form a source groove corner protection area;

the step 6 comprises the following steps:

performing Al ion implantation on the source groove by using a self-aligned implantation process and a second mask to form the corner protection region of the source groove in the drift layer;

performing Al ion implantation on the source trench, including:

using an implantation energy of 450keV, 7.97X 10¹³cm^-2The first Al ion implantation is carried out on the source groove;

using an implantation energy of 300keV, 4.69X 10¹³cm^-2Performing second Al ion implantation on the source groove;

using an implantation energy of 200keV, 3.27X 10¹³cm^-2Performing third Al ion implantation on the source groove;

using an implantation energy of 120keV, 2.97X 10¹³cm^-2For the source tankPerforming fourth Al ion implantation;

step 7, growing a gate dielectric layer and a gate layer in the gate groove to form a gate;

step 8, passivating and preparing electrodes to form the SiC double-groove UMOSFET device;

the step 8 comprises the following steps:

growing a passivation layer on the upper surface of the substrate including the grid electrode;

etching the passivation layer on the surface of the grid electrode by using an etching process to form an electrode contact hole;

growing a metal material in the source groove and the electrode contact hole by using an electron beam evaporation process to form a source electrode and a gate electrode, wherein the source electrode in the source groove is in Schottky contact with the interface of the epitaxial layer and the interface of the drift layer;

and growing a metal material on the lower surface of the substrate by using an electron beam evaporation process to form a drain electrode so as to finally form the SiC double-groove UMOSFET device.

2. The method of claim 1, wherein step 2 comprises:

step 21, growing the drift layer on the surface of the SiC substrate by using an epitaxial growth process;

step 22, growing the epitaxial layer on the surface of the drift layer by using an epitaxial growth process;

and 23, epitaxially growing the source region layer on the surface of the epitaxial layer by using an epitaxial growth process.

3. The method of claim 1, wherein step 3 comprises:

and etching the surface of the source region layer by using an ICP (inductively coupled plasma) etching process and a first mask to form the gate groove in the source region layer, the epitaxial layer and the drift layer.

4. The method of claim 1, wherein step 5 comprises:

and etching the surface of the source region layer by using an ICP (inductively coupled plasma) etching process and a second mask to form the source groove in the source region layer, the epitaxial layer and the drift layer.

5. The method of claim 1, wherein step 7 comprises:

growing SiO in the gate trench by dry oxygen process₂Material to form the gate dielectric layer;

and growing a polycrystalline Si material in the gate groove by using a HWLPCVD process to form the gate electrode layer.

6. A SiC double-groove UMOSFET device, which is characterized by being prepared by the method of any one of claims 1-5.

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