JP2001358128A - Method for manufacturing semiconductor device - Google Patents

Abstract

[Problem] To provide a dry etching method with less damage to a gate insulating film due to charge-up. SOLUTION: In a method of manufacturing a semiconductor device in which wiring patterns 20, 21 and gate electrode patterns 36, 37 having various pattern densities are mixed, wiring is performed by dry etching under etching conditions in which the higher the pattern density, the higher the etching rate. A pattern or a gate electrode pattern is patterned.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device having a dense / dense wiring pattern or a dense / dense gate electrode pattern.

[0002]

2. Description of the Related Art In recent years, power consumption of semiconductor devices has been reduced,
The gate insulating film thickness is 0.25 μm due to the higher performance.
Is 7 to 9 nm in the wiring rule, 4 nm in the 0.18 μm wiring rule, and 2.5 n in the 0.13 μm wiring rule.
As shown in FIG. With such a reduction in the thickness of the gate insulating film, charge-up damage during dry etching, which lowers the reliability of the gate insulating film, has become a major problem. In particular, in a logic LSI in which various and complicated wiring patterns exist, the wiring pattern functions as an antenna for charge incidence, so that charge-up damage due to the antenna effect is a serious problem. Hereinafter, the charge-up damage due to the antenna effect will be described.

FIG. 7 is a conceptual diagram showing a charge-up mechanism in a dry etching step of wiring on a semiconductor substrate. In FIG. 7, 1 is a semiconductor substrate, 2 is a gate insulating film, 3 is a gate electrode, 10 is an interlayer insulating film, 11
Denotes a contact hole connected to the gate electrode 3, 50
Is a wiring pattern, and 51 is a resist.

During the dry etching, the wiring pattern 50 is exposed to the plasma 52 and charged particles enter the semiconductor substrate 1. In the wiring pattern 50, etching proceeds by ions and radicals supplied from the plasma thus incident. At this time, with respect to the wiring pattern 50 electrically connected to the contact hole 11 and electrically floating (electrically separated from other wiring patterns), charged particles in the plasma from the pattern side wall. Is incident on the wiring pattern 50, and the charges concentrate on the gate electrode 3 via the contact hole 11. For this reason, a large electric field is generated in the gate insulating film 2, and this electric field causes a gate insulating film breakdown.

As described above, the side wall of the wiring pattern 50 is
Acts as an antenna for incident charged particles. And
The ratio of the area of the region serving as an antenna (here, the total area of the side wall portions of the wiring pattern 50) to the gate area (Lg (gate length) × W (gate width)) is called an antenna ratio, and a structure having a large antenna ratio The more the charge-up damage of the gate insulating film 2 increases, the more.

FIG. 8 is a graph showing the relationship between the breakdown ratio of the gate insulating film 2 and the antenna ratio. As is clear from FIG. 8, it is understood that the damage to the gate insulating film 2 increases as the antenna ratio increases. In the semiconductor device, the surface area of the wiring pattern 50 is equal to the gate insulating film 2.
It becomes very large for the upper electrode area, and the antenna ratio reaches several hundreds to tens of thousands.

Therefore, in each of the current wiring rules, a rule of an allowable antenna ratio has been established in view of the degree of characteristic deterioration due to insulation film breakdown, and the insulation film breakdown due to charge-up has been suppressed by observing the rule.

[0008]

As described above, the breakdown of the insulating film due to the charge-up has been suppressed by observing the rules set for the antenna ratio. In recent years, however, the mechanism of occurrence of a new charge-up damage has been elucidated. (For example, Ono et al., The 46th Joint Lecture Meeting on Applied Physics)
p775 (1999)).

The mechanism of occurrence of the charge-up damage will be described with reference to FIG. FIG. 9 is a process cross-sectional view for describing the above-described antenna effect damage during the dry etching in the wiring process.

In FIG. 9, 1 is a semiconductor substrate, and 2 is a game substrate.
Insulating film, 3 is a gate electrode, 4 is an isolation region, 10 is an interlayer
The insulating film 11 is a contact connected to the gate electrode 3
The holes 12 are contactors connected to the semiconductor substrate 1.
13, a wiring material film, 14 a space width S₁To
15 has a high aspect ratio resist pattern
Width S_TwoResist pattern with low aspect ratio, 2
0 is the space width S₁Aspect ratio wiring pattern with
, 21 is the space width S_TwoWiring with low aspect ratio
It is a pattern. In the figure, the aspect ratio S₁, S_TwoTo
In the S₁<S_TwoRelationship exists. Aspect ratio and
Is defined by the wiring film thickness / space width.
The pattern density of the wiring pattern is shown. Wiring putter
The film thickness of the₀Gives a high aspect ratio
The aspect ratio of the line pattern 20 is (T₀/ S₁)
And the aspect ratio of the low aspect ratio wiring pattern 21 is
(T ₀/ S_Two). In other words, relatively high
The aspect ratio wiring pattern 20 is a low aspect ratio wiring pattern.
Indicates that the pattern density is denser than
You.

[0011] As shown in FIG.
After the gate insulating film 2 and the gate electrode 3 are formed,
An interlayer insulating film 10 is deposited, and contact holes 11 and 1 are formed.
2 is formed by a known technique such as lithography and dry etching. Thereafter, a wiring material film 13 is deposited, and the wiring material film 13 is patterned by lithography to form wiring patterns 20 and 21. The resist patterns 14 and 15 are used when patterning the wiring material film 13. Note that the wiring pattern 20 and the wiring pattern 21 are not electrically connected to each other.

Generally, as shown in FIG. 9A, when a line and space pattern in which a high aspect ratio and a low aspect ratio are combined is etched, it is caused by the pattern dependence of the incident angle of ions and the incident amount of radicals. RI to do
The E lag phenomenon easily occurs. This is a phenomenon in which the etching rate of a wiring pattern region having a high aspect ratio (dense pattern density) is lower than that of a wiring pattern region having a low aspect ratio (sparse pattern density). When such a phenomenon occurs, FIG.
As shown in FIG. 5, the etching depth (etching rate) of the high aspect ratio wiring pattern 20 after a predetermined time has elapsed.
towards h ₅ is, it becomes low aspect ratio etching depth of the wiring pattern 21 shallower than the (etching rate) h _{4 (slow) (h 5 <h 4)} .

At this time, the charged particles 53 in the plasma 52
Is incident not only from the bottom of the etching groove but also from the side wall of the etching groove. These incident charged particles flow into the semiconductor substrate 1 through the contact holes 12.

In this state, if the etching is further advanced,
As shown in FIG. 9C, in the region of the low aspect ratio wiring pattern 21, the wiring material film 13 at the bottom of the etching groove disappears and the underlying interlayer insulating film 10 is exposed. At this time, in the region of the high aspect ratio wiring pattern 20, the wiring material film 13 at the bottom of the etching groove has not disappeared. Therefore, at this time, the low aspect ratio wiring pattern 21 and the high aspect ratio wiring pattern 22 are electrically separated. Since the high aspect ratio wiring pattern 20 is not connected to the semiconductor substrate 1, it is in a state of being electrically floating (electrically separated) with respect to the gate electrode 3 at this point. At this time, the charged particles 53 of the plasma
The light enters from the pattern side wall and the pattern bottom of the high aspect ratio wiring pattern 20, passes through the contact hole 11, and is accumulated in the gate electrode 3.

Previously, it was thought that only the pattern sidewalls functioned as charged particle antennas. However, as described above, the high aspect ratio wiring pattern 2
In the 0 region, the charged particles 53 enter from the lower part of the etching groove. Therefore, it is possible to calculate the incident charge amount more accurately by considering that the bottom of the etching groove also plays the role of the antenna. Thus, in effect,
The antenna area is larger than previously thought,
As more charged particles 53 accumulate on the gate electrode 3,
Accelerate charge-up. This clearly shows that charge-up damage occurs in the gate insulating film 3 more than conventionally thought.

[0016] For these reasons, it is clear that suppression of insulation film breakdown due to charge-up is insufficient only by observing the rules of the antenna ratio set for the current wiring rules. It has been desired to suppress antenna charge-up damage caused by the RIE lag.

Accordingly, an object of the present invention is to provide a dry etching method capable of suppressing antenna charge-up damage caused by RIE lag without changing the device structure.

[0018]

According to the dry etching method of the present invention, in order to suppress the charge-up damage due to the antenna effect derived from the RIE lag described above,
As shown in FIG. 1, the etching using an inverse RIE lag characteristic in which the etching rate is higher as the region has a higher aspect ratio is used. In FIG. 1, 8
0 high aspect ratio region 81 is a low aspect ratio region, when the inverse RIE lag, better etch depth h ₇ of the high aspect ratio region 80 is greater than the etch depth h ₈ of the low aspect ratio region . In addition,
In FIG. 1, reference numeral 82 denotes a resist, 83 denotes a wiring material film, and 84 denotes a semiconductor substrate.

FIG. 2 shows an inverse RIE lag.
Therefore, interlayer insulation under the high aspect ratio wiring pattern
After the edge film is exposed, the low aspect ratio wiring pattern remains.
The load when overetching was performed to remove the excess
FIG. 2 is a schematic diagram of the behavior of an electric particle, and in FIG.
High aspect ratio wiring pattern on interlayer insulating film on MOS structure
When forming a pattern and a low aspect ratio wiring pattern
Will be described. In FIG. 2, 1 is a semiconductor substrate and 2 is a game substrate.
Insulating film, 3 is a gate electrode, 4 is an isolation region, 10 is an interlayer
An insulating film 11 is a contact hole connected to the gate electrode 3.
And 12 are contact holes connected to the semiconductor substrate 1.
, 13 is a wiring material film, 14 is a high aspect ratio resist
Pattern, 15 is a low aspect ratio resist pattern, 2
0 is the space width S₁Aspect ratio wiring pattern with
, 21 is the space width S_TwoWiring with low aspect ratio
It is a pattern. The space width S₁, S_TwoAt
Is S ₁<S_TwoThere is a relationship.

According to the present invention, as shown in FIG.
Since the etching rate of the high aspect ratio wiring pattern 20 becomes faster than the etching rate of the low aspect ratio wiring pattern 21 due to the reverse RIE lag characteristics, the space portion (etching groove) of the high aspect ratio wiring pattern 20 has a lower aspect ratio wiring pattern. The underlying interlayer insulating film 10 is exposed earlier than at 21. At this time, in the low aspect ratio wiring pattern 21, the etching of the wiring material film 13 is not completed. Therefore, the charged particles incident from the pattern side wall and the pattern bottom of the high aspect ratio wiring pattern 20 enter the semiconductor substrate 1 via the etching residue and the contact hole 12 remaining at the etching groove bottom of the low aspect ratio wiring pattern 21. Flow in. As a result, the high aspect ratio wiring pattern 20 does not function as an antenna, and charge-up damage of the gate insulating film 2 due to the antenna effect can be reduced.

[0021]

Embodiments of the dry etching method of the present invention will be described below with reference to the drawings.

(First Embodiment) A dry etching method in a wiring step according to a first embodiment of the present invention will be described.

FIG. 3 is a sectional view of a process when a wiring pattern is formed on a semiconductor substrate having a MOS structure by a dry etching process. In FIG. 3, 1 is a semiconductor substrate, 2 is a gate insulating film, 3 is a gate electrode, 4 is an isolation region, 10 is an interlayer insulating film, 11 is a contact hole connected to the gate electrode 3, and 12 is a semiconductor substrate. the connected contact hole, 13 wiring material film, high aspect ratio resist pattern having a space width S ₁ is 14, 15 low-aspect ratio resist pattern having a space width S _2, 20 is high has a space width S ₁ aspect ratio wiring pattern 21 is a low aspect ratio wiring pattern having a space width S _2. Note that S ₁ and S ₂ have a relationship of S ₁ <S ₂ . The aspect ratio is defined by the wiring film thickness / space width.
The pattern density of the wiring pattern is shown. Assuming that the thickness of the wiring pattern is T ₀ , the aspect ratio of the high aspect ratio wiring pattern 20 is represented by (T ₀ / S ₁ ), and the aspect ratio of the low aspect ratio wiring pattern 21 is (T ₀ / S ₂ ).
It is represented by In other words, this indicates that the pattern density of the high aspect ratio wiring pattern 20 is higher than that of the low aspect ratio wiring pattern 21 when viewed relatively.

Hereinafter, the dry etching method according to the present embodiment will be described in detail. First, as shown in FIG. 3A, after a gate insulating film 2 and a gate electrode 3 are formed on a semiconductor substrate 1, an interlayer insulating film 10 is deposited. Then, contact holes 11 and 12 are formed in the interlayer insulating film 10 by well-known lithography and dry etching. Thereafter, a wiring material film 13 is deposited on the interlayer insulating film 10, and a high aspect ratio resist pattern 14 and a low aspect ratio resist pattern 15 are further formed. The high aspect ratio resist pattern 14 and the low aspect ratio resist pattern wiring pattern 15 are formed separately from each other without being connected to each other.

Next, as shown in FIG.
The wiring material film 13 is dry-etched by applying an etching condition that causes a se RIE lag. As a result, the etching rate of the high aspect ratio wiring pattern 20 is higher than that of the low aspect ratio wiring pattern 21. At this time, charged particles 53 in the plasma are incident from the pattern side wall and the pattern bottom, and these charged particles 53 flow into the semiconductor substrate 1 through the contact holes 12 connected to the semiconductor substrate 1.

When the etching is further advanced, FIG.
As shown in FIG. 7, in the etching region of the high aspect ratio wiring pattern 20 having a high etching rate, the underlying interlayer insulating film 10 is exposed. At this time, in the etching region of the low aspect ratio wiring pattern 21, the wiring material film 13, which is a material to be etched, has not yet disappeared.
Are connected to each other and maintain an electrically connected state. Therefore, the low aspect ratio wiring pattern 21
It is in a state of being grounded to the semiconductor substrate 1 through the contact hole 12. As a result, charged particles 5 incident from the wiring pattern side wall of the high aspect ratio wiring pattern 20
Most of the wirings 3 are made of the wiring material film 13 and the contact holes 1.
2 and is dropped to the semiconductor substrate 1 at the ground potential, so that it does not accumulate on the gate electrode 3. for that reason,
Neither the high aspect ratio wiring pattern 20 nor the low aspect ratio wiring pattern 21 functions as an antenna.

The low aspect ratio wiring pattern 21
In the etching region (at the bottom of the etching groove), the etching is terminated when the wiring material film 13 as the material to be etched is completely removed and the interlayer insulating film 10 is exposed, thereby obtaining a desired pattern shape (FIG. 3 (d)).

An FDDB (Field Dependent Dielectric Break) when the structure shown in FIG. 3A is etched using the etching condition showing the RIE lag characteristic and the etching condition showing the inverse RIE lag characteristic.
down) FIG. 4 shows a comparison of dependence of the yield on the antenna ratio (total area of the wiring pattern side wall / gate area). At the time of measurement, the thickness of the gate insulating film was 3n.
m, gate length 0.25 μm, and gate width 1 μm. Then, a voltage is applied to the gate electrode, and a time when a current of 1E-6 A / cm ² flows between the semiconductor substrate and the gate electrode is regarded as a dielectric breakdown, and the electric field of the gate insulating film at this time is 9 mV / cm or less was regarded as defective. In FIG. 4, the solid line shows the product of the present invention (etching conditions showing the inverse RIE lag characteristics), and the dotted line shows the product of the prior art (R
(Etching conditions showing IE lag characteristics).

As is clear from FIG.
It can be seen that the FDDB yield is better when dry etching is performed under the condition indicating the RIE lag.

In this embodiment, a resist is used as a mask material. However, the same effect can be obtained when a silicon oxide film mask or a silicon nitride mask is used. Although the type of the wiring material is not described, the same effect can be obtained if the wiring material includes at least one of aluminum, aluminum alloy, tungsten, tungsten nitride, titanium, titanium nitride, copper, platinum, and gold.

Second Embodiment Next, a dry etching method in a gate electrode forming step according to a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a process sectional view in the dry etching process of the gate electrode. In FIG. 3, 30 is a semiconductor substrate, 31 is a gate insulating film,
32 polycrystalline silicon layer serving as a gate electrode material, the isolation region 33, high aspect ratio resist pattern having a space width S ₃ is 34, the low-aspect ratio resist pattern 35 having a space width S _4, 36 is a space width S _Three
High aspect ratio gate electrode pattern having a 37 is a low aspect ratio gate electrode pattern having a space width S _4. In the space widths S ₃ and S ₄ , S ₃
<There is a relationship between the S _4. Further, when the thickness of the gate electrode pattern and T _1, the aspect ratio is, the electrode film thickness (T ₁₎
/ Space width. Therefore, the aspect ratio of the high aspect ratio gate electrode pattern 36 is (T ₁ /
S ₃ ), represented by the low aspect ratio gate electrode pattern 3
The aspect ratio of 7 is represented by (T ₁ / S ₄ ). That is,
In comparison, the high aspect ratio gate electrode pattern 36
Indicates that the pattern density is higher than that of the low aspect ratio gate electrode pattern 37.

As shown in FIG.
After depositing the gate insulating film 2 and the polycrystalline silicon 5,
Resist patterns 16 and 17 for forming a gate electrode are formed by lithography. The high aspect ratio resist pattern 34 and the low aspect ratio resist pattern 35 are not connected to each other.

Next, as shown in FIG.
Dry etching is performed by applying an etching condition that causes a rse RIE lag. As a result, the etching rate of the high aspect ratio gate electrode pattern 36 is faster than the etching rate of the low aspect ratio gate electrode pattern 37 (h ₃ <h ₂ ). At this time, the charged particles 53 in the plasma are incident from the pattern side wall and the pattern bottom, and these charged particles 53 flow into the semiconductor substrate 1 and the electrodes of the etching apparatus through the conductive polycrystalline silicon film 32. .

When the etching is further advanced, FIG.
As shown in FIG.
In the etching region (bottom of the etching groove) of the gate electrode pattern 36, the polycrystalline silicon film 32 disappears and the underlying gate insulating film 31 is exposed. At this time, since the etching rate of the low aspect ratio gate electrode pattern 37 is lower in the etching region (the bottom of the etching groove) of the low aspect ratio gate electrode pattern 37 than in the high aspect ratio gate electrode pattern 36, A certain polycrystalline silicon film 32 has not disappeared. Therefore, the charged particles 56 incident on the low aspect ratio gate electrode pattern 37 from the pattern side wall and the pattern bottom in the low aspect ratio gate electrode pattern 37 almost flow through the polycrystalline silicon film 32 and flow into the semiconductor substrate 1 and the electrode of the etching apparatus. .

Also, charged particles incident from the pattern side wall and the pattern bottom of the high aspect ratio gate electrode pattern 36 pass through the remaining portion 38 of the polycrystalline silicon film 32 by the inverse RIE lag, and the semiconductor substrate 30 and the electrodes of the etching apparatus (shown in the figure). (Omitted).

As a result, the pattern side wall and the pattern bottom of the high aspect ratio gate electrode pattern 36 are:
Although acting as an antenna for collecting the charged particles 53, the polycrystalline silicon film 32 constituting the high aspect ratio gate electrode pattern 36 (becomes a high aspect ratio gate electrode)
No charge is accumulated in the Therefore, the gate insulating film 31 located below the polycrystalline silicon film 32 forming the high aspect ratio gate electrode pattern 36 is hardly damaged by the charged charges.

On the other hand, some charge is accumulated in the polycrystalline silicon film 32 (which becomes a gate electrode having a low aspect ratio) constituting the low aspect ratio gate electrode pattern 37. However, since the area of these low aspect ratio gate electrode patterns 37 is relatively large as compared with the amount of charge to be charged, the amount of charge per unit area does not become extremely large. Therefore, the gate insulating film 31 under the low aspect ratio gate electrode pattern 37 is hardly damaged by the charge.

For this reason, the polycrystalline silicon film 32 forming the high aspect ratio gate electrode pattern 36 is formed.
The gate insulating film 31 located below the gate insulating film 31 is not damaged by the charged charges.

Then, in a wide space pattern,
The desired gate electrode pattern is obtained by terminating the etching when the gate insulating film 31 is exposed by removing all the polycrystalline silicon film 32 as the material to be etched (see FIG. 5D).

The result of comparing the antenna ratio dependence of the FDDB yield when the structure shown in FIG. 5D is dry-etched under the etching condition showing the RIE lag characteristic and the etching condition showing the inverse RIE lag characteristic. Is shown in FIG. In this measurement, the thickness of the gate insulating film was 3 nm and the gate length was 0.25 μm.
m, and the gate width was 1 μm. Then, a voltage is applied to the gate electrode, and 1E-6 is applied between the semiconductor substrate and the gate electrode.
The case where a current of A / cm ² flowed was regarded as dielectric breakdown, and the case where the electric field of the gate insulating film was 9 mV / cm or less at this time was regarded as defective. In FIG. 4, the solid line is the product of the present invention (inve
RIE lag characteristic is shown), and the dotted line shows a conventional example (etching condition showing RIE lag characteristic).

As is clear from FIG.
It can be seen that the FDDB yield is better when dry etching is performed under the condition indicating the RIE lag.

The characteristics measurement (FDDB yield) in the first and second embodiments is based on inductively coupled plasma (IC
P: Inductively Coupled Plas
ma) Performed using an etching apparatus.

In each embodiment, a resist is used as a mask material. However, a similar effect can be obtained when a silicon oxide film or silicon nitride is used as a mask.

Although polycrystalline silicon is used as the material to be etched, the same effect can be obtained with amorphous silicon.

The same applies to the case where the gate electrode material is a laminated film of polysilicon and a silicide material such as tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, or a laminated film of the above silicide material and amorphous silicon. The effect is obtained.

Further, when the gate electrode material is a metal film and polysilicon, or a laminated film of a metal film and amorphous silicon, or when the gate electrode material is metal, the metal material is tungsten, tungsten nitride,
The same effect can be obtained by using any of titanium and titanium nitride.

Inverse RI in each embodiment
Examples of the etching conditions showing the E lag characteristics include the following. However, these are inve
It is needless to say that the present invention is only an example of the etching condition showing the rseRIE lag characteristic, and the present invention is not limited to these conditions.

Cl ₂ flow rate 30 sccm HBr flow rate 30 sccm He-О ₂ flow rate 7 sccm (He: О ₂ = 7: 3) Gas pressure 5 mTorr ICP power 200 W RF bias power 200 W Wafer temperature 50 ° C. Especially Cl ₂ When the flow rate ratio is 25-100%
The rss RIE lag characteristic is shown. In the case where the O ₂ flow ratio is in the range of 0 to 30%, inverse RIE
Since the lag characteristic is remarkably exhibited, the inverse RIE lag characteristic is exhibited even under the following conditions.

Cl ₂ flow rate 60 sccm He—O ₂ flow rate 15 sccm (He: O ₂ = 7: 3) Gas pressure 5 mTorr ICP power 200 W RF bias power 200 W Wafer temperature 50 ° C.

[0050]

As described above, according to the present invention, R
Charge-up damage caused by an antenna effect caused by the IE lag can be reduced. As a result, a highly reliable semiconductor device can be manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic diagram for explaining an inverse RIE lag.

FIG. 2 is a schematic view of the behavior of charged particles during overetching when using inverse RIE lag.

FIG. 3 is a process cross-sectional view according to the first embodiment of the present invention.

FIG. 4 is a diagram showing how charge-up damage is reduced according to the first embodiment;

FIG. 5 is a process cross-sectional view according to the second embodiment of the present invention.

FIG. 6 is a diagram showing a charge-up damage recommendation state according to the second embodiment;

FIG. 7 is a schematic diagram showing occurrence of charge-up damage.

FIG. 8 is a graph showing a relationship between a gate insulating film breakdown rate and an antenna ratio.

FIG. 9 is a process sectional view of a conventional example.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 gate insulating film 3 gate electrode 4 isolation region 5 polycrystalline silicon 6 polycrystalline silicon pattern 10 interlayer insulating film 11 contact hole connected to gate electrode 12 contact hole connected to semiconductor substrate 13 wiring material film Reference Signs List 20 high aspect ratio wiring pattern 21 low aspect ratio wiring pattern 36 high aspect ratio gate electrode pattern 37 low aspect ratio gate electrode pattern

Continuation of the front page (72) Inventor Hideo Nakagawa 1-1, Sachimachi, Takatsuki-shi, Osaka, Japan Inside Matsushita Electronics Corporation (72) Inventor Shigenori Hayashi 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics Corporation (72) Inventor Masafumi Kubota 1-1, Yukicho, Takatsuki-shi, Osaka F-term (reference) 4M104 BB01 BB14 BB18 BB30 BB33 CC05 DD65 FF14 FF17 FF18 GG09 GG10 GG14 HH20 5F004 AA06 CA04 DA00 DA04 DA22 DA26 DB02 DB09 DB10 DB12 DB15 DB30 EA06 EA07 EA32 EB02 5F033 HH04 HH05 HH07 HH08 HH09 HH11 HH13 HH18 HH19 HH25 HH27 HH28 HH33 HH34 KK01 MM05 MM07 QQ08 QQ09 QQ13 ECQ EC09 EC07 EC00

Claims (2)

[Claims] 1. A gate electrode on a semiconductor substrate is covered with an interlayer insulating film, and then a wiring pattern is formed on the interlayer insulating film. While the pattern region is mixed, both pattern regions are electrically separated from each other, and the dense pattern region is electrically connected to the gate electrode, and the sparse pattern region is formed on the semiconductor substrate. A method for manufacturing an electrically connected semiconductor device, comprising: after forming a wiring material film on the interlayer insulating film, dry etching under etching conditions in which the higher the pattern density, the higher the etching rate; Forming the wiring pattern by patterning the semiconductor device. 2. A gate electrode pattern in which a pattern region having a low pattern density and a pattern region having a low pattern density coexist, and both pattern regions are electrically separated from each other, is formed on a semiconductor substrate by dry etching. A method of manufacturing a semiconductor device, comprising: forming a gate electrode material film on the semiconductor substrate;
A method of manufacturing a semiconductor device, comprising: forming a gate electrode pattern by patterning the gate electrode material film by dry etching under etching conditions in which an etching rate increases as a pattern density increases.