JP2001230330A - Nonvolatile semiconductor memory and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the device characteristics. SOLUTION: The memory comprises a floating gate 24 formed through a first gate oxide film on a semiconductor substrate 21, erase gate 28 formed through a selective oxide film and a tunnel oxide film on the floating gate 24, side wall oxide film 31 formed so as to cover the floating gate 24, the selective oxide film, the tunnel oxide film, the erase gate 28 and an oxide film, control gate 33 formed through the side wall oxide film 31 and a second gate oxide film formed on the substrate surface layer on one-side walls of the floating gate 24, the selective oxide film, the tunnel oxide film, the erase gate 28 and he oxide film, source region 34 formed adjacent to the floating gate 24, and drain region 37 formed adjacent to the control gate 33.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to a technology for improving characteristics and a miniaturization technology of the nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art An electrically erasable nonvolatile semiconductor memory device in which a memory cell comprises a single transistor, in particular, a programmable ROM (EEPROM: Electronically Erasable an).
In a d Programmable ROM (also referred to as a flash memory), each memory cell is formed by a transistor structure having a floating gate and a control gate.

FIG. 12 is a plan view of a memory cell portion of a nonvolatile semiconductor memory device having such a floating gate and a control gate, and FIG.
It is sectional drawing of the X1 line. This structure is a split gate structure having a memory cell portion in which a control gate 6 is arranged so as to extend from the upper portion to the side portion of the floating gate 4 as shown.

In such a memory cell transistor, data is written by injecting, into the floating gate 4, hot electrons generated in a channel region below the region where the control gate 6 and the floating gate 4 are juxtaposed. Will be And FN conduction
Data is erased by extracting charges from the floating gate 4 to the control gate 6 via the tunnel oxide film 3 by (Fowler-Nordheim tunnelling).

In FIG. 1, a plurality of element isolation films 2 each formed of a LOCOS oxide film selectively formed thick by a LOCOS (Local Oxidation Of Silicon) method are formed in a strip shape in a surface region of a P-type semiconductor substrate 1. And an element region. Floating gate 4 is arranged on semiconductor substrate 1 so as to straddle between adjacent element isolation films 2 via oxide film 3A. This floating gate 4
Are arranged independently for each memory cell. Also,
The selective oxide film 5 on the floating gate 4 is formed thick at the central portion of the floating gate 4 by a selective oxidation method, and makes the upper corner of the floating gate 4 an acute angle. As a result, electric field concentration is likely to occur at the upper corner of the floating gate 4 during the data erasing operation.

A control gate 6 is arranged on a semiconductor substrate 1 on which a plurality of floating gates 4 are arranged via a tunnel oxide film 3 integrated with the oxide film 3A corresponding to each column of the floating gates 4. Is done. The control gate 6 is arranged so that a part thereof overlaps the floating gate 4 and the remaining part is in contact with the semiconductor substrate 1 via the oxide film 3A. The floating gate 4 and the control gate 6 are arranged such that adjacent rows are plane-symmetric with each other.

An N-type drain region 7 and a source region 8 are formed in a substrate region between the control gate 6 and a substrate region between the floating gate 4. The drain region 7 is formed between the control gate 6 and the device isolation film 2.
Are separated from each other, and the source region 8 continues in the direction in which the control gate 6 extends. These floating gate 4, control gate 6, drain region 7 and source region 8 constitute a memory cell transistor.

A metal wiring 10 is arranged on the floating gate 4 and the control gate 6 via an oxide film 9 in a direction crossing the control gate 6. This metal wiring 10 is connected to drain region 7 through contact hole 11. Each control gate 6 becomes a word line, and the source region 8 extending in parallel with the control gate 6 becomes a source line.
The metal wiring 10 connected to the drain region 7 becomes a bit line. The metal wiring 10 is made of an aluminum film (for example, Al, Al-Si, Al-Cu, Al-S
i-Cu film) and the like.
It is formed via a barrier metal film made of an i film, a titanium nitride (TiN) film, or the like. In the metal wiring 10, a tungsten plug made of a W film is buried in the contact hole 11 via a barrier metal film, and an aluminum film (for example, Al, Al—Si, Al) is formed thereon.
—Cu, Al—Si—Cu film) or the like.

In the case of a memory cell transistor having such a structure, the on-resistance between the source and the drain varies depending on the amount of charge injected into the floating gate 4.
Therefore, by selectively injecting electric charges into the floating gate 4, the on-resistance value of a specific memory cell transistor is varied, and the resulting difference in the operating characteristics of each memory cell transistor is made to correspond to the stored data. ing.

The above-described operations of writing, erasing, and reading data in the nonvolatile semiconductor memory device are performed, for example, as follows. In the write operation, the potential of the control gate 6 is 2 V, the potential of the drain region 7 is 0.5 V, and the high potential of the source region 8 is 12 V. By applying a high potential to the source region 8, the potential of the floating gate 4 becomes 9 V due to the coupling ratio between the source region 8 and the floating gate 4.
Hot electrons generated near the channel region below the region where the floating gate 4 and the control gate 6 are juxtaposed are injected into the floating gate 4 through the oxide film 3A to write data.

On the other hand, in the erase operation, the potentials of the drain region 7 and the source region 8 are set to 0 V, and the control gate 6 is set to 14 V. As a result, the electric charges (electrons) accumulated in the floating gate 4 are transferred from the acute angle portion of the upper corner of the floating gate 4 to FN (Fowler).
-Nordheim tunnelling) penetrates through the tunnel oxide film 3 and is released to the control gate 6 to erase data.

In the read operation, the potential of the control gate 6 is set to 4 V and the drain region 7 is set to 2 V.
V and the source region 8 is set to 0V. At this time, if charges (electrons) are injected into the floating gate 4, the potential of the floating gate 4 becomes low, so that no channel is formed below the floating gate 4 and no drain current flows. Conversely, if charges (electrons) have not been injected into the floating gate 4, the potential of the floating gate 4 increases, so that a channel is formed below the floating gate 4 and a cell current (read current) flows.

[0013]

In the nonvolatile semiconductor memory device having the above structure, the following problem occurs because the control gate 6 also has a role as an erase gate.

In other words, it is necessary to apply a high voltage to the control gate 6 at the time of erasing. Therefore, the gate oxide film 3A cannot be made too thin in order to ensure the withstand voltage of the gate oxide film under the control gate 6. Therefore, a large cell current (read current) cannot be obtained. Further, although the read operation and the erase operation are different in the magnitude of the voltage applied to the control gate 6, they are almost the same, so that the floating gate 4 is erroneously read during the read operation. There is a danger that the data inside will be pulled out to the control gate 6 side and erased (hereinafter referred to as a read disturb phenomenon).

Furthermore, since the floating gate 4 and the control gate 6 are formed by mask alignment, there is a problem that a margin for mask misalignment or the like is required and miniaturization is difficult.

[0016]

In view of the above-mentioned problems, a nonvolatile semiconductor memory device of the present invention is formed on a semiconductor substrate 21 via a first gate oxide film 23A as shown in FIG. A floating gate 24, an erase gate 28 formed on the floating gate 24 via a selective oxide film 26 and a tunnel oxide film 27, and the floating gate 24, the selective oxide film 26, the tunnel oxide film 27, the erase gate 28, Sidewall oxide film 31 formed to cover oxide film 29;
1 and the second gate oxide film 23 formed on the surface of the substrate, the floating gate 24, the selective oxide film 2
6, tunnel oxide film 27, erase gate 28 and oxide film 2
9, a control gate 33 formed on one side wall;
It comprises a source region 34 formed adjacent to the floating gate 24 and a drain region 37 formed adjacent to the control gate 33.

Further, as shown in FIG. 2, an opening is formed on a first polysilicon film (floating gate forming film) 24A formed on a semiconductor substrate 21 via a first gate oxide film 23A as shown in FIG. Silicon nitride film 2 having a portion
5 and then, as shown in FIG. 3, the first polysilicon film 24 is formed using the silicon nitride film 25 as a mask.
A is selectively oxidized, and a selective oxide film 26 is formed thereon. Next, as shown in FIG. 4, after removing the silicon nitride film 25, the first polysilicon film 24A is patterned using the selective oxide film 26 as a mask. Further, as shown in FIGS. 5 and 6, a tunnel oxide film 27, a second polysilicon film (erase gate forming film) 28A and an oxide film are formed so as to cover the first polysilicon film 24A and the selective oxide film 26. After laminating 29, as shown in FIG. 7, the oxide film 29, the second polysilicon film 28A, and the resist film 30 formed on the oxide film 29 are used as a mask.
The tunnel oxide film 27, the selective oxide film 26, and the first polysilicon film 24A are patterned to form an oxide film 29, an erase gate 28, the tunnel oxide film 27, the selective oxide film 26, and the floating gate 24. As shown in FIG. 8, the oxide film 29, the erase gate 28, the tunnel oxide film 27, the selective oxide film 26 and the floating gate 24 are formed.
After a sidewall oxide film 31 is formed so as to cover the sidewall portion of the substrate and a substrate surface layer is exposed, a second gate insulating film 23 is formed on the substrate surface layer, and the second gate insulating film 2 is formed.
A control gate 33 is formed so as to cover the oxide film 29, the erase gate 28, the tunnel oxide film 27, the selective oxide film 26, and one side wall of the floating gate 24 via the side wall 3 and the side wall oxide film 31. Then, a source region 34 is formed adjacent to the floating gate 24 as shown in FIG. 10, and a drain region 37 is formed adjacent to the control gate 33 as shown in FIG.
And forming a.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a nonvolatile semiconductor memory device according to the present invention and a method for manufacturing the same will be described with reference to the drawings.

In FIG. 1, LOC is formed on a semiconductor substrate 21.
An element isolation film 22 having a thickness of about 600 nm by the OS method.
To form That is, although illustration is omitted, a pad oxide film and a pad polysilicon film are formed on the semiconductor substrate 21, and the element is selectively oxidized using a silicon nitride film having an opening as a mask and exposed to a portion exposed from the opening. After forming the isolation film 22, the silicon nitride film, the pad polysilicon film and the pad oxide film are removed.

Subsequently, as shown in FIG.
The upper portion is thermally oxidized to form a gate oxide film 2 having a thickness of about 15 nm.
3A, a polysilicon film (floating gate formation film) 24A having a thickness of about 200 nm is formed thereon, and then a silicon nitride film 25 having an opening is formed.

Next, as shown in FIG. 3, selective oxidation is performed by using the silicon nitride film 25 as a mask to form a selective oxide film 26 on the portion of the polysilicon film 24A exposed from the opening. The selective oxide film 26 is formed so that the film thickness becomes maximum at the central portion and becomes thinner toward the peripheral portion. Therefore, the shape of the polysilicon film 24A under the selective oxide film 26 is a so-called The central portion is depressed in a bowl shape, and becomes thin and flat toward the outer peripheral portion (the cross-sectional shape is such that the upper corner portion is thin and sharp).

Subsequently, as shown in FIG. 4, after removing the silicon nitride film 25, the polysilicon film 24A is anisotropically etched using the selective oxide film 26 as a mask to form a polysilicon film 24B.

Further, as shown in FIG. 5, about 20 n of the polysilicon film 24B is covered by the CVD method so as to cover the polysilicon film 24B.
After forming a tunnel oxide film 27 (for example, a TEOS film or an HTO film) having a thickness of m, a polysilicon film (erasing gate forming film) 28A having a thickness of approximately 200 nm After laminating an oxide film 29 (for example, a TEOS film or an HTO film) having a thickness of 50 nm, as shown in FIG. 7, a resist film 30 formed on the oxide film 29 is used as a mask to form the oxide film 29 and polysilicon. Film 28A, tunnel oxide film 27, selective oxide film 26
And the polysilicon film 24B is patterned to form an oxide film 2
9, an erase gate (EG) 28, a tunnel oxide film 27, a selective oxide film 26, and a floating gate 24 (FG) are formed. At this time, a part of the gate oxide film 23 other than the lower part of the floating gate 24 is etched to become a thin oxide film 23B of about 10 nm. At the upper corner of the floating gate 24, a sharp portion 24C that is sharpened upward is formed reflecting the shape of the selective oxide film 26 (see FIG. 7B). FIG. 7 (b) is the same as FIG.
3 is a vertical sectional view of FIG.

As shown in FIG. 8, the oxide film 29,
Erase gate 28, tunnel oxide film 27, selective oxide film 26
And CVD to cover the floating gate 24
Oxide film (for example, TE)
After forming an OS film or an HTO film, the oxide film is anisotropically etched by about 25 nm to form a sidewall oxide film 31 so as to cover those sidewall portions.
The sidewall oxide film 31 is integrated with the oxide films 23B and 29. Then, the entire surface is treated with hydrofluoric acid by about 10 nm to remove the oxide film 23B and expose the surface layer of the substrate.

Subsequently, after the substrate 21 is thermally oxidized to form a gate oxide film 23 having a thickness of about 7 nm, the gate oxide film 23, the sidewall oxide film 31 (the floating gate 24, the selective oxide film 26) are formed. , Tunnel oxide film 27,
A polysilicon film having a thickness of about 300 nm is formed so as to cover the erase gate 28) and the oxide film 29. Further, after the polysilicon film is doped with phosphorus and made conductive, the polysilicon film is anisotropically etched to form the sidewall oxide film 31 (the floating gate 24, the selective oxide film 26, the tunnel oxide film 27, A sidewall conductive film is formed so as to cover the gate 28 and the oxide film 29).
Then, as shown in FIG. 9, the control gate (CG) 33 is formed by using the resist film 32 as a mask and leaving the sidewall conductive film in a predetermined region.

Further, as shown in FIG. 10, an N-type impurity, for example, phosphorus ions is applied to the surface layer of the substrate using the resist film 32 as a mask at a dose of about 4.0 to 5.0 × 10 ¹⁵ / cm ² .
Ion implantation is performed under an implantation condition of an acceleration voltage of 50 to 100 KeV, an annealing process is performed to diffuse the ion,
The source region 34 is formed to a relatively deep position in the substrate so as to be adjacent to the source region 34.

The control gate 33, oxide film 29 (floating gate 24, selective oxide film 2)
6, tunnel oxide film 27, erase gate 28) and side wall oxide film 31 so as to cover about 200
nm-thick oxide film (for example, TEOS film or HT
After forming the O film or the like, the oxide film is anisotropically etched to form a sidewall oxide film 35 so as to cover those sidewall portions as shown in FIG. The sidewall oxide film 35 is integrated with the oxide films 23, 29, 31.

Then, on the source region 34,
N-type impurities on the surface of the substrate using a resist film (not shown) as a mask,
For example, a dose of about 5.0 × 10¹³/ C
m^Two, An accelerating voltage of 40 KeV, and arsenic ions
Dose 5.0 × 10^Fifteen/ Cm ^Two, Acceleration voltage of 50 KeV
Ion implantation under implantation conditions, diffusion by annealing,
The drain region is adjacent to the control gate 33.
The region 37 is formed at a position shallower than the source region 34.
You.

Although not shown in the drawings, a metal wiring is formed in contact with the source region 34 and the drain region 37 via an interlayer insulating film formed on the entire surface to complete the memory cell of the nonvolatile semiconductor memory device. I do.

Here, various operations in the nonvolatile semiconductor memory device having the above structure will be described.

First, at the time of writing, approximately 1 V is applied to the control gate 33, 0 V is applied to the drain region 37 (bit line), approximately 9 V is applied to the source region 34, and approximately 10 V is applied to the erase gate 28. Thus, by applying a high potential to the source region 34 and the erase gate 28, the coupling ratio between the source region 34 and the floating gate 24 and the erase gate 28
The potential of the floating gate 24 is raised to about 11 V by the coupling ratio between the floating gate 24 and the floating gate 24, and hot electrons generated near the channel region below the region where the floating gate 24 and the control gate 33 are juxtaposed are generated. The oxide film 23A
Through the floating gate 24 to write data. At this time, in addition to the potential of the source region 8 in the conventional structure, the potential of the erase gate 28 is added to increase the potential of the floating gate 24, so that the potential of the floating gate 24 can be efficiently increased.

On the other hand, in the erase operation, the erase gate 2
10 is applied to 8 and 0 is applied to the other source region 34, control gate 33, and drain region 37 (bit line).
V is applied. Thereby, the floating gate 24
The electric charges (electrons) stored in the inside of the floating gate 24 are sharpened at the upper corner portion 24C of the floating gate 24 (see FIG. 7B).
Through the tunnel oxide film 27 by FN (Fowler-Nordheim tunnelling) conduction and is released to an upper erase gate 28 to erase data. At this time, in the conventional structure, the thickness under the control gate 6 (the oxide film 3A and the tunnel oxide film 3) could not be reduced, so that the structure is naturally interposed between the floating gate 4 and the control gate 6 serving as an erase gate. Although the thickness of the tunnel oxide film 3 was also large, in the present structure, the thickness of each of the (gate oxide film 23 and tunnel oxide film 27) can be set independently, so that the gap between the erase gate 28 and the floating gate 24 is provided. The thickness of the interposed tunnel oxide film 27 can also be set to an appropriate thickness. Therefore, the same current can be obtained even when the voltage applied to the erase gate 28 is lowered (14 V is applied to the control gate in the conventional structure → in the present structure,
10 V across erase gate 28 as described above.

In the read operation, 0 V is applied to the source region 34 and the erase gate 28, approximately 2 V is applied to the control gate 33, and the drain region 3
7 (bit line) is applied with 1V. At this time, if charges (electrons) are injected into the floating gate 24,
Since the potential of the floating gate 24 decreases, no channel is formed below the floating gate 24 and no drain current flows. Conversely, floating gate 2
If no charge (electrons) is injected into 4, the potential of the floating gate 24 increases, so that a channel is formed below the floating gate 24 and a cell current (read current) flows. Further, since the thickness of the gate oxide film 23 under the control gate 33 is formed to be thinner than the conventional structure, the same current can be obtained even when the voltage applied to the control gate 33 is reduced.

As described above, in the nonvolatile semiconductor memory device of the present invention, as shown in FIG. 11, a floating gate 24 and an erase gate 28 formed thereon via a selective oxide film 26 and a tunnel oxide film 27 as shown in FIG. And the control gate 33 formed on one side wall of the gates 24 and 28, the thickness of the gate oxide film 23 and the thickness of the tunnel oxide film 27 can be set independently. .

Therefore, the risk of occurrence of the read disturb phenomenon is reduced, and the thickness of the gate oxide film 23 below the control gate 33 can be reduced. Therefore, the cell current (read current) can be increased, and the cell threshold can be lowered. As a result, a read operation by applying a low voltage becomes possible.

Further, the voltage between the control gate 33 and the floating gate 24 at the time of the write operation can be increased as compared with the conventional structure. The write efficiency can be increased because the write current can be increased by both the potential of the source region 28 and the potential of the source region 34, and the write current can flow with a low control voltage. Therefore, a rewriting operation by applying a low voltage becomes possible.

Also, in the cells of the same source which are paired on the opposite side to the write side, by setting the voltage of the erase gate to 0 V, the potential of the floating gate decreases,
Disturbance (erroneous writing) can be reduced.

Further, since the risk of the read disturb phenomenon is reduced, the thickness of the tunnel oxide film 27 can be made smaller than before, and an erasing operation by applying a low voltage to the erasing gate 28 becomes possible. Therefore, the number of times of data rewriting can be improved. This is because the probability that charges (electrons) are trapped in the tunnel oxide film is reduced by reducing the film thickness.

As described above, according to the structure of the present invention, the voltage can be reduced in all the operations (read, rewrite, and erase), so that the peripheral circuits can be miniaturized.

Further, in the manufacturing method of the present invention, since the erase gate 28 and the control gate 33 can be formed in a self-alignment manner, it is effective for miniaturization.

In this embodiment, the floating gate 2 patterned by using the selective oxide film 26 as a mask is used.
Although the nonvolatile semiconductor memory device having the four structures has been described, the present invention may be applied to a nonvolatile semiconductor memory device having a floating gate structure in which a conductive film made of a polysilicon film or the like is patterned using a resist film as a mask.

[0042]

According to the present invention, a structure comprising a floating gate, an erase gate formed on the floating gate via a tunnel oxide film, and a control gate formed on one side wall of these gates is employed. Thus, the thicknesses of the gate oxide film and the tunnel oxide film can be set independently, and the voltage can be reduced in various operations.

Since the voltage between the control gate and the floating gate during the write operation can be increased as compared with the conventional structure, the write efficiency can be increased.

Further, according to the manufacturing method of the present invention, since the erase gate and the control gate can be formed in a self-aligned manner, miniaturization is possible.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a method for manufacturing a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a method for manufacturing a nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 3 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 4 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 5 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 6 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 7 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 8 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 9 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 10 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 11 is a sectional view illustrating the method of manufacturing the nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 12 is a plan view showing a conventional nonvolatile semiconductor memory device.

FIG. 13 is a sectional view showing a conventional nonvolatile semiconductor memory device.

Continued on the front page F-term (reference) 5F001 AA21 AA22 AA26 AA32 AB03 AB07 AC02 AC06 AC20 AD16 AD41 AD52 AD62 AE02 AE03 AE08 AF06 AF10 AG02 AG12 AG22 AG24 AG30 5F083 EP15 EP25 EP30 ER02 ER09 ER14 ER18 ER22 BA30 BA04 BA045 BB09 BC02 BC03 BC11 BD06 BD22 BD33 BD37 BE02 BE05 BE07 BF02 BF10 BH03 BH04 BH07 BH09 BH16

Claims (4)

[Claims] A floating gate formed on a semiconductor substrate via a gate insulating film; an erase gate formed on the floating gate via an insulating film; and covering the floating gate, the insulating film and the erase gate. A control gate formed on one side wall of the floating gate, the insulating film and the erase gate via an insulating film formed so as to be formed on the surface of the substrate adjacent to the floating gate or the control gate; A nonvolatile semiconductor memory device having a diffusion region. 2. The method according to claim 1, further comprising:
2. The nonvolatile semiconductor memory device according to claim 1, wherein a selective oxide film formed by a selective oxidation method is formed, and a sharp portion is formed at an upper corner thereof. 3. A step of forming a first conductive film on a semiconductor substrate via a first gate insulating film; and forming an insulating film, a second conductive film, and an insulating film so as to cover the first conductive film. Stacking a film, and patterning the insulating film, the second conductive film, the insulating film and the first conductive film using the resist film formed on the insulating film as a mask, and forming an insulating film, an erase gate, an insulating film, Forming a floating gate, forming a side wall insulating film so as to cover the insulating film, the erase gate, the insulating film and the side wall of the floating gate, and exposing a substrate surface layer; Forming a control gate on one side wall of the floating gate, the insulating film, and the erase gate via the second gate insulating film after forming the gate insulating film; Or a method of manufacturing a nonvolatile semiconductor memory device characterized by a step of forming the substrate surface layer diffusion region so as to be adjacent to the control gate. 4. A step of forming an oxidation-resistant film having an opening on a first conductive film formed on a semiconductor substrate via a first gate insulating film, and using the oxidation-resistant film as a mask. Selectively oxidizing the first conductive film to form a selective oxide film thereon, and after removing the oxidation-resistant film, patterning the first conductive film using the selective oxide film as a mask A step of stacking an insulating film, a second conductive film and an insulating film so as to cover the first conductive film and the selective oxidation film; and a step of using the resist film formed on the insulating film as a mask to form the insulating film. Forming an insulating film, an erase gate, an insulating film, a selective oxide film, and a floating gate by patterning the first conductive film, the second conductive film, the insulating film, the selective oxide film, and the first conductive film; , Insulating film, selective oxide film and float Anisotropically etching the insulating film after forming the insulating film so as to cover the insulating gate, forming a side wall insulating film so as to cover those side walls, and exposing the substrate surface layer; After a second gate insulating film is formed, the insulating film, the erase gate,
After forming a third conductive film so as to cover the insulating film, the selective oxide film, the floating gate, and the side wall insulating film, the third conductive film is anisotropically etched to cover those side walls. A step of forming a sidewall conductive film; a step of forming a control gate made of the sidewall conductive film by etching and removing the sidewall conductive film other than a predetermined region using a resist film as a mask; Forming a diffusion region in the surface layer of the substrate as described above.