JPH08306808A - Nonvolatile semiconductor memory device - Google Patents

Abstract

(57) [Summary] [Object] In a non-volatile semiconductor memory device, a threshold voltage variation among memory cells is suppressed, and the threshold voltage of the memory cells is increased. In the floating gate type nonvolatile semiconductor memory device, an insulating film 6 is formed on the floating gate 5.
The first control gate 7 is provided via the first control gate 7, and the second control gate 9 is provided on the first control gate 7 via the insulating film 8. At the time of writing, writing is performed by selecting the first control gate 7 or the second control gate 9 and applying a voltage. In the MONOS-type or MNOS-type non-volatile semiconductor memory device, the second gate electrode is provided over the first gate electrode with an insulating film interposed therebetween. At the time of writing, writing is performed by selecting the first gate electrode or the second gate electrode and applying a voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and is particularly suitable for application to a floating gate type nonvolatile semiconductor memory device and a MONOS type or MNOS type nonvolatile semiconductor memory device. .

[0002]

2. Description of the Related Art At present, so-called flash EEPROMs are used.
Non-volatile semiconductor memory devices such as are increasing their capacity with the goal of replacing magnetic disk devices used as external memory devices such as computers, but this increasing capacity lowers the bit unit price. To
It is required to be realized by increasing the threshold voltage of memory cells (memory transistors).

Conventionally, the multi-threshold voltage of this memory cell is changed by changing the injection time or the extraction time of electrons.

[0004]

However, the conventional method of changing the injection time or the withdrawal time of electrons as described above to make the memory cells have a multi-threshold voltage is as follows. There are problems that it is difficult to suppress variations and that it is difficult to manufacture a memory cell used as a reference at the time of reading.

Therefore, an object of the present invention is to set the threshold voltage of a memory cell in three steps and to suppress variations in the threshold voltage between memory cells, which is used as a reference at the time of reading. It is an object of the present invention to provide a nonvolatile semiconductor memory device in which memory cells can be easily manufactured.

[0006]

In order to achieve the above object, a nonvolatile semiconductor memory device according to the first invention of the present invention includes a floating gate provided on a semiconductor substrate via a gate insulating film, and a floating gate. A first control gate provided on the gate via the first insulating film, and a second control gate provided on the first control gate via the second insulating film. It is what

In the first aspect of the present invention, writing is performed by selecting the first control gate or the second control gate at the time of writing and applying a predetermined voltage.

A non-volatile semiconductor memory device according to a second aspect of the present invention is a gate insulating film formed of an oxide film and a nitride film, which is sequentially provided on a semiconductor substrate, and a first gate provided on the gate insulating film. It is characterized in that it has an electrode and a second gate electrode provided on the first gate electrode via an insulating film.

In the second aspect of the present invention, writing is performed by selecting the first gate electrode or the second gate electrode at the time of writing and applying a predetermined voltage.

In the second invention of the present invention, typically, the oxide film is a silicon dioxide (SiO ₂ ) film and the nitride film is a silicon nitride (Si ₃ N ₄ ) film.

A nonvolatile semiconductor memory device according to a third aspect of the present invention is a gate insulating film formed of a first oxide film, a nitride film and a second oxide film, which are sequentially provided on a semiconductor substrate, and a gate insulating film. A first gate electrode provided above,
It has a second gate electrode provided over the first gate electrode with an insulating film interposed therebetween.

In the third aspect of the present invention, writing is performed by selecting the first gate electrode or the second gate electrode at the time of writing and applying a predetermined voltage.

In the third invention of the present invention, typically, the first oxide film and the second oxide film are SiO ₂ films, and the nitride film is a Si ₃ N ₄ film.

In the present invention, the non-volatile semiconductor memory device is, for example, an electrically batch-erasable non-volatile semiconductor memory device, that is, a so-called flash EEPROM, or an EPROM.

[0015]

According to the nonvolatile semiconductor memory device of the first aspect of the present invention, the capacitance between the semiconductor substrate and the floating gate, the capacitance between the floating gate and the first control gate, and the first control gate. The capacitance between the second control gate and the first
Of the memory cell depending on whether the write operation is performed by selecting the control gate of the second control gate and applying a predetermined voltage, and the write operation is performed by selecting the second control gate and applying the predetermined voltage. The threshold voltages are different from each other. Therefore, writing is performed by the erased state, when writing is performed by selecting the first control gate and applying a predetermined voltage, and when writing is performed by selecting the second control gate and applying a predetermined voltage. Depending on the case, the threshold voltage of the memory cell can be set in three steps. Further, in this case, it is possible to suppress variations in threshold voltage between memory cells, and it is easy to manufacture a memory cell that serves as a reference during reading.

According to the nonvolatile semiconductor memory device in accordance with the second and third aspects of the present invention, the capacitance between the semiconductor substrate and the first gate electrode and the first gate electrode and the second gate electrode. Depending on the capacitance between and, writing is performed by selecting the first gate electrode and applying a predetermined voltage, and by writing the data by selecting the second gate electrode and applying a predetermined voltage. The threshold voltage of the memory cell is different from that of the case. Therefore,
In the erased state, when writing is performed by selecting the first gate electrode and applying a predetermined voltage, and when writing is performed by selecting the second gate electrode and applying a predetermined voltage With, the threshold voltage of the memory cell can be set in three steps. Further, in this case, it is possible to suppress variations in threshold voltage between memory cells, and it is easy to manufacture a memory cell that serves as a reference during reading.

[0017]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention, and particularly shows a portion of one memory cell (memory transistor) thereof. Here, FIG. 1A is a sectional view parallel to the channel length direction, and FIG. 1B is a sectional view parallel to the channel width direction.

As shown in FIG. 1, in this nonvolatile semiconductor memory device, for example, a p-type silicon (Si) substrate 1 is used.
A field insulating film 2 such as a SiO ₂ film is formed on the surface of the
Are selectively provided, whereby element isolation is performed. In the lower portion of the field insulating film 2, for example, a p ⁺ type channel stop region 3 is provided.

A gate insulating film 4 such as a SiO ₂ film is provided on the surface of the active region surrounded by the field insulating film 2. A floating gate 5 is provided on the gate insulating film 4. Both ends of the floating gate 5 in the channel width direction straddle the field insulating film 2. Here, the floating gate 5 is made of, for example, a polycrystalline Si film doped with an impurity such as phosphorus (P).

On the floating gate 5, for example, S
A film having a three-layer structure of an iO ₂ film, a Si ₃ N ₄ film, and a SiO ₂ film, that is, an insulating film 6 made of a so-called ONO film is provided. Then, the first control gate 7 is provided on the floating gate 5 via the insulating film 6. The first control gate 7 extends in the channel width direction so as to cover the floating gate 5. Here, this first control gate 7
Is a polycrystalline S doped with an impurity such as P.
It consists of an i-membrane.

An insulating film 8 made of, for example, an ONO film is provided on the first control gate 7. Then, a second control gate 9 is provided on the first control gate 7 via the insulating film 8.
The second control gate 9 extends in the channel width direction so as to cover the portion of the first control gate 7 excluding one end in the channel width direction. Here, the second control gate 9 has a structure in which a refractory metal silicide film such as a tungsten silicide (WSi ₂ ) film is laminated on a polycrystalline Si film doped with an impurity such as P. It consists of a so-called polycide film.

In this case, the floating gate 5, the first control gate 7 and the second control gate 9 described above have the same width in the channel length direction.

In addition, in the active region surrounded by the field insulating film 2, for example, an n ⁺ type source is self-aligned with the floating gate 5, the first control gate 7 and the second control gate 9. A region 10 and a drain region 11 are provided. The floating gate 5, the first control gate 7 and the second control gate 9 and their source region 10 and drain region 11 constitute a memory transistor.

In practice, an interlayer insulating film covering the second control gate 9, the first control gate 7, etc., a contact hole for this interlayer insulating film, a metal wiring, a passivation film, etc. are provided. Illustration and description thereof are omitted.

Next, the operation of the non-volatile semiconductor memory device according to the first embodiment constructed as described above will be described.

In FIG. 1, the capacitance between the p-type Si substrate 1 and the floating gate 5 is C ₁ , the capacitance between the floating gate 5 and the first control gate 7 is C ₂ , and the first control is The capacitance between the gate 7 and the second control gate 9 is C ₃ . Further, the voltage applied between the p-type Si substrate 1 and the floating gate 5 is V ₁ , the voltage applied between the floating gate 5 and the first control gate 7 is V ₂ , and the first control gate is The voltage applied between 7 and the second control gate 9 is V ₃ .

Here, for example, when the p-type Si substrate 1 is grounded, the voltage V is applied to the first control gate 7, and the second control gate 9 is made floating, V ₁ = [(1 / C ₁ ) / (1 / C ₁ + 1 / C ₂ )] V (1).

When the p-type Si substrate 1 is grounded, the voltage V'is applied to the second control gate 9, and the first control gate 7 is set in a floating state, V ₁ = [(1 / C ₁ ) / (1 / C ₁ + 1 / C ₂ + 1 / C ₃ )] V ′ (2).

As can be seen from the equations (1) and (2), the p-type is obtained when the voltage V is applied to the first control gate 7 and when the voltage V'is applied to the second control gate 9. The voltage V ₁ applied between the Si substrate 1 and the floating gate 5 is different, and therefore when the voltage V is applied to the first control gate 7 and when the voltage V ′ is applied to the second control gate 9. Can change the electron injection efficiency or the electron extraction efficiency. Therefore, the first control gate 7 and the second control gate 7
Even if the voltage is applied to the control gate 9 of the same time,
The memory cells have different threshold voltages.

Therefore, in the erased state, when the first control gate 7 is selected and the voltage V is applied,
The threshold voltage of the memory cell can be set to three levels depending on whether the control gate 9 is selected and the voltage V ′ is applied.

The capacitance C ₁ between the p-type Si substrate 1 and the floating gate 5 is determined by the gate insulating film 4 between them.
Floating gate 5 determined by the area and thickness of
The capacitance C ₂ between the first control gate 7 and the first control gate 7 is determined by the area and thickness of the insulating film 6 between them, and the capacitance C ₂ between the first control gate 7 and the second control gate 9 is determined. ₃ is determined by the area and thickness of the insulating film 8 between them. In order to set the threshold voltage of the memory cell to a desired value, the thickness of the gate insulating film 4, the insulating film 6 and the insulating film 8, the element isolation width, the floating gate 5 and the first control are set. The overlap between the gate 7 and the overlap between the first control gate 7 and the second control gate 9 may be optimized to secure the required capacitance.

Based on the above, the write operation and read operation of the non-volatile semiconductor memory device according to the first embodiment will be described as follows.

Now, assume that electrons are injected into the floating gate 5 in the erased state, and this state is made to correspond to information "0", for example. Further, the state in which electrons are extracted from the floating gate 5 is associated with, for example, the information “2”. Then, an intermediate state between these, that is, a state in which a predetermined amount of electrons are extracted from the floating gate 5 is made to correspond to, for example, information "1". Here, the threshold voltage of the memory cell is, for example, +6 V when the information “0” is written, +4 V when the information “1” is written, and + 1.V when the information “2” is written. It is assumed to be 5V.

First, when writing the information "2", a predetermined negative voltage, for example -6, is applied to the first control gate 7.
V is applied, and a predetermined positive voltage, for example, + 12V is applied to the drain region 11. The second control gate 9 is floating and the source region 10 is grounded. At this time, from the floating gate 5 to the drain region 11
Electrons are drawn into the memory cell and the threshold voltage of the memory cell is +6
It is set to V, which causes the information "2" to be written. When writing the information "1", a predetermined negative voltage, for example, -6V is applied to the second control gate 9, and a predetermined positive voltage, for example, + 12V is applied to the drain region 11. The first control gate 7 is floating and the source region 10 is grounded. At this time, a predetermined amount of electrons are extracted from the floating gate 5 to the drain region 11 and the threshold voltage of the memory cell is set to + 4V, whereby the information "1" is written.

Next, at the time of reading, for example, first, the threshold voltage (= + 1.5) of the memory cell when the information “2” is written in the first control gate 7.
A predetermined positive voltage, for example + 3V, which is higher than V) and lower than the threshold voltage (= + 4V) of the memory cell when the information “1” is written is applied. The second control gate 9 is floated, the source region 10 is grounded, and a predetermined positive voltage is applied to the drain region 11.
In this case, when the information “2” is written in the memory cell, the memory transistor is turned on and the read current flows, but the information “0” or the information “1” is written in the memory cell.
When is written, the memory transistor does not turn on and no read current flows. Therefore, the read current flows when + 3V is applied to the first control gate 7, whereby the information “2” can be read.

When a read current does not flow when + 3V is applied to the first control gate 7, whether the information "1" or the information "0" is written in the memory cell as it is. Is unknown. Therefore, next, in the second control gate 9, the threshold voltage of the memory cell when the information “1” is written is higher than the threshold voltage of the memory cell, and the memory cell when the information “0” is written is selected. A predetermined positive voltage lower than the threshold voltage,
For example, + 5V is applied. Second control gate 9
Is floating, the source region 10 is grounded, and a predetermined positive voltage is applied to the drain region 11. in this case,
Information "1" can be read when the memory transistor is turned on and a read current flows, while information "0" can be read when the memory transistor is not turned on and a read current does not flow.

Next, a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment will be described.

2 to 9 are sectional views showing a method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment in the order of steps. Here, FIGS. 2A and 2B are cross-sectional views corresponding to FIGS. 1A and 1B, respectively. The same applies to FIGS. 3 to 9.

In the method of manufacturing the nonvolatile semiconductor memory device according to the first embodiment, first, as shown in FIG.
A field insulating film 2 made of a SiO ₂ film is selectively formed on the surface of the p-type Si substrate 1 by a thermal oxidation method to perform element isolation, and a channel stop region 3 is formed below the field insulating film 2. To form. After that, the gate insulating film 4 made of a SiO ₂ film is formed on the surface of the active region surrounded by the field insulating film 2 by, for example, a thermal oxidation method.

Next, as shown in FIG. 3, a polycrystalline Si film 12 is formed on the entire surface by, for example, a CVD method, and the polycrystalline Si film 12 is further doped with an impurity such as P by an ion implantation method or a thermal diffusion method. Then, the polycrystalline Si film 12 doped with the impurities is patterned by, for example, a reactive ion etching (RIE) method to have a predetermined shape whose width in the channel width direction is equal to that of the floating gate 5. .

Next, the insulating film 6 made of an ONO film is formed on the polycrystalline Si film 12 thus patterned. Here, Si of the ONO film forming the insulating film 6
The O ₂ film is formed by the thermal oxidation method, and the Si ₃ N ₄ film is formed under reduced pressure C
It is formed by the VD method.

Next, a polycrystalline Si film 13 is formed on the entire surface by, for example, the CVD method, and the polycrystalline Si film 13 is further doped with an impurity such as P by an ion implantation method or a thermal diffusion method to reduce the resistance. After that, the polycrystalline Si film 13 doped with the impurities is patterned by, for example, RIE, and the width in the channel width direction is the first control gate 7.
To be equal to.

Next, the insulating film 8 made of an ONO film is formed on the polycrystalline Si film 13 thus patterned. Here, Si of the ONO film forming the insulating film 8
The O ₂ film is formed by the thermal oxidation method, and the Si ₃ N ₄ film is formed under reduced pressure C
It is formed by the VD method.

Next, a polycrystalline Si film is formed on the entire surface by, for example, the CVD method, and then the polycrystalline Si film is doped with an impurity such as P by an ion implantation method or a thermal diffusion method to reduce the resistance. , Polycrystalline S doped with this impurity
For example, WSi _{2 is formed} on the i film by, for example, a sputtering method.
A refractory metal silicide film such as a film is formed, and a polycide film 14 including these polycrystalline Si film and refractory metal silicide film is formed. Then, a resist pattern 15 is formed on the polycide film 14 by a lithography method.
To form. Here, the resist pattern 15 is formed on the floating gate 5 and the first gate in the channel length direction.
Has the same width as the control gate 7 and the second control gate 9 of
It has the same width as the control gate 9 of.

Next, using the resist pattern 15 as a mask, the polycide film 14 is patterned by, eg, RIE. As a result, the second control gate 9 is formed as shown in FIG.

Next, as shown in FIG. 5, the polycrystalline Si film 1
After forming a resist pattern 16 having a predetermined shape by a lithography method so as to cover one end in the channel width direction that is not covered by the second control gate 9 among the three, the resist pattern 15 and this resist pattern 16 are used as a mask. For example, the insulating film 8 is patterned by the RIE method.

Next, the polycrystalline Si film 13 is patterned by the RIE method using the resist patterns 15 and 16 as masks. As a result, the first control gate 7 is formed as shown in FIG.

Next, as shown in FIG. 7, the insulating film 6 is patterned by the RIE method using the resist patterns 15 and 16 as masks.

Next, the polycrystalline Si film 12 is patterned by, eg, RIE using the resist pattern 15 and the resist pattern 16 as masks. As a result, the floating gate 5 is formed as shown in FIG.

Next, as shown in FIG. 9, n-type impurities such as arsenic (As) and P are ion-implanted into the active region by using the resist pattern 15 and the resist pattern 16 as masks, for example, n ⁺ -type A source region 10 and a drain region 11 are formed. These source region 10 and drain region 11 are formed in the channel length direction in self-alignment with floating gate 5, first control gate 7 and second control gate 9.

Next, after removing the resist pattern 15 and the resist pattern 16 and further performing a heat treatment for electrically activating the implanted impurities, a necessary process such as an interlayer insulating film, a contact hole, The target nonvolatile semiconductor memory device is completed through the formation of metal wiring and passivation film.

As described above, according to this first embodiment,
The first control gate 7 is provided on the floating gate 5 via the insulating film 6, and the second control gate 9 is provided on the first control gate 7 via the insulating film 8. Since the writing is performed by selecting the first control gate 7 or the second control gate 9 and applying the voltage, the threshold voltage of the memory cell can be set in three steps. That is, it is possible to increase the threshold voltage of the memory cell. Further, in this case, unlike the conventional method of realizing a multi-threshold voltage by changing the electron injection time or the electron extraction time, it is possible to suppress the variation in the threshold voltage between memory cells, and It is easy to manufacture a memory cell used as a reference.

Next, a second embodiment of the present invention will be described.

FIG. 10 is a sectional view showing the non-volatile semiconductor memory device according to the second embodiment, and particularly shows a portion of one memory cell (memory transistor) thereof. Here, FIG. 10A is a sectional view parallel to the channel length direction, and FIG. 10B is a sectional view parallel to the channel width direction.

As shown in FIG. 10, in this non-volatile semiconductor memory device, a field insulating film 22 such as a SiO ₂ film is selectively provided on the surface of a p-type Si substrate 21, thereby separating elements. Is performed, and, for example, p on the lower side of the field insulating film 22.
^{A +} type channel stop region 23 is provided. The above is the same as the nonvolatile semiconductor memory device according to the first embodiment.

In the second embodiment, the gate insulating film 24 made of an ONO film is provided on the surface of the active region surrounded by the field insulating film 22. A first gate electrode 25 is provided on the gate insulating film 24. Both ends of the first gate electrode 25 in the channel width direction straddle the field insulating film 22. Here, the first gate electrode 25 is made of, for example, a polycrystalline Si film doped with an impurity such as P.

On the first gate electrode 25, for example, ON
An insulating film 26 made of an O film is provided. Then, the second film is formed on the first gate electrode 25 through the insulating film 26.
Gate electrode 27 is provided. The second gate electrode 27 extends in the channel width direction so as to cover the portion of the first gate electrode 25 excluding one end in the channel width direction. Here, the second gate electrode 27 is made of, for example, a polycide film having a structure in which a refractory metal silicide film such as a WSi ₂ film is laminated on a polycrystalline Si film doped with an impurity such as P. .

In this case, the above-mentioned first gate electrode 25 and second gate electrode 27 have the same width in the channel length direction.

In the active region surrounded by the field insulating film 22, for example, an n ⁺ type source region 28 and drain are self-aligned with the first gate electrode 25 and the second gate electrode 27. A region 29 is provided.
Then, the first gate electrode 25 and the second gate electrode 27 and their source region 28 and drain region 29 are formed.
A memory transistor is constituted by and.

In practice, the second gate electrode 27,
Although an interlayer insulating film covering the first gate electrode 25 and the like, a contact hole of this interlayer insulating film, a metal wiring, a passivation film, and the like are provided, their illustration and description are omitted.

In the operation of the non-volatile semiconductor memory device according to the second embodiment having the above-described structure, the first gate electrode 25 corresponds to the first control gate 7, and the second gate electrode 25 corresponds to the second control gate 7.
The description of the non-volatile semiconductor memory device according to the first embodiment will be omitted if the gate electrode 27 of the second embodiment corresponds to the second control gate 9. The method of manufacturing the non-volatile semiconductor memory device according to the second embodiment is also the same as the method of manufacturing the non-volatile semiconductor memory device according to the first embodiment, and a description thereof will be omitted.

According to the second embodiment, the same advantages as those of the first embodiment can be obtained in the MONOS type nonvolatile semiconductor memory device.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the technical idea of the present invention.

For example, the numerical values given in the above-mentioned first embodiment are merely examples, and the present invention is not limited to these numerical values.

The portions of the p-type Si substrates 1 and 21 in the above-mentioned first and second embodiments may be p-wells formed in the Si substrate.

Further, in the above-mentioned second embodiment, M
The case where the present invention is applied to the ONOS type non-volatile semiconductor memory device has been described, but the present invention can also be applied to the MNOS type non-volatile semiconductor memory device.

[0068]

As described above, according to the first aspect of the present invention, in the floating gate type nonvolatile semiconductor memory device, the threshold voltage of the memory cell can be set in three stages. Moreover, it is possible to suppress variations in threshold voltage between memory cells, and it is easy to manufacture a memory cell used as a reference during reading.

According to the second and third aspects of the present invention, in the MONOS type or MNOS type non-volatile semiconductor memory device, the threshold voltage of the memory cell can be set in three steps, and Variations in threshold voltage between memory cells can be suppressed, and a memory cell used as a reference at the time of reading can be easily manufactured.

[Brief description of drawings]

FIG. 1 is a sectional view showing a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a cross sectional view for illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a cross sectional view for illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a cross sectional view for illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a cross sectional view for illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a cross sectional view for illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 7 is a cross sectional view for illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 8 is a sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 9 is a cross sectional view for illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention.

FIG. 10 is a sectional view showing a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

[Explanation of symbols]

 1, 21 p-type Si substrate 2, 22 field insulating film 4, 24 gate insulating film 5 floating gate 6, 8, 26 insulating film 7 first control gate 9 second control gate 10, 28 source region 11, 29 drain Region 25 First gate electrode 27 Second gate electrode

Claims (6)

[Claims] 1. A floating gate provided on a semiconductor substrate via a gate insulating film, a first control gate provided on the floating gate via a first insulating film, and the first control. A non-volatile semiconductor memory device having a second control gate provided over the gate with a second insulating film interposed therebetween. 2. The non-volatile memory according to claim 1, wherein writing is performed by selecting the first control gate or the second control gate at the time of writing and applying a predetermined voltage. Semiconductor memory device. 3. A gate insulating film made of an oxide film and a nitride film, which is sequentially provided on a semiconductor substrate, a first gate electrode provided on the gate insulating film, and an insulation on the first gate electrode. And a second gate electrode provided through a film. 4. The non-volatile memory according to claim 3, wherein the writing is performed by selecting the first gate electrode or the second gate electrode at the time of writing and applying a predetermined voltage. Semiconductor memory device. 5. A gate insulating film formed of a first oxide film, a nitride film, and a second oxide film, which are sequentially provided on a semiconductor substrate, and a first gate electrode provided on the gate insulating film. A nonvolatile semiconductor memory device, comprising: a second gate electrode provided on the first gate electrode via an insulating film. 6. The nonvolatile memory according to claim 5, wherein writing is performed by selecting the first gate electrode or the second gate electrode at the time of writing and applying a predetermined voltage. Semiconductor memory device.