JP2001203125A - Multilayer capacitors, wiring boards, decoupling circuits and high frequency circuits - Google Patents

Abstract

(57) [Summary] [Problem] A multilayer capacitor for which low ESL is achieved is realized by M
Provided is a preferred implementation when used as a decoupling capacitor connected to a power supply circuit for an MPU chip provided in a PU. SOLUTION: A cavity 6 provided in a wiring board 62.
6 houses the multilayer capacitor 41. The multilayer capacitor 41 includes a plurality of first through conductors 4 on the first internal electrode 44.
And a plurality of second external terminal electrodes 51 connected to the plurality of first external terminal electrodes 49 and the second internal electrodes 45 via the plurality of second through conductors 47. The first external terminal electrode 49 is provided on the first main surface 48 of the capacitor body 43, is connected to the power supply hot via-hole conductor 70 in the wiring board 62, and the second external terminal electrode 51 is 2 and is directly grounded to the motherboard 67.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer capacitor, a wiring board, a decoupling circuit, and a high-frequency circuit, and more particularly, to a multilayer capacitor which can be advantageously applied to a high-frequency circuit, and constituted by using the multilayer capacitor. A wiring board, a decoupling circuit, and a high-frequency circuit.

[0002]

2. Description of the Related Art The most typical conventional multilayer capacitor is made of, for example, a ceramic dielectric, and has a plurality of dielectric layers to be laminated, and a specific dielectric layer interposed therebetween to form a plurality of capacitor units. The capacitor body includes a plurality of pairs of first and second internal electrodes that are arranged to face each other and are alternately arranged in the stacking direction of the dielectric layers. First and second external terminal electrodes are formed on the first and second end faces of the capacitor body, respectively. The first internal electrode extends over a first end surface of the capacitor body, where it is electrically connected to a first external terminal electrode, and the second internal electrode extends over a second end surface. Extend here and are electrically connected to the second external terminal electrode.

In this multilayer capacitor, for example, a current flowing from the second external terminal electrode to the first external terminal electrode flows from the second external terminal electrode to the second internal electrode, and the second internal electrode Through the dielectric layer to the first internal electrode, and then through the inside of the first internal electrode to the first external terminal electrode.

In an equivalent circuit of a capacitor, CLR is connected in series, where C is the capacitance of the capacitor, L is the equivalent series inductance (ESL), and R is the resistance of the electrode mainly called equivalent series resistance (ESR). It is represented by a circuit.

In this equivalent circuit, the resonance frequency (f₀)
Is f₀= 1 / [2π × (L × C)^{1 / Two}] And resonance
Do not function as a capacitor at frequencies higher than
It becomes. In other words, if L or ESL value is small
If the resonance frequency (f₀) Is higher and used at higher frequencies
You can do it. In addition, ESR is performed by using copper for the internal electrode.
Although it is considered to reduce the
In order to use in the area, a capacitor with low ESL
Required.

A microprocessing unit (MP) such as a workstation or a personal computer
A capacitor used as a decoupling capacitor connected to a power supply circuit for supplying power to an MPU chip (bare chip) of U) is also required to have a low ESL.

FIG. 5 shows the MPU 1 and the power supply 2 described above.
FIG. 2 is a block diagram schematically illustrating an example of a connection configuration related to FIG.

Referring to FIG. 5, MPU 1 includes an MPU chip 3 and a memory 4. The power supply unit 2 is for supplying power to the MPU chip 3, and the power supply unit 2
A decoupling capacitor 5 is connected to a power supply circuit reaching the U chip 3. Further, a signal circuit is configured from the MPU chip 3 to the memory 4 side.

In the case of the decoupling capacitor 5 used in connection with the MPU 1 as described above, it is used for noise absorption and smoothing against fluctuations in the power supply, similarly to a normal decoupling capacitor. , MPU chip 3 has an operating frequency of 50
It is planned to exceed 0 MHz and reach 1 GHz. In applications where high-speed operation is required in connection with such an MPU chip 3, a function as a quick power supply (power at startup or the like is used). When it is needed suddenly, a function of supplying power within a few nanoseconds from the amount of electricity charged in the capacitor is required.

More specifically, in a certain MPU chip (operating clock frequency: about 500 MHz) 3, a DC
About 2.0 V is supplied, and power consumption is about 24 W, that is, a design in which a current of about 12 A flows. In order to reduce the power consumption, a specification is adopted in which the sleep mode is set when the MPU 1 is not operating and the power consumption is reduced to 1 W or less. At the time of conversion from the sleep mode to the active mode, it is necessary for the MPU chip 3 to be supplied with power required for the active mode during the number of clocks of its operation. At an operating frequency of 500 MHz, when converting from sleep mode to active mode, 4
Power must be supplied for a time of ~ 7 nanoseconds.

However, since the supply of the above-mentioned electric power cannot be made from the power supply unit 2, the decoupling capacitor 5 placed near the MPU chip 3 is charged until the power is supplied from the power supply unit 2. Power is supplied to the MPU chip 3 by discharging the electric charge.

For this reason, even in the decoupling capacitor 5 in the MPU 1, it is necessary that the inductance component be as low as possible, and it is desired to realize a capacitor having such a low inductance value.

Under the above-described background, the structure of a multilayer capacitor that can achieve low ESL is disclosed in, for example,
-204372 and the like.

The above-mentioned reduction in ESL is mainly due to the cancellation of the magnetic field induced by the current flowing in the multilayer capacitor. In order to cause such cancellation of the magnetic field, the direction of the current flowing in the multilayer capacitor is varied. Is being done. In order to diversify the direction of the current, the number of external terminal electrodes formed on the outer surface of the capacitor main body is increased, so that the lead-out portions of the internal electrodes that are drawn out so as to be electrically connected thereto are increased. In addition to increasing the number, the current length of the current flowing through the internal electrode is shortened.

FIG. 6 shows the above-mentioned JP-A-11-2043.
No. 72 schematically shows a multilayer capacitor 11 described in Japanese Patent Application Publication No.
Using MPU as a decoupling capacitor
2 is schematically shown.

Referring to FIG. 6, a multilayer capacitor 11 includes:
Capacitor body 1 including a plurality of stacked dielectric layers 13
4 is provided. Inside the capacitor body 14,
At least one pair of first and second internal electrodes 15 and 16 facing each other via a specific dielectric layer 13 is provided.

The internal electrode 1 of the capacitor body 14
On first main surface 17 extending in parallel with 5 and 16, both first and second external terminal electrodes 18 and 19 are provided. Second main surface 2 facing first main surface 17
No external terminal electrodes are provided on 0.

Inside the capacitor body 14,
The first through the specific dielectric layer 13 so as to electrically connect the first internal electrode 15 and the first external terminal electrode 18 while being electrically insulated from the second internal electrode 16. 1
A specific dielectric material is provided such that the second internal electrode 16 and the second external terminal electrode 19 are electrically connected to each other while being electrically insulated from the through conductor 21 and the first internal electrode 15. Second through conductors 22 penetrating the layer 13 are provided.

A plurality of the first and second through conductors 21 and 22 are provided, respectively, and the first and second through conductors 21 and 22 are provided.
A plurality of first and second external terminal electrodes 18 and 19 are provided respectively corresponding to the through conductors 21 and 22, respectively.

According to such a multilayer capacitor 11,
Since the current flowing through the internal electrodes 15 and 16 can be shortened and directed in various directions, the magnetic fields induced by the current flowing through the internal electrodes 15 and 16 cancel each other, and as a result, a low ESL is generated. Can be achieved.

On the other hand, the MPU 12 includes a wiring board 24 having a multilayer structure in which a cavity 23 is provided on the lower surface side. On the upper surface of the wiring board 24, an MPU chip 25 is surface-mounted. The cavity 23 of the wiring board 24
The above-mentioned multilayer capacitor 11 functioning as a decoupling capacitor is accommodated therein. Further, the wiring board 24 is surface-mounted on the motherboard 26.

As shown schematically, wiring conductors necessary for the MPU 12 are formed on the surface and inside of the wiring board 24.
The connection shown in FIG.

To describe a typical example, a power supply hot side electrode 27 and a ground electrode 28 are formed inside a wiring board 24.

The power supply hot side electrode 27 is electrically connected to the first external terminal electrode 18 of the multilayer capacitor 11 via a power supply hot side via hole conductor 29, and is connected via the power supply hot side via hole conductor 30. , MPU chip 25
Of the motherboard 2 via a power-side hot via-hole conductor 32.
6 are electrically connected to the hot conductive land 33 to be connected.

The ground electrode 28 is electrically connected to the second external terminal electrode 19 of the multilayer capacitor 11 via a ground via-hole conductor 34, and is electrically connected to the MPU chip 25 via a ground via-hole conductor 35. It is electrically connected to a specific terminal 36 and is further electrically connected to a ground-side conductive land 38 to be connected to the motherboard 26 via a ground via-hole conductor 37.

In FIG. 6, illustration of a memory corresponding to the memory 4 shown in FIG. 5 is omitted.

[0027]

SUMMARY OF THE INVENTION Multilayer capacitor 11
6, the first and second external terminal electrodes 18 and 19 are both located on the first main surface 17 of the capacitor body 14. Therefore, for example, focusing on a wiring conductor having a ground potential, the second external terminal electrode 19 of the multilayer capacitor 11 passes through the ground via-hole conductor 34, the ground electrode 28, and the ground via-hole conductor 37 in the wiring board 24. After that, it is connected to the ground conductive land 38.

Therefore, the ground lines provided by the ground via-hole conductors 34 and 37 and the ground electrode 28 are relatively long, the inductance component generated in connection with such ground lines is large, and low ESL is achieved. The effect of using the obtained multilayer capacitor 11 is diminished. Also,
A relatively long ground line also causes an increase in impedance.

In addition, the routing of the ground line as described above has a problem that wiring in the wiring board 24 is complicated.

Therefore, an object of the present invention is to provide a multilayer capacitor which can solve the above-described problems, and a wiring board, a decoupling circuit, and a high-frequency circuit formed using such a multilayer capacitor. It is to be.

[0031]

A multilayer capacitor according to the present invention includes a capacitor body including a plurality of stacked dielectric layers.

At least one pair of first and second internal electrodes facing each other via a specific dielectric layer is provided inside the capacitor body.

Further, the second inside of the capacitor body is
A plurality of first through conductors penetrating a specific dielectric layer while being electrically insulated from the first internal electrode and electrically connected to the first internal electrode; and a first internal electrode And a plurality of second through conductors penetrating the specific dielectric layer while being electrically insulated from and electrically connected to the second internal electrode. The first and second through conductors are arranged so as to cancel each other out of the magnetic field induced by the current flowing through the internal electrode.

On the first main surface of the capacitor body extending in parallel with the internal electrodes, each of the first through conductors is electrically connected to the plurality of first through conductors. A plurality of corresponding first external terminal electrodes are provided.

The second main surface of the capacitor body opposite to the first main surface has individual second through-holes electrically connected to the plurality of second through-conductors, respectively. A plurality of second external terminal electrodes respectively corresponding to the conductors are provided.

As described above, the multilayer capacitor according to the present invention can be simply described as a plurality of first through-conductors provided respectively corresponding to a plurality of first through conductors connected to the first internal electrodes. , And a plurality of second external terminal electrodes provided respectively corresponding to the plurality of second through conductors connected to the second internal electrode, respectively.
Is provided on the first main surface of the capacitor body, and the second external terminal electrode is provided on the second main surface.

It is preferable that solder bumps are formed on the first and second external terminal electrodes.

Further, the multilayer capacitor according to the present invention comprises:
It is advantageously used as a decoupling capacitor connected to a power supply circuit for an MPU chip provided in the MPU.

The present invention is also directed to a wiring board on which the above-described multilayer capacitor is mounted.

As described above, when the present invention is directed to a wiring board, in a specific embodiment, an MPU chip provided for an MPU is mounted on the wiring board. And a power supply hot side wiring conductor and a ground wiring conductor for supplying power for the power supply, wherein the first main surface of the capacitor body is directed toward the wiring board and the second main surface is directed outward. The multilayer capacitor is mounted in the posture as described above, and in this mounted state, the first external terminal electrode is electrically connected to the power supply hot side wiring conductor. At this time, the second external terminal electrode faces outward and is provided for ground connection. When this wiring board is mounted on a motherboard, for example, it is electrically connected to a ground-side conductive land on the motherboard. It is in a state where it can be done.

The above-described first external terminal electrode and the power-side hot-side wiring conductor are preferably connected via a bump.

Preferably, the MPU chip is mounted on the first substrate surface of the wiring board, and
A cavity is provided having an opening located along a second substrate surface opposite to the first substrate surface. The multilayer capacitor is housed in the cavity with its second main surface facing the opening side of the cavity, the second main surface and the second substrate surface are located on the same surface, A ground-side conductive land electrically connected to the ground wiring conductor is formed on the substrate surface. By adopting such a configuration, the second external terminal electrode provided on the multilayer capacitor and the ground-side conductive land provided on the wiring board are:
They will be located on the same side and on the same plane.

In the above configuration, it is preferable that solder bumps are formed on the second external terminal electrodes and the ground-side conductive lands.

The present invention is further directed to a decoupling circuit including the multilayer capacitor as described above.

Further, the present invention is also directed to a high-frequency circuit including the multilayer capacitor as described above.

[0046]

1 to 3 show a multilayer capacitor 41 according to an embodiment of the present invention. Here, FIGS. 1 and 2 are plan views showing the internal structure of the multilayer capacitor 41, and FIGS. 1 and 2 show cross sections different from each other. FIG. 3 is a sectional view taken along line III-III shown in FIGS. 1 and 2.

The multilayer capacitor 41 has a capacitor body 43 including a plurality of dielectric layers 42 to be stacked.
The dielectric layer 42 is made of, for example, a ceramic dielectric.

At least one pair of first and second internal electrodes 44 and 45 facing each other via a specific dielectric layer 42 are provided inside the capacitor body 43. In this embodiment, a plurality of pairs of first and second internal electrodes 44 and 45 are provided.

Inside the capacitor body 43,
The first internal electrode 45 is electrically insulated from the first
A plurality of first through conductors 46 penetrating the specific dielectric layer 42 are provided in a state of being electrically connected to the internal electrodes 44. A plurality of second through conductors 47 penetrating the specific dielectric layer 42 in a state electrically insulated from the first internal electrode 44 and electrically connected to the second internal electrode 45 Is provided.

The internal electrode 4 of the capacitor body 43
On a first main surface 48 extending in parallel with 4 and 45, a plurality of first through conductors 46 respectively corresponding to the individual first through conductors 46 are electrically connected to the plurality of first through conductors 46, respectively. A first external terminal electrode 49 is provided.

Further, on the second main surface 50 of the capacitor body 43 facing the first main surface 48, each of the plurality of second through conductors 47 is electrically connected to each of the plurality of second through conductors 47. A plurality of second external terminal electrodes 51 respectively corresponding to the second through conductors 47 are provided.

In this embodiment, a plurality of first and second internal electrodes 44 and 45 are provided, respectively, and the capacitance formed between each of the first and second internal electrodes 44 and 45 is The first and second through conductors 46 and 47 are connected in parallel, and the capacitance thus connected in parallel is extracted between the first and second external terminal electrodes 49 and 51.

The first through conductor 46 and the second through conductor 47 described above are arranged so that the magnetic fields induced by the currents flowing through the internal electrodes 44 and 45 cancel each other. That is, in this embodiment, the first and second
Are arranged so as to be adjacent to each other, and diversify the direction and shorten the current length of the current flowing through each of the internal electrodes 44 and 45, thereby achieving low ESL. ing.

In this embodiment, the first and second
External terminal electrodes 49 and 51 include conductive pads 52 and 53 and solder bumps 54 and 55 formed thereon, respectively.

The conductive pads 52 and 53 are, for example,
The internal electrodes 44 and 45 and the penetrating conductors 46 and 4 are formed of Cr / Ni / Cu vapor-deposited films.
7 is formed, for example, by baking a conductive paste containing Ni.

FIG. 4 is a diagram corresponding to FIG. 6, and shows an MPU 61 using the multilayer capacitor 41 according to the above-described embodiment as a decoupling capacitor.

Referring to FIG. 4, MPU 61 includes a wiring board 62, and an MPU chip (bare chip) 64 is surface-mounted on a first substrate surface 63 on the upper surface side of wiring board 62. .

A cavity 66 is provided on the second substrate surface 65, which is the lower surface of the wiring substrate 62. The cavity 66 has its opening located along the second substrate surface 65.

The above-mentioned multilayer capacitor 41 is housed in the cavity 66 with the second main surface 50 of the capacitor body 43 facing the opening side of the cavity 66. At this time, the second main surface 50 of the capacitor body 43 and the second substrate surface 65 of the wiring board 62 are located on the same plane.

The wiring board 62 is surface-mounted on a motherboard 67.

As shown schematically, wiring conductors necessary for the MPU 61 are formed on the surface and inside of the wiring board 62.
The connection shown in FIG.

To describe a typical example, a power supply hot side electrode 68 and a ground electrode 69 are formed inside the wiring conductor 62.

The power supply hot side electrode 68 is electrically connected to the first external terminal electrode 49 of the multilayer capacitor 41 via the power supply hot side via hole conductor 70, and is connected via the power supply hot side via hole conductor 71. , MPU chip 64
Of the motherboard 6 via a power supply hot-side via-hole conductor 73.
7 is electrically connected to a hot-side conductive land 74 to be connected.

Although not shown in detail in FIG. 4 with respect to the hot-side connection portion, the connection between the power supply hot-side via-hole conductor 70 and the first external terminal electrode 49 and the connection between the power supply hot-side via-hole conductor 71 A connection via a bump is applied to the connection with the terminal 72, and a solder bump is formed on the hot-side conductive land 74.

On the other hand, the ground electrode 69 is electrically connected to a specific terminal 76 of the MPU chip 64 via a ground via-hole conductor 75, and further connected to the motherboard 67 via a ground via-hole conductor 77. It is electrically connected to the ground-side conductive land 78 to be formed.

Although not shown in detail in FIG. 4 with respect to the above-described ground-side connection portion, a connection via a bump is applied to the connection between the ground via-hole conductor 75 and the terminal 76. Conductive land 7
8, solder bumps are formed.

As a characteristic configuration in this embodiment,
The second external terminal electrode 51 of the multilayer capacitor 41 is not connected to the ground electrode 69 in the wiring board 62, but is directly connected to the motherboard 67. As described above, the solder bumps 55 (see FIG. 3) are formed on the second external terminal electrodes 51, and the second external terminal electrodes 51 are connected to the motherboard 67 via such solder bumps 55.

Thus, according to this embodiment,
Since the second external terminal electrode 51 on the ground side of the multilayer capacitor 41 is directly connected to the motherboard 67, the ground line for the multilayer capacitor 41 can be made relatively short, so that the inductance component and the impedance component can be reduced. It is possible to achieve a reduction, and it is possible to sufficiently cope with a higher frequency. Also,
The wiring on the wiring board 62 can also be simplified.

In FIG. 4, illustration of a memory corresponding to the memory 4 shown in FIG. 5 is omitted.

[0070]

As described above, according to the multilayer capacitor of the present invention, the first and second internal electrodes facing each other are connected by the plurality of first and second through conductors, and the capacitor body is formed. A plurality of first external terminal electrodes respectively corresponding to each of the first through conductors are provided on the outer surface of the plurality of first through conductors while being electrically connected to the plurality of first through conductors; And a plurality of second external terminal electrodes respectively corresponding to the individual second through conductors, which are electrically connected to the second through conductors, respectively. ES
L, the first external terminal electrode is on the first main surface of the capacitor body, the second external terminal electrode is on the second main surface of the capacitor body, and so on. Since the second external terminal electrodes and the second external terminal electrodes are provided on different main surfaces, when the multilayer capacitor is mounted on a wiring board, the following effects are obtained.

That is, when the multilayer capacitor is mounted with the first main surface facing the wiring board, the first external terminal electrode is electrically connected to the wiring conductor on the wiring board.
As for the second external terminal electrodes on the second main surface, they can be directed outward. Therefore, when the wiring board on which the multilayer capacitor is mounted is mounted on the motherboard with the second main surface of the capacitor body facing the motherboard, for example, the second external terminal electrode is grounded on the motherboard. A state directly connected to the side conductive land can be obtained. As a result, the ground line related to the multilayer capacitor can be shortened, and accordingly, the inductance component and the impedance component can be prevented from increasing. Of the present invention can be prevented from being reduced. Further, the wiring substrate does not require a wiring conductor for ground connection to the multilayer capacitor, so that the wiring in the wiring substrate can be further simplified.

Thus, the multilayer capacitor according to the present invention can be advantageously used, for example, as a bypass capacitor or a decoupling capacitor in a high-frequency circuit. Further, a decoupling capacitor used in combination with an MPU chip or the like provided in the MPU is required to have a function as a quick power supply. However, the multilayer capacitor according to the present invention itself has a low ESL, Further, since it is possible to mount the semiconductor device on a wiring board in a state where an inductance component is not generated so much, it is possible to sufficiently cope with a high-speed operation even when it is used for such a decoupling capacitor.

As described above, when the multilayer capacitor according to the present invention is used as the decoupling capacitor connected to the power supply circuit for the MPU chip provided in the MPU, the decoupling capacitor is provided on the wiring board side on which the MPU chip is mounted. 1
The multilayer capacitor is mounted in such a manner that the main surface of the multilayer capacitor is turned and the second main surface is turned outward.
A U chip is mounted on a first substrate surface of a wiring substrate, and the wiring substrate is provided with a cavity having an opening located along a second substrate surface opposite to the first substrate surface. The multilayer capacitor is housed in the cavity with the second main surface facing the opening side of the cavity, and the second main surface and the second
Substrate surface is located on the same surface, and on the second substrate surface,
If the ground-side conductive land electrically connected to the ground wiring conductor in the wiring board is formed, for example, the second external terminal electrode and the ground-side conductive land for achieving ground connection to the motherboard and the motherboard Connection to the ground-side conductive land on the side can be performed at once and efficiently.

In the multilayer capacitor according to the present invention, when the solder bumps are formed on the first and second external terminal electrodes, or when the solder bumps are formed on the ground-side conductive lands in the wiring board according to the present invention. In addition to enabling high-density mounting, it is also possible to suppress occurrence of parasitic inductance in connection.

[Brief description of the drawings]

FIG. 1 shows a multilayer capacitor 4 according to an embodiment of the present invention.
FIG. 2 is a plan view showing an internal structure of a first example with a cross section through which a first internal electrode passes.

FIG. 2 is a plan view showing an internal structure of the multilayer capacitor 41 shown in FIG. 1 with a cross section through which a second internal electrode 45 passes.

FIG. 3 is a sectional view of the multilayer capacitor 41 taken along a line III-III shown in FIGS. 1 and 2;

FIG. 4 shows an MPU 6 using the multilayer capacitor 41 shown in FIGS. 1 to 3 as a decoupling capacitor.
FIG. 2 is a cross-sectional view schematically illustrating a structural example of FIG.

FIG. 5 is a block diagram schematically showing a connection configuration regarding an MPU 1 and a power supply unit 2 which are of interest to the present invention.

FIG. 6 is a view corresponding to FIG. 4, and is a cross-sectional view schematically showing an example of the structure of an MPU 12 using a conventional multilayer capacitor 11 as a decoupling capacitor.

[Explanation of symbols]

 1,61 MPU 2 Power supply unit 3,64 MPU chip 5 Decoupling capacitor 41 Multilayer capacitor 42 Dielectric layer 43 Capacitor body 44 First internal electrode 45 Second internal electrode 46 First penetrating conductor 47 Second penetrating conductor 48 first main surface 49 first external terminal electrode 50 second main surface 51 second external terminal electrode 54, 55 solder bump 62 wiring board 63 first substrate surface 65 second substrate surface 66 cavity 67 motherboard 68 Power supply hot side electrode 69 Ground electrode 70, 71, 73 Power supply hot side via hole conductor 75, 77 Ground via hole conductor 78 Ground side conductive land

 ──────────────────────────────────────────────────の Continuing on the front page (72) Keiichi Kuroda, Inventor 2-26-10 Tenjin, Nagaokakyo-shi, Kyoto Stock Company Murata Manufacturing Co., Ltd. (72) Haruo Hori 2-26-10, Tenjin, Nagaokakyo-shi, Kyoto Stock Inside the Murata Manufacturing Company (72) Takanori Kondo 2-26-10 Tenjin, Nagaokakyo-shi, Kyoto Prefecture GG01 GG11 JJ03 JJ06 JJ15 MM28

Claims (10)

[Claims] 1. A capacitor body including a plurality of stacked dielectric layers, wherein at least one pair of a first and a second pair facing each other via a specific dielectric layer is provided inside the capacitor body.
Is provided inside the capacitor body, further in a state in which the specific internal electrode is electrically insulated from the second internal electrode and electrically connected to the first internal electrode. A plurality of first penetrating conductors penetrating the dielectric layer, and a specific through conductor electrically insulated from the first internal electrode and electrically connected to the second internal electrode; A plurality of second penetrating conductors penetrating the dielectric layer are provided, and the first and second penetrating conductors are arranged so as to cancel a magnetic field induced by a current flowing through the internal electrode. On the first main surface of the capacitor main body extending in parallel with the internal electrodes, each of the first through conductors is electrically connected to the plurality of first through conductors, respectively. Corresponding multiple first exterior Child electrodes provided, of the capacitor body, the opposite to the first major surface 2
A plurality of second external terminal electrodes respectively corresponding to each of the second through conductors are provided on the main surface of the plurality of second through electrodes while being electrically connected to the plurality of second through conductors, respectively. There is a multilayer capacitor. 2. The multilayer capacitor according to claim 1, wherein solder bumps are formed on the first and second external terminal electrodes. 3. The power supply circuit according to claim 1, wherein the power supply circuit is used as a decoupling capacitor connected to a power supply circuit for an MPU chip provided in the microprocessing unit.
3. The multilayer capacitor according to item 1. 4. A wiring board on which the multilayer capacitor according to claim 1 is mounted. 5. A wiring board, comprising: an MPU chip provided in a microprocessing unit; and a power supply hot side wiring conductor for supplying power for the MPU chip and a ground wiring conductor. The multilayer capacitor is mounted with the first main surface facing the wiring board and the second main surface facing outward, and in this mounting state, the first external terminal electrodes are: The wiring board according to claim 4, wherein the wiring board is electrically connected to the power supply hot-side wiring conductor. 6. The first external terminal electrode and the hot power supply wiring conductor are connected via a bump.
The wiring board according to claim 5. 7. The MPU chip is mounted on a first board surface of the wiring board, and the first wiring board is provided with the first MPU chip.
A cavity is provided in which an opening is located along a second substrate surface opposite to the substrate surface of the multilayer capacitor;
The second main surface is accommodated in the cavity with the second main surface facing the opening side of the cavity, the second main surface and the second substrate surface are located on the same plane, 6. A ground-side conductive land electrically connected to the ground wiring conductor is formed on the substrate surface of (5).
Or the wiring board according to 6. 8. The wiring board according to claim 7, wherein solder bumps are formed on the second external terminal electrodes and the ground-side conductive lands. 9. A decoupling circuit comprising the multilayer capacitor according to claim 1. 10. A high-frequency circuit comprising the multilayer capacitor according to claim 1.