JP2001292574A - DC / DC converter - Google Patents

Abstract

(57) [Problem] To provide a low-cost DC / DC converter that realizes small size and high efficiency. SOLUTION: A transformer provided with at least a primary winding and a secondary winding, a main switching element for intermittently supplying power from a power supply to the primary winding, and a main switching element during an off period of the main switching element. A series circuit of a capacitor for resetting the transformer by recirculating the excitation energy stored in the transformer and a sub switching element, and a primary side control circuit for generating a control signal for alternately turning on and off the main switching element and the sub switching element. And a secondary rectifier circuit for rectifying the electric power generated in the secondary winding, and a current blocking means for blocking a current flowing into the secondary rectifier circuit for a predetermined time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a DC / DC converter having an active clamp circuit, and more particularly, to reducing a voltage applied to a primary switching element to zero when the primary switching element is turned on. The present invention relates to a DC / DC converter that realizes zero voltage switching (ZVS) to reduce switching loss and switching noise.

[0002]

2. Description of the Related Art A DC / DC converter having a conventional active clamp circuit is disclosed, for example, in US Pat. No. 4,444,146.
Is disclosed.

FIG. 22 shows an example of a DC / DC converter having an active clamp circuit having such a configuration.

In the figure, a primary circuit is an active clamp circuit in which a main winding Np of a transformer T1 and a main switching element Q11 are connected in series, and a voltage clamping capacitor C13 and a sub switching element Q12 are connected in series. Is connected in parallel to the main winding of
Each of the switching elements Q11 and Q12 has a timer D11 and D12.
And capacitors C11 and C12 are connected in parallel.

When MOSFETs having a parasitic element are used for the switching elements Q11 and Q12, the parasitic elements D11 and D12 and the capacitors C11 and C12 can be used in place of the parasitic elements.

Further, as shown in the figure, the transformer T1 has a form of forward connection in which a main winding Np and a secondary winding Ns are wound in the same direction.

The secondary circuit includes a secondary winding Ns of the transformer T1.
A forward rectifier D21 and a flywheel rectifier D22 are connected to each other, and a common connection point between the rectifier D21 and the flywheel rectifier D22 is connected to an output capacitor C30 via an inductor L21, and both ends of the output capacitor C30 are connected to a load circuit 100. .

In the circuit having such a configuration, the main switching element Q11 and the sub-switching element Q12 input drive signals G11 and G12 generated by a primary-side control circuit (not shown) to gates and alternately turn on / off. I do. Also, drive signals G11, G1
No. 2 is provided with a dead time so that the main switching element Q11 and the sub switching element Q12 are not simultaneously turned on.

Here, during the period when the main switching element Q11 is on and the switching element Q12 is off by the drive signals G11 and G12, current flows as shown by solid lines Ip1 and Is1 in FIG. Further, the current Is1 flowing here supplies current to the load circuit 100 through the forward rectifier D21, and at the same time, excites the secondary-side inductor L21 to store energy.

[0010] Further, during the period from the time when the main switching element Q11 is turned off to the time when the sub-switching element Q12 is turned on, the forward rectifier D is used.
The current flowing in the flywheel rectifier D22 decreases, and the current flowing in the flywheel rectifier D22 increases.

Next, during the period when the main switching element Q1 is off and the switching element Q12 is on, the dotted lines Ip2 and Ip2 in FIG.
As shown in (5), a current flows through the flywheel rectifier D22 by the energy stored in the inductor L21.

In addition, during the period from the time when the main switching element Q12 is turned off to the time when the switching element Q11 is turned on, the flywheel rectifier is provided.
The current flowing through D22 decreases and the current flowing through forward rectifier D21 increases.

In the DC / DC converter shown in FIG. 22, it is possible to supply power to the load circuit 100 while insulating the input voltage HV by repeating the above operation.

[0014]

However, the conventional DC / DC converter shown in FIG. 22 has the following problems.

In the DC / DC converter shown in FIG. 22, when the switching element Q12 is turned off, the charge of the capacitor C11 is extracted by the resonance of the inductance of the main winding Np (hereinafter referred to as main inductance) and the combined capacitance of the circuit. As a result, the voltage Vds of the main switching element Q11 decreases. At this time, the forward rectifier D21 of the secondary circuit is off, and the flywheel rectifier D22 is on.

As the voltage Vds of the main switching element Q11 decreases, the voltage of the secondary winding Ns of the transformer T1 is inverted.
When the voltage reaches 21 Cassort (voltage Vk + forward voltage Vf) or more, current starts flowing through the forward rectifier D21. This means that energy is released to the secondary side via the transformer T1.

As a result, the resonance energy on the primary side is reduced, the amount of charge withdrawn from the capacitor C11 is reduced, and the main switching element Q11
Of the voltage applied to the gate electrode becomes slow.

The phenomenon during this period indicates that the main interactance is equivalently short-circuited with the conduction of the forward rectifier D21, and the resonance due to the main inductance changes from the resonance due to the leakage inductance.

When the energy for extracting the charge of the capacitor C11 is insufficient, such as when the excitation current is small or the input voltage HV is high, the voltage Vds applied to the main switching element Q11 does not decrease sufficiently.

When the main switching element Q11 is turned on in a state where the voltage Vds is applied as in this case, an excessive surge current is generated, which causes a switching loss, which is a serious problem that deteriorates the efficiency of the converter.

Further, since the surge current generated here is emitted to the outside of the converter even as noise, it is necessary to take measures such as a noise filter, which is a problem that hinders downsizing of the converter.

In order to solve such a problem, US Pat. No. 4,444,146 discloses a circuit capable of reducing a surge current when the main switching element is turned on.

FIG. 23 shows an example of a DC / DC converter having such a configuration.

In the figure, the point different from FIG. 22 is that a saturable inductor L23 is inserted between the secondary winding Ns and the forward rectifier D21. Other configurations are the same as those in FIG. 22, and thus the same reference numerals are given and the description will be omitted.

When a current starts flowing through the saturable inductor L23, the internal impedance is high and the current flowing therethrough is blocked. After that, when the saturable inductor L23 saturates, the impedance decreases and the current flows. is there.

The saturable inductor L23 having such properties
Is inserted between the secondary winding Ns and the forward rectifier D21 to prevent the forward current starting to flow through the forward rectifier D21 when the switching element Q12 is turned off, thereby preventing the energy transfer to the secondary side. The obstruction makes it possible to maintain resonance due to the main inductance of the primary circuit.

As a result, it is possible to continue extracting the charge of the capacitor C11 connected in parallel with the main switching element Q11, and it is possible to reduce the voltage applied to the main switching element Q11 to zero.

After the voltage applied to the main switching element Q11 is reduced to zero or the level at which the switching loss does not cause a problem, the drive signal G11 is controlled so as to turn on the main switching element Q11. ZV
S) can be realized.

However, in a circuit having such a configuration, D
It has been necessary to individually adjust the saturation value of the saturable inductor according to the variation of the components constituting the C / DC converter and the operating conditions. Therefore, in the circuit of FIG. 23, when mass-producing DC / DC converters, it is practically difficult to individually adjust the saturation value of the saturable inductor.

Further, depending on the circuit specifications of the DC / DC converter, the use of the saturable inductor may cause an increase in iron loss and copper loss of the supersaturated inductor.

Therefore, the circuit shown in FIG. 23 has a problem that circuits to which the saturable inductor can be applied are limited.

An object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a DC / DC converter realizing a small size and high efficiency at a low cost.

[0033]

According to the first aspect of the present invention, there is provided a transformer having at least a primary winding and a secondary winding, and an electric power from a power source is supplied to the primary winding. A main switching element for intermittently energizing the line, and a series circuit of a capacitor and a sub switching element for resetting the transformer by recirculating the excitation energy stored in the transformer during an off period of the main switching element.
A primary-side control circuit that generates a control signal for alternately turning on and off the main switching element and the sub-switching element; a secondary-side rectification circuit that rectifies power generated in the secondary winding;
Current blocking means for blocking a current flowing into the secondary side rectifier circuit for a certain period of time.

According to a second aspect of the present invention, in the first aspect, the series circuit of the capacitor and the switching element is configured to be connected in parallel or equivalently in parallel to the primary winding. It is characterized by having been done.

According to a third aspect of the present invention, in the first aspect, the series circuit of the capacitor and the switching element is connected in parallel or equivalently in parallel to the main switching element. It is characterized by having been done.

According to a fourth aspect of the present invention, in the first aspect, the series circuit of the capacitor and the switching element is connected in parallel or equivalently in parallel to the secondary winding. It is characterized by having been constituted.

According to a fifth aspect of the present invention, in the first aspect, the transformer further includes a tertiary winding, and a series circuit of the capacitor and the switching element is connected in parallel to the tertiary winding. Alternatively, it is characterized by being configured to be equivalently connected in parallel.

According to a sixth aspect of the present invention, in the first aspect of the invention, the current blocking means includes a block switch element inserted into a current path of the secondary winding and a secondary side rectifier circuit; The block switch control circuit is configured to control the block switch element, and the block switch control circuit generates a drive signal for holding the block switch element in an Off state for a certain period after the sub switch element is turned off. It is characterized by having been constituted.

According to a seventh aspect of the present invention, in the sixth aspect of the present invention, the block switch control circuit is wound around the same core as the transformer, and generates a voltage having the same polarity as that of the secondary winding. A forward winding to be generated, and an inductor (L24) and a resistor (R24) having one end connected to a voltage generating end of the forward winding.
And a Zener diode (ZD24) having an anode connected to the gate of the block switch Q23 and a cathode connected to the other end of the series circuit of the inductor (L24) and the resistor (R24).
And a capacitor (C24) for connecting the cathode of the Zener diode (ZD24) to the reference potential (NG) of the forward winding.

In the invention described in claim 8, in the invention described in claim 6, the block switch control circuit is wound around the same core as the transformer, and generates a voltage having the same polarity as that of the secondary winding. A forward winding to be generated, a non-inverting output type drive IC (41) for converting a signal input to an input terminal (IN) into a drive signal for the block switch, and a voltage generating terminal of the forward winding to the non-inverting terminal. A series circuit of a resistor (R24) and a diode (D24) connected to the input terminal (IN) of the inverted output type drive IC (41);
It is characterized by comprising a parallel circuit of a capacitor (C24) and a diode (D25) for connecting the input terminal (IN) of C (41) to the reference potential (NG) of the forward winding.

According to a ninth aspect of the present invention, in the invention of the sixth aspect, the block switch control circuit is wound around the same core as the transformer, and generates a voltage having the same polarity as that of the secondary winding. A forward winding that is generated, a power supply circuit that generates a stable voltage from a voltage generated in the winding of the transformer, and an inversion that converts an inverted signal of a signal input to an input terminal (IN) into a drive signal of the block switch. Output type drive IC (4
2) a voltage dividing circuit for dividing a voltage generated by the forward winding; a transistor for inputting an output voltage of the voltage dividing circuit to a base and connecting an emitter to a reference potential (NG) of the forward winding; (Q24) and a resistor (R25) for applying the stable voltage to the collector of the transistor (Q24).
A resistor (R24) for inputting the collector voltage of the transistor (Q24) to an input terminal (IN) of the inverted output type drive IC (42);
The input terminal (IN) of (42) is constituted by a capacitor (C24) for connecting to a reference potential (NG) of the forward winding.

According to a tenth aspect of the present invention, in the invention of the sixth aspect, the block switch control circuit is wound around the same core as the transformer, and generates a voltage having a polarity opposite to that of the secondary winding. A flyback winding to be generated, an inverted output type drive IC (42) for converting an inverted signal of a signal input to an input terminal (IN) into a drive signal for the block switch, and a voltage generating terminal of the flyback winding. With the inverted output type drive I
Resistance (R24) input to the input terminal (IN) of C (42)
And a series circuit of a diode (D24) and a capacitor (C2) for connecting the input terminal (IN) of the inverted output type drive IC (42) to the reference potential (NG) of the flyback winding.
4) and a diode (D25) in parallel.

According to an eleventh aspect of the present invention, in the invention of the sixth aspect, the block switch control circuit is wound around the same core as the transformer, and generates a voltage having a polarity opposite to that of the secondary winding. A flyback winding that is generated, a power supply circuit that generates a stable voltage from a voltage generated in the winding of the transformer,
A voltage dividing circuit for dividing a voltage generated by the flyback winding; a transistor (Q24) for inputting an output voltage of the voltage dividing circuit to a base and connecting an emitter to a reference potential (NG) of the flyback winding; A resistor (R25) for applying the stable voltage to the collector of the transistor (Q24), and a collector voltage of the transistor (Q24) to an input terminal (IN), and a signal input thereto is applied to the block switch Non-inverting output type drive IC (4
1) and a capacitor (C24) for connecting an input terminal (IN) of the non-inverting output type drive IC (41) to a reference potential (NG) of the flyback winding. is there.

According to the twelfth aspect, in the eighth aspect,
In the invention according to the eleventh aspect, the non-inverted output type drive IC (41) is configured using a floating output type non-inverted output type drive IC (43).

According to the thirteenth aspect, in the ninth aspect,
In the invention described in Item 10, the inverted output type drive I
C (42) is characterized by being configured using a floating output type inverted output type drive IC (44).

According to a fourteenth aspect of the present invention, in the sixth aspect of the present invention, the block switch control circuit detects a turn-off of the sub-switch element by a voltage change of the main switch element, and detects the turn-off of the sub-switch element. After the element is turned off, a drive signal for holding the block switch element in the Off state for a certain period is generated.

According to a fifteenth aspect of the present invention, in the first aspect of the present invention, the secondary rectifier circuit is a synchronous rectifier rectifier circuit using a synchronous rectifier. Is what you do.

According to a sixteenth aspect, in the first aspect, the output of the secondary rectifier circuit is supplied to a load circuit via an inductor winding wound on the same core as the transformer. It is configured to be output.

[0049]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of a DC / DC converter according to the present invention.

In this figure, the point different from the conventional example of FIG. 23 is that a block switch Q2 is used instead of the saturable inductor L23.
3 is used. Block switch Q used here
Reference numeral 23 uses a semiconductor switching element such as a transistor or a MOSFET. Since other configurations are the same as those of the conventional example, the same reference numerals are given and the description is omitted.

In the figure, the block switch Q23
Is controlled by a drive signal Vgs output from a delay circuit (not shown) for maintaining the Off state for a certain period after the switching element Q12 is turned off, and the block switch Q23 is turned on after the switching element Q12 is turned off. The Off state is maintained for a certain period.

In the conventional circuit, as described above, the forward current is blocked by the saturable inductor, thereby preventing the forward current, preventing the energy transfer to the secondary side, and maintaining the resonance by the main inductance. However, the circuit of the present invention achieves this by controlling the on / off timing of the block switch.

FIG. 2 shows a timing chart of the DC / DC converter of the present invention. In the same figure, the switching element
The maximum time t in the (t ₀ -t ₂ ) period from when Q12 turns off to when the voltage applied to the main switching element Q11 reaches zero is as follows, where L is the main interactance, and C is the combined capacitance of the circuit. Equation (1) is obtained.

The symbols of each waveform in FIG. 2 are as follows. Main switching element Q11 voltage Vds-Q11 Main switching element Q11 current Ids-Q11 sub switching element Q12 current, Ids-Q12 forward rectifier D21 cathode voltage Vak-D21 forward rectifier D21 forward current If-D21 block switch Q23 Drive signal Vgs-Q23 Block switch Q23 voltage Vds-Q23 Block switch Q23 current Ids-Q23 Flywheel Rectifier D22 cathode voltage Vak-D22 Flywheel Rectifier D22 forward current If-D22

In the figure, in (t ₀ -t ₁ period), time t
_{When the} switching element Q12 is turned off at ₀ , the charge of the capacitor C11 is drawn out due to resonance due to the main inductance and the combined capacitance of the circuit, and the voltage Vds-Q11 of the main switching element Q11 decreases. In the secondary circuit, the current I is supplied to the flywheel rectifier D22.
f-D22 is flowing.

In the period (t ₁ -t ₂ ), the forward rectifier D21 turns on as the voltage Vds-Q11 of the main switching element Q11 decreases, but the block switch Q23 connected in series with the forward rectifier D21 is turned off by the delay circuit. Therefore, the current If-D21 does not flow through the forward rectifier D21.

In (t ₂ -t ₃ period), V of the main switching element Q11
ds-Q11 is turning the main switch link Bu element Q11 in becomes zero time t _2. At this time, the driving signal Vgs-Q2 is also applied to the gate of the block switch Q23.
3 is applied to turn on the block switch Q23. As a result, the current If-D21 of the forward rectifier D21 starts to flow, the current If-D22 of the flywheel rectifier D22 decreases, and the current is switched.

[0058] In (t ₃ -t ₄ period), turning off the main switch link Bu element Q11 at time t _3.

In the period (t ₄ -t ₅ ), when the voltage of the secondary winding Ns becomes equal to or less than (D21 cassort voltage + forward voltage), the forward rectifier D21 is turned off. When the forward rectifier D21 is turned off, the flywheel rectifier D22 is turned on, and the currents If-D21 and If-D22 are switched.

In the period (t ₅ -t ₆ ), a current starts to flow through the tire D12 connected in parallel with the switching element Q12. By turning on the sub-switching element Q12 during this period, the sub-switching element Q12 becomes a zero current switch (ZCS).
ching). Block switch Q23 turns off after forward rectifier D21 turns off. Since the forward rectifier D21 has already been turned off, the current Ids-Q23 flowing through the block switch Q23 becomes zero, and when the block switch Q23 turns off, the current becomes zero. Further, since the block switch Q23 is turned off within the range of t5 ≦ t <t7, the loss of the block switch Q23 during this period is zero. The secondary circuit holds the operation state of the previous period.

In the period (t ₆ -t ₇ ), the current flowing through the timer D12 becomes zero, and all the current flows through the switching element Q12.

The state returns to t ₀ at time t ₇ .

Here, FIG. 3A shows a measured waveform of the turn-on of the main switching element Q11 in the conventional circuit, and FIG. 3B shows a measured waveform of the turn-on of the main switching element Q11 in the circuit of the present invention.

In the waveform of the conventional circuit shown in FIG. 3A, at the timing Ton when the main switching element Q11 is turned on, a voltage Vds of 250 V is applied between the train and the source of the main switching element Q11. Has a switching loss of 0.38W. In the circuit of the present invention shown in FIG. 3B, at the timing Ton in which the main switching element Q11 is turned on, no voltage is applied between the train and the source of the main switching element Q11, so that no switching loss occurs.

Therefore, in the circuit of the present invention, the soft switching of the main switching element can be realized, and the switching loss can be reduced to zero. Further, in the circuit of the present invention, by using a semiconductor switching element for the block switch Q23,
Loss is a small value of 0.1 W or less in a DC / DC converter of 60 W. Further, in the circuit of the present invention, the fluctuation of the forward current blocking period due to the operating condition of the converter and the component dispersion is small,
It is practical.

The DC / D of the present invention described with reference to FIG.
The C converter will be described in detail with reference to four specific embodiments.

FIG. 4 is a block diagram showing a first embodiment of the circuit of FIG. (Hereinafter, this circuit is referred to as circuit-a.)

In the figure, the transformer T1 is provided with a forward winding Nsrb that generates a voltage having the same polarity as that of the secondary winding Ns, and the voltage generated there is input to the delay circuit unit DL. I have.

The output of the delay circuit section DL is connected as a drive signal Vgs to the gate of the block switch Q23.

In the circuit of the present invention, with such a circuit configuration, the block switch Q2
3 is generated. Also, in the figure, the forward winding Nsrb, the delay circuit section DL and the switch portion of the block switch Q23 are connected between the secondary winding Ns and the forward rectifier timer D21 note terminal, but the forward rectifier timer D21 sorter is connected. The same operation is performed when the terminal is replaced between the terminal connected to the D22 cascade and the inductor L21 or between the secondary winding Ns and the flywheel rectifying timer {D22 annotation} terminal.

FIG. 14 shows an example in which a MOSFET is used for the block switch Q23. A capacitor C23 and a timer D23 are shown in FIG.
Indicate parasitic elements of the MOSFET, and do not contribute to the circuit operation.

Next, FIG. 5 shows a specific embodiment of the delay circuit DL.

In the figure, one end of a series circuit of an inductor L24 and a resistor R24 is connected to the voltage generating end of the forward winding Nsrb, and the other end of this series circuit is connected to the gate of the block switch Q23 with the anode. The cathode of zener timer ZD24 is connected. The cathode of the zener timer ZD24 is connected to the reference potential (NG) of the forward winding Nsrb by a capacitor C24.

The operation of the delay circuit DL having such a configuration will be described with reference to FIG. The figure shows the forward winding in FIG.
Voltage Vnsrb generated in Nsrb and voltage generated in capacitor C12
FIG. 7 is a diagram showing waveforms of Vk and a drive signal Vgs of the block switch Q23.

In the figure, time t ₀ (time in FIG. 2)
It corresponds to t ₀ . ) After the switching element Q12 is turned off,
The polarity of the voltage Vnsrb of the forward ゛ winding Nsrb is inverted, and a negative to positive voltage Vnsrb appears in the forward ゛ winding Nsrb.

At this time, the Zener timer {Casote of ZD24} includes the voltage V delayed by the time constant (t _0a -t _{0 b} ) of the inductor L24 and the capacitor C24.
k appears.

At this time, a voltage is applied to the zener timer (the note of the ZD24).
A waveform delayed by (t _0b -t _0c ) from Vk appears as a voltage value (a voltage having a value of Cassort ゛ voltage−Zener voltage). This voltage is applied as a drive signal Vgs to the gate of the block switch Q23, and the block switch Q23 is turned on.

When the main switching element Q11 is turned off, the voltage Vnsrb of the forward winding Nsrb is inverted. At the same time, the charge of the capacitor C24 is extracted through the inductor L24 and the resistor R24,
And the time constant of C24 delays the waveform.

The falling voltage delayed from the voltage Vnsrb is the MOS
When the threshold value of the FET is reached, the block switch Q23 is turned off.
The turn-off of the block switch Q23 is performed immediately after the main switching element Q11 is turned off and the secondary-side forward rectification is also turned off to immediately before the next main switching element Q11 is turned on in order to realize the zero-voltage switching.

In FIG. 5, a resistor R24 is used as a buffer for waveform shaping.

FIG. 7 shows a second example of the delay circuit DL.
It is a figure which shows the Example of. The delay circuit DL shown in FIG.
It is configured using a non-inverting output type drive IC 41.

In the figure, one end of a series circuit composed of a timer D28 and a resistor R28 is connected to the voltage generating end of the forward winding Nsrb, and the other end of the series circuit is connected to the power supply terminal of the non-inverting output type drive IC 41. Vcc is connected. In addition, a zener timer D27 and a capacitor C27 are connected in parallel to a series circuit of the forward winding Nsrb, timer D28 and resistor R28.

The common connection point between the forward winding Nsrb and the timer D28 is connected to the input terminal IN of the non-inverting output drive IC 41 via the resistor R24 and the timer D24 connected in series. Further, a resistor R25 is connected in parallel with the timer D28.

The ground terminal GND of the non-inverting output type drive IC 41 is connected to the reference potential NG of the forward winding Nsrb, the output terminal OUT is connected to the gate of the locking switch Q23, and the input terminal IN and the forward winding Nsrb are connected. The reference potential NG is connected to a capacitor C24 and a timer D25.

In the circuit having such a configuration, the turn-on delay time of the block switch Q23 is set by a circuit composed of a timer D24 connected to the forward winding Nsrb, a resistor R24 and a capacitor C24, and the turn-off delay time of the block switch Q23 is Resistance R24, R25
And the circuit constituted by the capacitor C24.

The signal to which the delay time has been added in this manner is input to the input terminal IN of the non-inverting output type drive IC 41, and after being converted in voltage, the drive signal is supplied from the output terminal OUT to the gate of the block switch Q23. Entered as Vgs.

The timer D28, the resistor R28, the Zener timer ZD27, and the capacitor C27 are a non-inverting output type drive IC4.
One of the power supply circuits, the timer D25 is used as an input voltage clamping timer of the non-inverting output type drive IC 41, and protects a withstand voltage of an input signal.

Hereinafter, the operation of the delay circuit having the above configuration will be described.

First, after the switching element Q12 is turned off,
The positive voltage Vnsrb appearing in the forward winding Nsrb charges the capacitor C24 via the resistor R24, and the time constant delays the voltage Vnsrb.

When the delayed voltage reaches the threshold value of the input terminal IN of the non-inverting output type drive IC 41, the block switch Q23 is connected to the output terminal OUT of the non-inverting output type drive IC 41.
Drive signal Vgs appears and turns on the block switch Q23.

The main switching element Q11 is turned off, and the forward winding N
Simultaneously with the inversion of the voltage Vnsrb of srb, the charge of the capacitor C24 is extracted via the resistors R24 and R25, and the waveform of the voltage Vnsrb is delayed by the time constant of the resistors R24 and R25 and the capacitor C24.

When the falling voltage of the delayed voltage reaches the threshold value of the input terminal IN of the non-inverting output type drive IC 41, the voltage of the output terminal OUT becomes zero and the block switch Q2
Turn 3 off. At this time, the block switch Q23 is turned off immediately after the main switching element Q11 is turned off and the secondary-side forward current is turned off in order to realize zero-voltage switching, and immediately before the next main switching Q11 is turned on.

Further, a negative voltage is applied to the input terminal IN of the non-inverting output type drive IC 41, but the timer D25 conducts and clamps the voltage so as not to exceed the withstand voltage.

FIG. 8 shows a third embodiment for realizing the delay circuit DL.
It is a figure which shows the Example of. The delay circuit DL shown in FIG.
It is configured using an inversion output type drive IC 42.

In the figure, at the voltage generating end of the forward winding Nsrb, as in FIG. 7, a series circuit of a timer D28 and a resistor R28 and a power supply circuit composed of a Zener timer D27 and a capacitor C27 are formed. Are connected to the power supply terminal Vcc of the inverted output drive IC 42.

The common connection point between the forward winding Nsrb and the tire D28 is connected to a voltage dividing circuit constituted by resistors R26 and R27, and this divided voltage is connected to the base of the transistor Q24. .

The collector of the transistor Q24 is connected to the output of the power supply circuit via the resistor R25 and to the input terminal IN of the inverting output type drive IC 42 via the resistor R24, and the emitter is the reference of the forward winding Nsrb. It is connected to the potential (NG). Other configurations are the same as those in FIG.

In the circuit having such a configuration, the block switch Q23
The turn-on delay time and the turn-off delay time are set by a circuit including resistors R26 and R27, a transistor Q24, a capacitor C24, and resistors R24 and R25.

The operation of the delay circuit having the above configuration will be described below.

First, after the switching element Q12 is turned off,
Transistor Q24 turns on with a positive voltage Vnsrb appearing on forward winding Nsrb.

A falling waveform delayed from the voltage Vnsrb is generated at the collector of the transistor Q24 by the time constant for extracting the charge of the capacitor C24 via the resistor R24 and the current of the resistor R25 connected to the power supply terminal Vcc which is a stable potential. .

The falling voltage of the delayed voltage is
When the threshold value of the input terminal IN of the inverted output type drive IC 42 is reached, the drive signal Vgs of the block switch Q23 appears at the inverted output terminal OUT of the inverted output type drive IC 42 and the block switch Q23.
Turn on.

When the main switching element Q11 is turned off, the voltage Vnsrb of the forward winding Nsrb is inverted. Transistor Q24 turns off and charges the capacitor C24 via resistors R24 and R25,
The waveform is delayed by the time constant of the resistors R24 and R25 and the capacitor C24.

When the delayed voltage reaches the threshold value of the input terminal IN of the inverted output drive IC 42, the voltage of the output terminal OUT of the inverted output drive IC 42 becomes zero,
Turn off the block switch Q23.

The turn-off of the block switch Q23 is based on the main switching element Q1.
1 is turned off, and the secondary side forward rectification is performed immediately after being turned off and immediately before Q11 is turned on next time.

FIG. 9 shows a modified circuit example of the circuit-a described in FIG. (Hereinafter, this circuit is referred to as circuit-b.)

In the figure, the difference from the circuit-a described with reference to FIG. 4 is that the circuit-a is provided with a flyback winding Nsrb2 having an inverted polarity instead of the forward winding Nsrb2. .

In the circuit-b of FIG. 9, the drive signal Vgs for driving the block switch Q23 is provided in the transformer T1 with a flyback winding Nsrb2 for generating a voltage having a polarity opposite to that of the secondary Ns winding. To be generated is delayed by the delay circuit section DL. Other operation principles are the same as those of the circuit-a. However, if the voltage value generated in the winding exceeds the withstand voltage of the block switch Q23 input terminal,
If the operating voltage is insufficient, the number of turns needs to be changed.

In the above circuit-b, the flyback winding Nsrb
2. The delay circuit portion DL and the lock switch portion of the lock switch Q23 are connected between the secondary winding Ns and the forward rectifier timer D21 note terminal. There is no problem even if it is replaced between the terminals connecting the cascade and the inductor L21 or between the secondary winding Ns and the note terminal of the flyback rectifier tire D22.

FIG. 19 shows an example in which a MOSFET is used for the block switch Q23. The capacitor C23 and the timer D23 indicate the parasitic elements of the MOSFET, and do not contribute to the circuit operation.

FIG. 10 is a diagram showing a first embodiment for realizing the delay circuit DL.

The delay circuit DL shown in the figure is an example of a delay circuit constituted by using an inverting output type drive IC 42, and the structure thereof is the same as that of the non-inverting output type drive IC 41 in the delay circuit shown in FIG. Instead, the circuit is the same as that in which the inverted output type drive IC 42 is used and the connection direction of the tire automatic # D24 is reversed.

The operation of the delay circuit having the above configuration will be described below.

First, after the switching element Q12 is turned off,
The negative voltage Vnsrb2 appearing in the flyback winding Nsrb2 is connected to the resistor R24.
The capacitor C24 is discharged via the
rb2 is delayed.

When the delayed voltage reaches the threshold value of the input terminal IN of the inverted output type drive IC 42, the block switch Q23 is connected to the inverted output terminal OUT of the inverted output type drive IC 42.
Drive signal Vgs appears and turns on the block switch Q23.

When the main switching element Q11 is turned off, the voltage Vnsrb2 of the flyback winding Nsrb2 is inverted. At the same time, resistors R24 and R2
The capacitor C24 is charged with electric charge via 5, and the waveform of the voltage Vnsrb2 is delayed by this time constant.

The rising voltage of this delayed voltage is
, The voltage at the inverted output terminal OUT of the inverted output drive IC 42 becomes zero, and Q23 is turned off. At this time, the block switch Q23 is turned off immediately after the main switching element Q11 is turned off and the secondary side forward rectification is also turned off, and immediately before the next turn on of Q11.

A negative voltage is applied to the input terminal IN of the inverting output type drive IC 42. However, the timer D25 is turned on to clamp and protect the voltage so as not to exceed the withstand voltage.

FIG. 11 is a diagram showing a second embodiment for realizing the delay circuit DL.

The delay circuit DL shown in FIG. 13 is an example of a delay circuit formed by using a non-inverting output type drive IC 41. The configuration is the same as that of the delay circuit shown in FIG. Instead, it is the same as the circuit in which the non-inverting output type drive IC 41 is used and the resistor R24 is removed.

The operation of the delay circuit having the above configuration will be described below.

First, after the switching element Q12 is turned off,
Transistor Q24 with negative voltage Vnsrb2 appearing on flyback winding Nsrb2
Turns off.

A rising waveform delayed from the voltage Vnsrb2 occurs at the collector of the transistor Q24 due to the time constant for charging the capacitor C24 via the resistor R25.

When the rising voltage of the delayed voltage reaches the threshold value of the input terminal IN of the non-inverting output type drive IC 41, the drive signal Vqs of the block switch Q23 changes to the non-inverting output terminal OUT of the non-inverting output type drive IC 41. Appears on block switch
Turn Q23 on.

When the main switching element Q11 is turned off, the voltage Vnsrb2 of the flyback winding Nsrb2 is inverted. Transistor Q24 turns on, the charge in capacitor C24 is discharged, and the waveform drops.

When the voltage generated here reaches the threshold value of the input terminal IN of the non-inverted output type drive IC 41, the non-inverted output terminal OUT voltage of the non-inverted output type drive IC 41 becomes zero, and the block switch Q23 is turned off. Let it.

The turn-off of the block switch Q23 is based on the main switching element Q1.
1 is turned off, the secondary side forward rectification is performed immediately after the rectification is turned off, and then immediately before the main switching element Q11 is turned on.

After the sub-switching element Q12 is turned off, the transistor is driven by the negative voltage Vnsrb2 appearing on the driving winding Nsrb2.
Q24 turns off.

As described above, in the DC / DC converter of the present invention having the above-described circuit-a and circuit-b configuration, the winding for driving the block switch is provided in the transformer, and the block switch is driven through the delay circuit. By doing so, soft switching can be realized.

The windings for generating the voltage for driving the block switch used in the circuit having the above-described configuration (the forward winding Nsrb and the flyback winding Nsrb2 in the above circuit) are secondary. The circuit can be applied to either a forward winding in which a voltage having the same polarity as the side voltage is generated or a flyback winding in which a voltage having a polarity opposite to the secondary voltage is generated, so that a wide variety of circuit variations can be applied.

Further, the delay circuit can be constituted by a simple circuit using only an inductor, a capacitor, a resistor, and a zener diode, and a low power consumption driving IC is provided in the delay circuit.
The drive circuit loss can be further reduced in the circuit using.

Next, the DC / DC of the present invention described with reference to FIG.
A second embodiment of the converter will be described.

FIG. 12 shows that, similar to the circuit-a shown in FIG. 4, a forward winding Nsrb that generates a voltage having the same polarity as the secondary Ns winding is provided in the transformer T1, and the voltage generated here is delayed. The block switch Q2 is driven by the drive signal Vgs which is delayed in the circuit section.
FIG. 3 is a configuration diagram of a DC / DC converter that drives the DC / DC converter 3;
(Hereinafter, this circuit is referred to as circuit-a.)

In this figure, the point different from the configuration of the circuit-a shown in FIG. 4 is that one end of the forward winding Nsrb is connected to the secondary side GND, and that the output trifle such as the flat strut type is used.
The point is that a driving unit DR for driving the block switch Q23 using an IC is provided. In such a case, the flywheel rectifier D22 is connected to the source terminal of the block switch Q23. Other configurations are the same as those in FIG. 4, and therefore, are denoted by the same reference numerals and description thereof will be omitted.

The block switch Q in the circuit-a is
The on / off timing and operation principle of the circuit 23 are the same as those of the circuit-a shown in FIG.

The delay circuit DL used here is:
When a non-inverting floating-output tri-life IC 43 is used for the driving unit DR, a configuration as shown in FIG. 13 is used, which is almost the same configuration as the delay circuit of the circuit-a described in FIG. The following points are different.

In the delay circuit DL shown in FIG.
The configuration differs from that of the first embodiment in that a non-inverting floating output life IC 43 is used as a drive unit for outputting a drive signal Vgs of the block switch Q23, and that the drive signal Vgs output from this unit is connected to the cathode of the flywheel rectifier D22. Block switch Q connected to terminal
The point is that the input is made to the 23 gate terminals.
Note that, in FIG.
A power supply circuit for supplying power to the power supply terminal Vcc is omitted for simplicity.

The delay circuit DL having such a configuration operates according to the same operation principle as the delay circuit DL of FIG. Therefore, the turn-on delay time of the block switch Q23 is set by a circuit composed of the timer D24 connected to the forward winding Nsrb, the resistor R24 and the capacitor C24, and the block switch Q23 turn-off delay time is set by the resistors R24 and R2.
Set with 5 and capacitor C24. Then, the delay signal generated here is converted into a drive signal Vgs for driving the block switch Q23 via the non-inverting floating output IC 43.

The configuration of the delay circuit DL in the case where the inverting floating output life IC 44 is used for the drive unit DR will be described below.

Inverting type floating output IC for driving unit DR IC
When using the delay circuit 44, the delay circuit DL has a configuration as shown in FIG. 14, which is almost the same configuration as the delay circuit of the circuit-a described in FIG. 8, except for the following points. different.

In the delay circuit DL shown in FIG.
The configuration is different from that of the first embodiment in that the driving section that outputs the driving signal Vgs of the block switch Q23 has an inverting floating
And the driving signal Vgs output from this point.
However, the configuration is such that the cathode of the flywheel rectifier D22 is input to the gate terminal of the block switch Q23 connected to the source terminal. Note that, in the figure, a power supply circuit for supplying power to the power supply terminal Vcc of the inverting floating output / output / life IC 44 is omitted for simplicity.

The delay circuit DL having such a configuration operates according to the same operation principle as the delay circuit DL of FIG. Therefore, the delay time is equal to the voltage dividing resistor R26 connected to the forward winding Nsrb.
And R27, transistor Q24, capacitor C24, resistor R24, resistor R25
Set by the circuit composed of. The delay signal generated here is converted into a drive signal Vgs for the block switch Q23 via the inverting floating output IC 44.

FIG. 15 shows a modified circuit example of the circuit-a described in FIG. (Hereinafter, this circuit is referred to as circuit-b.)

In this figure, the point different from the circuit-a described with reference to FIG. 12 is that the forward-winding winding Nsrb of the circuit-a is replaced with a flyback winding Nsrb2 having an inverted polarity. . The other configuration is the same as that of the circuit-a described in FIG. 12, and therefore, the same reference numerals are given and the description is omitted.

Further, the block switch Q in the above circuit-b
The ON / OFF timing and operation principle of the circuit 23 are the same as those of the circuit-b shown in FIG.

Further, the delay circuit DL used here is:
When the inverting floating output tri-life IC 44 is used for the drive unit DR, the configuration shown in FIG. 16 is used, which is almost the same configuration as the delay circuit of the circuit-b described in FIG. The following points are different.

In the delay circuit DL shown in FIG.
0 is different from the configuration of FIG. 2 in that an inverting floating output life IC 44 is used as a driving unit for outputting the driving signal Vgs of the block switch Q23, and that the driving signal Vgs output from the driving unit is connected to the cathode of the flywheel rectifier D22. Block switch Q connected to terminal
The point is that the input is made to the 23 gate terminals.
Note that, in the figure, a power supply circuit for supplying power to the power supply terminal Vcc of the inverting floating output / output / life IC 44 is omitted for simplicity.

The delay circuit DL having such a configuration is similar to that shown in FIG.
Operates according to the same operation principle as the delay circuit DL. Therefore, the turn-on delay time of the block switch Q23 is equal to the flyback winding Nsrb.
Set by a circuit composed of a timer D24 connected to 2, a resistor R24 and a capacitor C24, and the block switch Q23 turn-off delay time is set by a resistor R2.
4. Set with R25 and capacitor C24. The delay signal generated here is converted to a drive signal Vgs for driving the block switch Q23 via the inverting floating output IC 44.

The configuration of the delay circuit DL in the case of using the non-inverting floating output / life IC 43 for the drive section DR will be described below.

A non-inverting type floating output {output life} is applied to the drive unit DR.
When the IC 43 is used, a delay circuit DL having a configuration as shown in FIG. 17 is used, which is almost the same configuration as the delay circuit of the circuit-b described in FIG. 11, except for the following points. different.

In the delay circuit DL shown in FIG.
The difference from the configuration 1 is that, similarly to the above, a non-inverting floating output tri-life IC 43 is used for the drive unit that outputs the drive signal Vgs of the block switch Q23, and the drive signal Vgs output from this
However, the configuration is such that the cathode of the flywheel rectifier D22 is input to the gate terminal of the block switch Q23 connected to the source terminal. Note that, in the figure, a power supply circuit for supplying power to the power supply terminal Vcc of the non-inverting type floating output (output life) IC 43 is omitted for simplicity.

As described above, in the DC / DC converter of the present invention, one end of the forward winding Nsrb is connected to the secondary side GND like the circuit-a and the circuit-b, and the floating output-life is connected.
Even if it is configured to drive the block switch Q23 using an IC,
The same effects as those of the circuit-a and the circuit-b can be realized.

Next, a description will be given of a third embodiment of the DC / DC converter of the present invention described with reference to FIG.

FIG. 18 is a block diagram showing a block switch which directly detects the voltage applied to the primary side switching element Q11 on the primary side and transmits a signal to the secondary side.
FIG. 14 is a diagram illustrating a configuration of a main part of a DC / DC converter that drives Q23. (Hereafter, this circuit is called a circuit.)

In the figure, a voltage detecting section 41 is a detecting circuit for detecting a fall of the voltage Vds of the main switching element Q11, and the detection signal S41 is input to the signal transmitting section. The voltage detection unit 41 uses a general-purpose voltage detection circuit composed of a converter, a transistor, and the like. Here, when the voltage Vds falls below a preset threshold, the detection signal S
It is assumed that the detection signal S41 is set to be low when the voltage Vds exceeds a preset threshold value by setting the signal 41 to high.

The signal transmitting section 42 is a circuit having a function of insulatingly transmitting the signal of the primary circuit to the secondary circuit. The output S 42 is input to the secondary delay circuit section 43. The signal transmission unit 42 uses a circuit having a general-purpose insulated transmission function including a transformer or a photo-coupler.

The secondary-side delay circuit 43 uses the delay circuit DL described in the circuits -a and -b.

The operation of the circuit thus configured will be described below.

First, when the switching element Q12 is turned off,
As time t ₂ of Taiminku Bu chart shown in FIG. 2, the applied voltage Vds of the main switch link Bu element Q11 becomes zero.

The voltage detection section 41 detects the falling voltage at this time, and sets the detection signal S41 output to the signal transmission section 42 to high.

The detection signal S41 is insulated and transmitted to the secondary delay circuit 43 by the signal transmission section 42.

The secondary-side delay circuit 43 converts the transmitted detection signal S41 into a drive signal Vds, and turns on the block switch Q23.

[0163] Then, as time t ₃ in FIG. 2, terminates the main switch-on period of the ink Bu element Q11, the main switch link Bu element Q11 is turned off, the main switch link Bu element Q11 preparative Bu Lane - voltage Vds appears between the source.

When the voltage Vds rises and exceeds the threshold value of the voltage detecting section, the output S41 of the voltage detecting section 41 is inverted, and a signal for turning off the main switching element Q23 via the signal transmitting section 42 is supplied to the secondary delay circuit. The information is transmitted to the unit 43.

The secondary delay circuit 43 converts this signal into a drive signal Vds, and turns off the block switch Q23.

In this way, the DC / DC converter of the circuit directly detects the voltage applied to the primary switching element Q11 on the primary side and transmits a signal to the secondary side to drive the block switch Q23.

In the DC / DC converter having such a configuration, even when the time required for the voltage Vds of the primary-side main switching element to reach the zero voltage greatly changes due to input fluctuation or load fluctuation, the main switching element does not change. Is directly detected, it is easy to make the voltage Vds zero.

Next, a fourth embodiment of the DC / DC converter of the present invention described with reference to FIG. 1 will be described.

FIG. 19 shows a DC / DC converter using secondary-side synchronous rectification.
FIG. 3 is a diagram illustrating a configuration of a DC converter. Also, in the circuit shown in the figure, a part of the smoothing inductor Ni and the transformer T1 are integrated. (Hereinafter, this circuit is called circuit-a.)

In the above-mentioned circuits, a soft switching circuit is applied to a system using a timer for secondary rectification. However, a synchronous rectification system in which the secondary rectification is constituted by an active switching element such as a MOSFET is also used. All the circuit examples of the circuit to can be applied as they are.

Also, the applicant's patent application, Japanese Patent Application No. 200
In No. 0-26677, as shown in FIG. 24, an inductor winding Ni is inserted between a rectifier circuit and an output capacitor C30, and this inductor winding Ni is connected to a winding N of a transformer T1.
By winding on the same core as p and Ns, the ripple current can be reduced, the reactance ratio between the secondary winding Ns and the inductor Ni, and the off duty D of the main switching element Q11. It is disclosed that if the 'are equal, the ripple current can be reduced to zero.

In the DC-DC converter of the circuit-a shown in FIG. 19, in addition to the secondary-side synchronous rectification, a part of the smoothing inductor winding as described above is integrated with a transformer, and a small-sized absorber for absorbing a refill current. 3 shows a circuit to which an inductor Ni is externally attached.

In the circuit of FIG. 19, a forward ゛ synchronous rectifier
Q21 is arranged at a position corresponding to the forward rectifier D21 in the circuit-b shown in FIG. 15, and the block switch Q23 is arranged to connect the source terminal of the forward synchronous rectifier Q21 and the source terminal of the block switch Q23, The gate terminal of the forward ゛ synchronous rectifier Q21 is connected to the forward ゛ winding Nsr1. With this configuration, the forward winding Nsr1 can be shared for driving the forward synchronous rectifier Q21 and for driving the block switch Q23, and a drive circuit can be configured without adding a separate winding.

The flywheel synchronous rectifier Q22 is arranged at a position corresponding to the flywheel rectifier D22 in the circuit-b shown in FIG. 15, and the gate is connected to the voltage generating terminal of the forward winding Nsr2.

The rest of the configuration is the same as that of the above-described circuit-b, and the same circuit as that of the circuit-b is used for the delay circuit DL for setting the period for blocking the forward current.

A MOSFET or the like is used for the secondary-side synchronous rectifiers Q21 and Q22 and the block switch Q23. Tires D21, D22, D23 and capacitors C21, C22, C23 connected in parallel to each element are MOS
Refers to the parasitic element of FET.

The operation of the circuit-a having such a configuration is shown in FIG.
Description will be made using a time chart of 0.

The synchronous rectification is driven by a drive signal synchronized with a timing at which a current flows through each rectifier in the forward rectifier Q21, and operates at the same timing as the time rectification. FIG. 20 is a time chart of the operation waveform of the circuit-a. The symbols of each waveform in FIG. Main switching element Q11 voltage Vds-Q11 Main switching element Q11 current Ids-Q11 sub switching element Q12 current, Ids-Q12 forward ゛ Synchronous rectifier Q21 drive signal Vgs-Q21 forward ゛ Synchronous rectifier Q21 voltage Vds-Q21 forward ゛ Synchronous rectifier Current of Q21 Ids-Q21 Block switch Drive signal of rectifier Q23 Vgs-Q23 Block switch Voltage of rectifier Q23 Vds-Q23 Block switch Current of rectifier Q23 Ids-Q23 Flywheel Drive signal of synchronous rectifier Q22 Vgs-Q22 Flywheel Synchronous rectifier Q22 Voltage Vds-Q22 Flywheel Current of synchronous rectifier Q22 Ids-Q22

In the figure, during (t ₀ -t ₁ ), when the switching element Q12 is turned off, the voltage Vds of the main switching element Q11 is turned off.
-Q11 decreases, and the voltage of the secondary winding Ns of the transformer T1 is inverted. In the secondary side rectifier circuit, the forward synchronous rectifier Q21 and the block switch Q23 are off, the flywheel synchronous rectifier Q22 is on,
The current Ids-Q22 is flowing through the flywheel synchronous rectifier Q22.

In (t ₁ -t ₂ period), the gate voltage Vgs-Q21 of the forward synchronous rectifier Q21 is inverted with the decrease of the voltage Vds-Q11 of the main switching element Q11, and the forward synchronous rectifier Q21 is turned on. Block switch Q2 connected in series with forward synchronous rectifier Q21
3, the off state is maintained by the delay circuit, so that the current Ids-Q21 does not flow through the forward / synchronous rectifier Q21.

[0181] In (t ₂ -t ₃ period), the voltage Vds-Q11 of the main switch link Bu element Q11 is turning the main switch link Bu element Q11 in becomes zero time t _2. The voltage Vgs-Q23 is applied to the gate of the block switch Q23, and the block switch Q23 is turned on. Then, the current Ids-Q21 starts flowing to the forward synchronous rectifier Q21, and the flywheel synchronous rectifier Q21
The current Ids-Q22 of 22 decreases, and the two currents are switched.

[0182] (t ₃ -t ₄ period), the turning off the main switch link Bu element Q11 at time t ₃ of the.

In (t ₄ -t ₅ period), the forward ゛ synchronous rectifier Q21
Gate drive winding Nsr1 voltage is inverted, forward synchronous rectifier
Q21 turns off. When the forward synchronous rectifier Q21 is turned off, the timer D22 connected in parallel with the flywheel synchronous rectifier Q22 conducts and the current is switched.

In the period (t ₅ -t ₆ ), current starts to flow through the tire D12 connected in parallel with the switching element Q12. By turning on the switching element Q12 during this period, the switching element Q12 becomes ZCS. The block switch Q23 turns off after the forward synchronous rectifier Q21 turns off. Since the forward synchronous rectifier Q21 is already off, the current Ids-Q23 flowing through the block switch Q23 becomes zero, and when the block switch Q23 is turned off,
ZCS. Since the block switch Q23 turns off within the range of t5 ≦ t <t7, the loss of the block switch Q23 during this period is zero.

In the period (t ₆ -t ₇ ), the current flowing through the timer D12 becomes zero, and all the current flows through the switching element Q12. Returns to the state of t ₀ at time t _7.

In the circuit using the secondary-side synchronous rectification method shown in the above-mentioned circuit-a, soft switching can be realized by the same circuit as that of the automatic rectification method. Further, in the present circuit, the drive winding can be omitted by sharing the drive winding of the block switch and the drive winding of synchronous rectification.

FIG. 21 shows a modified circuit example of the circuit-a described in FIG. (Hereinafter, this circuit is referred to as circuit-b.)

In the figure, the difference from the circuit-a described with reference to FIG. 19 is that the source terminal of the block switch Q23 is connected to the train terminal of the flywheel rectifier Q22, and the driving winding Nsr2 is connected to the delay circuit DL. The point connected to the input. The rest of the configuration is the same as that of the above-described circuit-a, and the delay circuit DL for setting the period for blocking the forward current is also provided by the circuit-a.
Use the same circuit as a.

The operation of the above circuit-b is as follows.
Since this is the same as the circuit-a shown in FIG. 19, the description is omitted.

As described above, the DC / DC converter of the present invention, like the circuit-a and the circuit-b, can realize the soft switching in the secondary-side synchronous rectification system using the same circuit as the time-auto rectification system. Further, by sharing the drive winding of the block switch and the drive winding of synchronous rectification, the drive winding can be omitted.

The foregoing description has been directed to specific preferred embodiments for the purpose of describing and illustrating the present invention. Therefore, the present invention is not limited to the above-described embodiment, but includes many more changes and modifications without departing from the essence thereof.

For example, in the circuit of the present invention, as shown in FIG. 25A, a series circuit of a capacitor C13 and a switching element Q12 is connected in parallel with a main switching element Q11. As shown in FIG. 25B, the series circuit is connected in parallel with the secondary winding Np, and FIG.
As shown in (5), the same effect as described above can be obtained even when the series circuit is applied to a circuit connected in parallel with the tertiary winding Nt.

[0193]

As is apparent from the above description,
According to the present invention, the following effects can be obtained. Claims 1 to 11
In the invention described in the above, the DC / D
The soft switching of the C converter can be realized.

The windings (for example, the forward winding Nsrb and the flyback winding Nsrb2 in the above circuit) for generating a drive signal for driving the block switch have the same polarity as the secondary voltage. Since either a forward winding generating a voltage or a flyback winding generating a voltage having a polarity opposite to that of the secondary voltage can be used, a wide variety of circuit variations can be applied.

Further, the delay circuit for generating the drive signal can be constituted by a simple circuit using only an inductor, a capacitor, a resistor, and a zener timer. In a circuit using an IC, drive circuit loss can be further reduced.

According to the twelfth and thirteenth aspects of the present invention, the same effect as described above can be realized even if the block switch is driven by using a floating output tri-life IC.

According to the fourteenth aspect, by driving the block switch in accordance with the timing of the voltage change of the main switching element, the voltage Vds of the main switching element on the primary side reaches zero voltage due to input fluctuation or load fluctuation. Even when the time required for the switching changes greatly, the voltage Vds of the main switching element is directly detected, so that the voltage Vds can be easily reduced to zero.

According to the fifteenth aspect, even in a DC / DC converter in which the secondary side rectifier circuit is a synchronous rectifier system, soft switching can be realized by the same circuit as that of the timer rectifier system. Further, by sharing the drive winding of the block switch and the drive winding of synchronous rectification, the drive winding can be omitted.

According to the sixteenth aspect of the present invention, the output of the secondary rectifier circuit is output to the load circuit via the inductor winding wound on the same core as the transformer, so that the ripple current can be reduced. , And soft switching can be performed, so that the efficiency of the DC / DC converter can be further improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of a DC / DC converter according to the present invention.

FIG. 2 is a timing chart of the DC / DC converter according to the present invention.

FIG. 3 is an actually measured waveform diagram of the DC / DC converter according to the present invention.

FIG. 4 is a configuration diagram showing a specific configuration (circuit-a) of the present invention.

FIG. 5 is a circuit diagram showing one embodiment of a delay circuit of circuit-a.

FIG. 6 is an operation waveform diagram of the delay circuit of FIG. 5;

FIG. 7 shows a non-inverting output drive IC used in the circuit-a.
FIG. 3 is a circuit diagram illustrating an embodiment of a delay circuit including:

FIG. 8 is a circuit diagram showing one embodiment of a delay circuit including an inversion type output drive IC used in the circuit-a.

FIG. 9 is a configuration diagram showing a specific configuration (circuit-b) of the present invention.

FIG. 10 shows an inverted output drive IC used in the circuit-b.
FIG. 3 is a circuit diagram illustrating an embodiment of a delay circuit including:

FIG. 11 shows a non-inverting output drive I used in the circuit-b.
FIG. 4 is a circuit diagram illustrating an embodiment of a delay circuit including C.

FIG. 12 is a configuration diagram showing a specific configuration (circuit-a) of the present invention.

FIG. 13 is a circuit diagram showing one embodiment of a delay circuit having a non-inverting type floating output drive IC used for the circuit-a.

FIG. 14 is a circuit diagram showing one embodiment of a delay circuit including an inversion type floating output floating drive IC used for the circuit-a.

FIG. 15 is a configuration diagram showing a specific configuration (circuit-b) of the present invention.

FIG. 16 is a circuit diagram showing one embodiment of a delay circuit including an inversion type floating output drive IC used for the circuit-b.

FIG. 17 is a circuit diagram showing one embodiment of a delay circuit including a non-inverting type floating output drive IC used for the circuit-b.

FIG. 18 is a configuration diagram showing a specific configuration (circuit) of the present invention.

FIG. 19 is a configuration diagram showing a specific configuration (circuit-a) of the present invention.

FIG. 20 is a timing chart of the circuit-a.

FIG. 21 is a configuration diagram showing a specific configuration (circuit-b) of the present invention.

FIG. 22 is a circuit diagram showing an example of a conventional DC / DC converter.

FIG. 23 is a circuit diagram showing an example of a conventional DC / DC converter.

FIG. 24 is a circuit diagram illustrating an example of a DC / DC converter including an output inductor.

FIG. 25 is a diagram showing another configuration of the present invention.

[Explanation of symbols]

G11, G12 drive signal Q11, Q12, Q21, Q22, Q23 switching element DL delay circuit DR drive circuit C11, C12, C13, C21, C22, C23, C
24, C27, C30 Capacitors D11, D12, D21, D22, D23, D24, D
25, D28 diode ZD24, D27 Zener diode R24, R25, R26, R27, R28 Resistance T1 Transformer L21, L24, Ni inductor 41, 43 Non-inverted output type drive IC 42, 44 Non-inverted output type drive IC 100 Load circuit

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Seiichi Noguchi 2-93-2 Nakamachi, Musashino-shi, Tokyo F-term in Yokogawa Electric Corporation (reference) 5H006 CA02 CA12 CA13 CB02 CB07 CC02 DB01 5H730 AA14 AA15 BB23 BB57 DD04 DD32 DD42 EE04 EE08 EE13 EE19 EE65 EE72 FG01

Claims (16)

[Claims] A transformer having at least a primary winding and a secondary winding; a main switching element for intermittently supplying power from a power supply to the primary winding; and A series circuit of a capacitor for resetting the transformer by recirculating the exciting energy stored in the transformer and a sub-switching element; and a primary side control for generating a control signal for alternately turning on and off the main switching element and the sub-switching element. A DC / DC converter comprising: a circuit; a secondary rectifier circuit for rectifying power generated in the secondary winding; and a current blocking means for blocking a current flowing into the secondary rectifier circuit for a predetermined time. DC converter. 2. The DC / DC converter according to claim 1, wherein the series circuit of the capacitor and the switching element is configured to be connected to the primary winding in parallel or equivalently in parallel. converter. 3. The DC / DC converter according to claim 1, wherein the series circuit of the capacitor and the switching element is configured to be connected in parallel or equivalently in parallel to the main switching element. converter. 4. The DC / DC converter according to claim 1, wherein the series circuit of the capacitor and the switching element is configured to be connected in parallel or equivalently in parallel to the secondary winding. DC converter. 5. The transformer further includes a tertiary winding, and a series circuit of the capacitor and the switching element is configured to be connected in parallel or equivalently in parallel to the tertiary winding. The DC / D according to claim 1,
C converter. 6. The current blocking means comprises a block switch element inserted into a current path of the secondary winding and a secondary rectifier circuit, and a block switch control circuit for controlling the block switch element. 2. The DC / DC converter according to claim 1, wherein the block switch control circuit is configured to generate a drive signal for holding the block switch element in an OFF state for a predetermined period after the sub-switch element is turned off. DC converter. 7. The block switch control circuit includes: a forward winding wound around the same core as the transformer, which generates a voltage having the same polarity as the secondary winding; and a voltage generating terminal of the forward winding. An anode connected to a series circuit of an inductor (L24) and a resistor (R24) having one end connected thereto, and a gate of the block switch (Q23);
A zener timer (ZD24) having a cathode connected to the other end of the series circuit of the inductor (L24) and the resistor (R24); and a cathode of the zener timer (ZD24) connected to a reference potential (NG) of the forward winding. 7. The DC / D according to claim 6, wherein the DC / D is constituted by a capacitor (C24).
C converter. 8. The block switch control circuit according to claim 1, wherein said block switch control circuit is wound around the same core as said transformer, generates a voltage of the same polarity as said secondary winding, and is inputted to an input terminal (IN). Non-inverting output type drive IC for converting a signal into a drive signal for the block switch (41)
And a resistor (R) connecting the voltage generating terminal of the forward winding to the input terminal (IN) of the non-inverting output type drive IC (41).
24) and a series circuit of a diode (D24), and an input terminal (I) of the non-inverting output type drive IC (41).
7. The DC / DC converter according to claim 6, comprising a parallel circuit of a capacitor (C24) and a diode (D25) connecting N) to a reference potential (NG) of the forward winding. 9. A block switch control circuit, comprising: a forward winding wound around the same core as the transformer and generating a voltage of the same polarity as the secondary winding; and a voltage generated at the winding of the transformer. Power supply circuit for generating a stable voltage from the inverter, and an inverted output type drive IC for converting an inverted signal of a signal input to an input terminal (IN) into a drive signal for the block switch
(42), a voltage dividing circuit for dividing a voltage generated by the forward winding, an output voltage of the voltage dividing circuit being input to a base, and an emitter being connected to a reference potential (NG) of the forward winding. A transistor (Q24); a resistor (R25) for applying the stable voltage to the collector of the transistor (Q24); and an input terminal (IN) of the inverted output type drive IC (42). (R24) input to the input terminal (IN) of the inverting output type drive IC (42)
7. A DC / DC converter according to claim 6, comprising a capacitor (C24) that connects a forward potential to a reference potential (NG) of the forward winding. 10. The block switch control circuit, wherein the fly switch winding is wound around the same core as the transformer, generates a voltage having a polarity opposite to that of the secondary winding, and is supplied to an input terminal (IN). Output type drive IC for converting an inverted signal of the generated signal into a drive signal for the block switch
(42) and a resistor (R) for inputting the voltage generating end of the flyback winding to an input terminal (IN) of the inverted output type drive IC (42).
24) and a series circuit of a diode (D24), and an input terminal (IN) of the inverted output type drive IC (42).
7. A parallel connection circuit comprising a capacitor (C24) and a diode (D25), which is connected to a reference potential (NG) of the flyback winding.
C / DC converter. 11. The block switch control circuit is wound on the same core as the transformer, and generates a flyback winding that generates a voltage having a polarity opposite to that of the secondary winding, and generates a flyback winding on the transformer winding. A power supply circuit for generating a stable voltage from a voltage; a voltage dividing circuit for dividing a generated voltage of the flyback winding; an output voltage of the voltage dividing circuit being input to a base; and an emitter serving as a reference for the flyback winding. A transistor (Q24) connected to the potential (NG); a resistor (R25) for applying the stable voltage to the collector of the transistor (Q24); and a collector voltage of the transistor (Q24) to an input terminal (IN). , A non-inverting output type drive IC (4) for converting a signal inputted thereto into a drive signal of the block switch.
1) and an input terminal (I) of the non-inverting output type drive IC (41).
7. The DC / DC converter according to claim 6, comprising a capacitor (C24) for connecting N) to a reference potential (NG) of the flyback winding. 12. The non-inverting output type drive IC (41).
Is a floating output type non-inverting output type drive IC
9. The apparatus according to claim 8, wherein the apparatus is configured using (43).
And the DC / DC converter according to 11. 13. The inverting output type drive IC (42).
Is a floating output type inverted output type drive IC
10. The apparatus according to claim 9, wherein the apparatus is configured using (44).
And the DC / DC converter according to 10. 14. The block switch control circuit detects a turn-off of the sub-switch element according to a voltage change of the main switch element, and after the sub-switch element is turned off, sets the block switch element to an Off state for a predetermined period. 7. The DC according to claim 6, wherein the DC signal is configured to generate a driving signal to be held.
/ DC converter. 15. The DC / DC converter according to claim 1, wherein the secondary rectifier circuit is a synchronous rectifier rectifier circuit using a synchronous rectifier. 16. An apparatus according to claim 1, wherein an output of said secondary rectifier circuit is output to a load circuit via an inductor winding wound around the same core as said transformer. 4. The DC / DC converter according to 1.