JPH1169803A - Switching power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the enhancement of the power conversion efficiency of a switching power supply, by using FET for synchronous rectification and a circuit for making gate drive waveform constant, and further adding a high- speed off-circuit when the gate waveform is off. SOLUTION: In a low-loss gate drive circuit using a synchronous rectification circuit, FET's 6, 10 are fed with a gate voltage obtained by stabilizing the secondary winding voltage of a transformer 5 through the transistors 7, 10 for clamp and the diodes 8, 12 in a waveform shaping circuit. A diode for circuit interruption is connected with the gate of the FET 10 for reflux in a synchronous rectification circuit 18 between a transistor 11 for clamp and a transistor 13 for discharge in order to discharge the charges in the gate capacitance through the transistor 13 at high speed. As a result, when the gate voltage is off, the voltage is quickly discharged through transistors 9, 13, and the diodes built in the FET's are turned off before they are turned on. Thereby loss is reduced. As a result, the risk of gate breakdown can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a switching power supply, and more particularly to a high-efficiency switching power supply using synchronous rectification.

[0002]

2. Description of the Related Art Conventionally, this kind of low-loss gate drive circuit for synchronous rectification is used in a switching power supply for the purpose of reducing power consumption and improving the reliability of equipment.

For example, Japanese Patent Application Laid-Open No. 8-336282 discloses a technique for shaping a synchronous rectification gate waveform, eliminating the risk of gate destruction, and reducing the loss of a gate drive circuit.

[0004]

However, the above-mentioned prior art has the following drawbacks.

[0005] The first problem is that in the prior art,
There is a problem that the loss is slow when the gate drive voltage waveform is "off".

The reason is that the built-in diode of the synchronous rectification FET is turned on.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and has been made to solve the above-mentioned disadvantages inherent in the prior art. Therefore, an object of the present invention is to reduce the loss of a synchronous rectification FET and to reduce switching. An object of the present invention is to provide a novel switching power supply capable of improving the power conversion efficiency of a power supply.

Another object of the present invention is to eliminate the risk of gate destruction of a synchronous rectification FET.

[0009]

In order to achieve the above object, a switching power supply according to the present invention comprises a synchronous rectifying FE.
T, a circuit that makes the gate drive waveform constant is used, and a circuit that turns off at high speed when the gate waveform is off is added.

In the present invention, if the gate drive waveform of the synchronous rectification FET is made constant and is kept constant even from the lowest input voltage to the highest input voltage, the loss of the FET can be reduced.

Further, there is no danger of gate destruction.

By turning off the synchronous rectification FET gate drive waveform at a high speed, the FET built-in diode can be turned off before the diode with built-in FET is turned on, so that the loss can be reduced.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Referring to FIG. 1, one embodiment of the present invention is a DC input voltage 1, a main switching element (M
OS FET) 3, 4, transformer 5, synchronous rectifier circuit 1
7, 18, a smoothing circuit 19, a load 16, and the like.

FIG. 2 is a time chart showing the operation of the embodiment of the present invention shown in FIG.

The operation of the present invention will be described with reference to FIGS.
_Are driven by the gate voltages VG1 and _VG2 having a dead time, and are repeatedly turned on and off.

During the period from t _{1 to} t ₂ when the primary side main switching element 4 is “on”, the secondary side synchronous rectification FET is used.
The FET 6 is turned "ON" by the gate voltage of 6, and the rectified voltage Vo is applied to the load 16 through the smoothing circuit 19.

The period t ₂ ~t ₃ is a period during which the main switching device 3, 4 is "off", the peak value Ip ⁺ parasitic capacitance 20 of the excitation current i _m flowing in the transformer 5 during this time Charge and discharge.

The period t _{3 to} t ₄ is a period in which the main switching element 4 is “off” and the main switching element 3 is “on”. 5
Are clamped at both ends of the secondary ticket line.

During this period, the FET 10 is turned on by the gate voltage of the secondary-side reflux FET 10, and the FET 1
0, the load current circulates to the load 16 and the rectified voltage Vo
Is applied.

Next, a low-loss gate drive circuit using a synchronous rectifier circuit will be described with reference to FIG.

Here, it should be noted that the secondary line voltage of the transformer 5 is not directly applied to the FET 6 and the FET 10 but the transistor 7 and the diode 8
The point is that a stabilized gate voltage is applied by the waveform shaping circuit constituted by (the transistor 11 and the diode 12).

That is, the FE for synchronous rectification of the synchronous rectifier circuit 17
The gate circuit of T6 is provided with a waveform shaping circuit including a Zener diode 8 for generating a constant voltage and a clamping transistor 7 for clamping the gate voltage of the FET 6 below a constant voltage output from the Zener diode 8. .

On the other hand, the reflux FET 1 of the synchronous rectifier circuit 18
The zero gate circuit is connected to a Zener diode 12 for generating a constant voltage, and a clamping transistor 11 for clamping the gate voltage of the FET 10 to a voltage equal to or lower than the constant voltage output from the Zener diode 12.

Normally, in the case of the conventional example in which the gate voltage is directly applied to the FET immediately from the line voltage of the transformer 5 (FIG. 3), the V _DS1 of the primary side main switching element 4 is changed with the change of the input voltage. The voltage changes. That is, if the input voltage is low, a low voltage is generated, and if the input voltage is high, a high voltage is generated, and is applied to the secondary side according to the ticket ratio of the transformer 5.
If the line voltage is high, the gate voltages of the synchronous rectification FETs 6 and 10 also increase, and the loss of the FETs 6 and 10 increases, and the efficiency decreases. Also, when the gate voltage increases, the FET
There is also the risk of 6, 10 gate breakdown.

Another feature is that a conventional FE for synchronous rectification is used.
In T gate drive circuit (technique described in Japanese Patent Laid-Open No. 8-336282), slow time "off" gate voltage, was one of the causes of loss (Fig. 4V _G1 ', V _G4' reference) .

In order to solve this problem, the present invention uses the transistor 9 (13) of FIG. 1 to turn off the gate voltage.
This is a circuit whose purpose is to rapidly withdraw the voltage, turn off at high speed before the diode built in the FET turns on, and reduce the loss.

That is, the synchronous FET 6 of the synchronous rectifier circuit 17
Has a discharge transistor 9 for rapidly extracting (discharging) the charge charged in the gate capacitance of the FET 6, a connection portion between the base of the transistor 9 and the gate of the FET 6, and a clamping transistor of the waveform shaping circuit. A diode 21 for disconnecting the circuit is connected between the emitter 7 and the connection between the base of the discharging transistor 9.

Similarly, the freewheeling FET of the synchronous rectifier circuit 18
The gate of the FET 10 has a discharging transistor 13 for rapidly extracting (discharging) the charge charged in the gate capacitance of the FET 10, a connection portion between the base of the discharging transistor 13 and the gate of the FET 10, and a waveform shaping circuit. A circuit disconnecting diode 22 is connected between the connection between the emitter of the clamping transistor 11 and the base of the discharging transistor 13.

Next, the operation of turning off the FET 10 at high speed by the transistor 13 will be described.

[0032] Figure 1, referring to FIG. 2, now the output voltage Vs of the transformer 5 ^- When becomes 0V at time t _1, the emitter of the transistor 11 through the collector of the "ON" to have the transistor 11 becomes 0V, The base of the discharging transistor 13 connected to this emitter also becomes 0V.
As a result, the transistor 13 is turned on,
The gate of the FET 10 is grounded, and the electric charge charged in the gate capacitance of the FET 10 is extracted (discharged) at a high speed. The diode 22 is connected to the transistor 13
Is turned on, the emitter of the transistor 11 and the gate of the FET are cut off on the circuit, and the "on" operation of the transistor 13 is promoted. As a result of the above operation, the "on" operation of the diode built in the FET 10 is prevented.

Since the discharging transistor 9 and the circuit disconnecting diode 21 operate in the same manner as described above, their description is omitted.

In the present invention, the primary-side switching circuit is not only an active clamp type switching circuit as shown in FIG. 1, but also a half bridge type, a one-stone forward type, or a class E resonance type. You may.

[0035]

The present invention is constructed and operates as described above, and according to the present invention, the following effects can be obtained.

The first effect is that the efficiency can be increased by using a transistor and a Zener diode in the synchronous rectification gate drive circuit. Also, the risk of gate destruction can be eliminated.

The reason is that even if the input voltage is high, the loss can be reduced and the gate voltage does not increase because the gate voltage is constant (low).

The second effect is that the efficiency can be improved by using a discharging transistor in the synchronous rectification gate drive circuit.

The reason is that the gate voltage is quickly turned off.
This is because the diode with the built-in FET does not turn on and the loss can be reduced.

[Brief description of the drawings]

FIG. 1 is a detailed circuit configuration diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart showing waveforms at various parts in the configuration shown in FIG.

FIG. 3 is a conventional circuit diagram.

FIG. 4 is a diagram showing waveforms at various parts of the circuit shown in FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Input power supply 2, 15 ... Capacitor 3, 4, 6, 10 ... MOS FET 5 ... Transformer 7, 9, 11, 13 ... Transistor 8, 12 ... Zener diode 14 ... Choke coil 16 ... Load 17, 18 ... Synchronous rectification Circuit 19: Smoothing circuit 20: Parasitic capacitance 21, 22: Diode

Claims (7)

[Claims] 1. A switching power supply which supplies a DC input voltage to a primary wire of a transformer and periodically turns "on" and "off", wherein both ends of a secondary wire of the transformer are provided while the switching means is "off". And a rectification / smoothing means for rectifying / smoothing the secondary wire output of the transformer, wherein a rectification / smoothing circuit of a synchronous rectification system is used for the rectification / smoothing means. A switching power supply, wherein a first waveform shaping means is provided between a gate of a synchronous rectification field-effect transistor of a synchronous rectification / smoothing circuit and one end of a secondary wire of the transformer. 2. The apparatus according to claim 1, further comprising a second waveform shaping means provided between the gate of the free-flow field effect transistor of the synchronous rectification / smoothing circuit and the other end of the secondary wire of the transformer. The switching power supply according to claim 1. 3. The switching power supply according to claim 2, wherein the first and second waveform shaping units further include a clamping transistor and a zener diode that generates a constant voltage. 4. The semiconductor device according to claim 1, further comprising a first discharging means provided at a gate of said field effect transistor for synchronous rectification for discharging electric charges charged in a gate capacitance of said field effect transistor for synchronous rectification at a high speed. The switching power supply according to claim 1. 5. The method according to claim 1, further comprising the step of: providing, at the gate of said reflux field effect transistor, a second discharging means for rapidly discharging the charge charged in the gate capacitance of said reflux field effect transistor. 4. The switching power supply according to 4. 6. The method according to claim 1, wherein the first discharging means includes a first discharging transistor connected to a gate of the synchronous rectification field-effect transistor, and a first circuit disconnecting diode. The switching power supply according to claim 4. 7. The apparatus according to claim 1, wherein said second discharging means includes a second discharging transistor connected to a gate of said free-wheeling field effect transistor, and a second circuit disconnecting diode. Item 6. The switching power supply according to Item 5.