JP2001284349A - High dielectric constant gate oxide for silicon substrate devices - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an improved gate oxide material for a silicon substrate device and a method for manufacturing the same. SOLUTION: A high dielectric rare earth oxide of the Mn ₂ O _{3 type} (for example, Gd ₂ O ₃ or Y ₂ O ₃ ) is cleaned under a partial pressure of oxygen lower than or equal to 10 ⁻⁷ torr. 100) Normal ultra-thin SiO grown on substrate surface
₂ Acceptable gate oxide (dielectric constant (ε ≒ 18) that eliminates tunnel currents present in the dielectric and avoids the formation of a native oxide layer at the interface between the silicon substrate and the dielectric
And in terms of thickness). Epitaxial films can be grown on regular silicon substrates to create high dielectric gate oxides.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to improved gate oxide materials for silicon-based devices and methods for making the same, and more particularly to Gd ₂ O ₃ or Y _2.
Using a rare earth oxide such as O ₃ (having a dielectric constant ε on the order of 18) to produce a gate oxide with desired insulating properties while maintaining a thickness greater than about 10 ° tunnel depth It is about doing.

[0002]

2. Description of the Related Art As integrated circuit technology advances, MOSF
The gate length of ET is getting shorter and shorter. further,
Gate dielectrics, typically gate oxides, are becoming increasingly thinner. Very thin gate oxide (eg,
(Less than 50 °) is often necessary for submicron MOS devices.

[0003] As device dimensions are rapidly shrinking with advances in technology, the electric field of thin gate oxides continues to increase. An important part of such an increasing electric field is the increased trapping at the oxide interface or in thin oxides. Trap generation by alternating traps and trapping of channel electrons leads to low frequency (1 / f) noise and increased transconductance (g _m ) degradation. 50Å
For the following ultra-thin gate oxides, the tunnel current is also significant, resulting in accelerated degradation of device characteristics. Indeed, the thickness of normal SiO ₂ gate oxide is now approaching the 10 ° quantum tunnel limit.

[0004] Instead of successive attempts to reduce the gate oxide SiO ₂ thickness, several groups have developed SiO ₂ layers.
An alternative insulator having a dielectric constant (ε) substantially greater than ₂ (ε = 3.9), and thus the dielectric thickness can be increased proportionally (thus, the tunneling current through the oxide (Reduced opportunities). S at the substrate / dielectric interface during the high temperature annealing operation
iO ₂ or to prevent the reaction causing the formation of metal silicide, it is desirable dielectric is thermodynamically stable with respect to the silicon surface. Currently, several "high dielectric" oxide is considered (eg Al ₂ O _3, Ta ₂
O _3, TiO ₂₎ interfacial SiO ₂ layer is produced at least 10Å thick while also growing gate oxide in each case. Another approach uses a relatively thin SiN _x barrier layer, which is first deposited on the silicon surface to prevent negative oxide growth. However, the use of a barrier layer then requires a total "effective" oxide thickness of greater than 15 ° with another unacceptable result.

[0005]

Accordingly, there is a need in the art for a "thin" silicon substrate device which prevents the formation of a native SiO ₂ layer but which exhibits an effective thickness approaching 10 °. There remains a need for dielectric materials to be used as gate dielectrics.

[0006]

A need remains in the art for improved gate oxide materials for silicon-based devices and methods of making the same, and more particularly for Gd ₂ O ₃ or Y ₂ O. ₃ (eg, exhibiting a much higher dielectric constant ε than SiO ₂ (about 4) on the order of 18)
The present invention relates to fabricating a gate oxide having desired insulating properties while maintaining a thickness greater than about 10 ° tunnel depth using a rare earth oxide such as

In accordance with the present invention, Gd ₂ O _{3 is} deposited on a “clean” silicon substrate surface using ultra-high vacuum (UHV) deposition.
Alternatively, a film of Y ₂ O ₃ grows. During growth, increase the oxygen partial pressure to 1
It has been found that by limiting to less than ^0-7 , oxidation of the silicon substrate surface is completely avoided. Both epitaxial and amorphous films have been found to produce oxides with the desired high dielectric constant properties.

According to the present invention, a single domain (110)
To promote the formation of an oriented Gd ₂ O ₃ or Y ₂ O ₃ film,
Preferably, a vicinal Si (100) substrate is used. In the preferred embodiment, a 4 ° miscut substrate can be used.

For example, for a corresponding SiO ₂ thickness of 19 °, G
10 ^-1 A / cm ² to 10 ^-5 A at ¹ V for the d ₂ O ₃ layer
A post-treatment gas anneal can also be used to improve the leakage current density at a value of / cm ² .

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS Other aspects of the present invention will become apparent from the following description and the accompanying drawings.

[0011] Rare earth oxides are suitable candidates for various semiconductor applications based on thermodynamic energy considerations. According to the present invention, the dielectric Gd ₂ O ₃ (ε~12) as a gate oxide on a silicon (100) surface or Y ₂ O ₃ (epsilon
18) can be formed. Both substances are
While exhibiting the required “high” dielectric properties when compared to the dielectric properties of SiO ₂ (ε = 3.9), Y ₂ O ₃ has a high dielectric constant and the absence of magnetic ions in the oxide, It is considered preferable.

An important aspect of the present invention is the use of vicinal Si to eliminate the formation of undesirable domains in the grown oxide.
Using a (100) substrate, thus providing a single domain (110) oriented gate oxide.
FIG. 1 shows a micro-tilt Si which is “miscut” at a predetermined tilt angle.
An example of a (100) substrate 10 is shown, where it has been found that a tilt angle in the range of 4 ° to 6 ° is preferred. The miscut plane 12 exhibits a double atomic layer surface step 14, and is therefore about 80 ° (for a 4 ° miscut) to nucleate the growth of a single variant of Gd ₂ O ₃ or Y ₂ O _3. Give a single-domain silicon conterrace with a spacing).

[0013] A multi-chamber ultra-high vacuum system can be used to make the high dielectric gate oxide structures of the present invention. Prior to dielectric growth, the silicon wafer is cleaned and then hydrogen passivated (eg, using buffered HF acid) to create a clean surface. Next, the substrate is heated to a temperature in the range of 450 ° C. to 500 ° C., for example, to produce a silicon surface free of impurities or oxides. next,
The ceramic source of powder-filled Gd ₂ O ₃ or Y ₂ O ₃ is U
Used as an electron beam source in the HV system to supply a desired epitaxial dielectric film deposit. According to one aspect of the invention, the oxygen partial pressure in the UHV chamber is 10 ^{-7 torr} during growth.
It must be kept below rr, where such pressure has been found to essentially eliminate the formation of a native SiO ₂ layer at the interface between the substrate and the dielectric. As mentioned above, the ability to control the structure and chemistry of the interface at the atomic layer scale is critical.

The presence / absence of such native oxide films was studied by performing infrared absorption analysis of the Gd ₂ O ₃ oxide film and the associated interface with the underlying silicon substrate. To maintain the integrity of the Gd ₂ O ₃ film during the analysis, a thin amorphous silicon film was deposited in situ on the Gd ₂ O ₃ film before exposure to air. The presence of this silicon film enabled HF etching of the amorphous front and crystalline back silicon surfaces, ensuring that only the native oxide at the interface contributed to the IR absorption spectrum, leaving the H-termini. . For comparison, each wafer containing the Gd ₂ O ₃ dielectric film was compared to a similarly HF etched silicon substrate (without deposition of the Gd ₂ O ₃ film). The absorption results clearly show a Gd ₂ O ₃ phonon band at 600 cm ⁻¹ , where the intensity was of the size within the film thickness.
For the same crystal as the amorphous Gd ₂ O ₃ sample,
O ₂ TO (1050 cm ⁻¹ ) or LO (1200 to 1200)
1250 cm ^-1) to measurable SiO ₂ - deletion of the relevant feature was present.

The crystal of Gd ₂ O ₃ or Y ₂ O ₃ has an isomorphous Mn ₂ O ₃ structure having a large lattice constant (10.81 ° and 10.60 °, respectively). Double symmetry (11
0) Orientation Gd ₂ O ₃ or Y ₂ O ₃ is a four-fold symmetric normal (1)
00) grown on a silicon surface, resulting in the undesired generation of two (110) variants with the same probability in the growth plane. In particular, the growth of these two variants with the same probability leads to relatively high leakage current oxides,
Obviously unfavorable in terms of equipment. According to the present invention, the use of a vicinal silicon substrate as shown in FIG.

[0016] Hereinafter, further detailing can also be employed post-growth method in the method of the present invention, the rear forming gas anneal 10 ^-1 A / c with 1V in equivalent SiO ₂ thickness of 19Å
m ² to 10 ⁻⁵ A / cm ² has been shown to provide improved leakage current density. Amorphous Y ₂ O ₃ film is 10Å S
It can be formed on a normal silicon surface having a leakage current as low as 10 ⁻⁶ A / cm ² at 1 V at a thickness corresponding to iO ₂ .

FIG. 2 shows three different Gd's._TwoO_ThreeAlong the surface of the membrane
1 shows a vertical X-ray diffraction scan. Scan A in FIG.
4Å Gd_TwoO_ThreeScan B
Gd with a thickness of 125mm_TwoO_ThreeCombined with a membrane,
Scan C is 196 mm thick Gd _TwoO_ThreeCombined with membrane
It is. Referring to FIG. 2, the fringe pattern of each scan
The solid between the air / oxide and oxide / silicon interfaces
This is due to the existence of interference. Fringe cycle is inverse to film thickness
Although proportional, the attenuation of the fringe amplitude is
It is a measure. Therefore, the looseness shown in each scan
Decay shows that each grown Gd_TwoO_ThreeThe membrane is very uniform
One conclusion is drawn. Figure 2 (The following figure is also
Various oxide thicknesses discussed above are examples.
Should be considered. Generally, according to the present invention
The manufactured high dielectric oxides are, for example, 10 ° to 50 °.
Any intended thickness, including any thickness within the range of
To provide the desired gate dielectric properties for placement applications
it can.

The Gd ₂ O ₃ gate dielectric film grown on a vicinal (100) silicon substrate according to the present invention exhibits a broad peak near 2θ = 47.5 ° for (440) reflection,
It was found that the peak became sharper as the film thickness increased. FIG. 3 shows three different Gd ₂ O ₃ associated with FIG.
In particular, a 360 ° φ scan set around a plane perpendicular to the in-plane component of the {222} reflection for the set of. In each case, the grown dielectric is a type of domain having a [001] axis of Gd ₂ O ₃ parallel to the silicon step edge 16 (see FIG. 1), ie, a [110] axis of the miscut substrate 10. It is mainly oriented within. The {222} reflection for each dielectric thickness shown in FIG. 3 shows peaks associated with both orientations. The two weak peaks, shown as w ₁ and w ₂ in FIG. 3, are separated by π with respect to the two strong peaks, shown as s ₁ and s ₂ . Analysis of the data in FIG.
Approximately 95% of the ₂ O ₃ is grown in the preferred “strong” orientation, with approximately 99% for a thick film 196 ° thick.
The conclusion is that there is an increase. This analysis leads to the conclusion that beyond a certain "critical" thickness (about 100 DEG), domains of undesired orientation start to be buried under the growing oxide.

FIG. 4 shows various Gd under various conditions._TwoO_Threedielectric
Leakage current density J as a function of gate voltage for body layer
_LIs plotted. 2-domain and single
The domain membrane is shown, after 1 hour at 400 ° C
Single domain Gd with thickness of 34 ° after gas annealing_TwoO_Three
Plot of leakage current / gate voltage for the membrane
(Indicated by “D” in FIG. 4). Referring to FIG.
Current density is unbiased (i.e.,
It is clear that the quantity voltage is essentially symmetric with respect to 0 V).
It is easy. The leakage current density of the 2-domain dielectric film is
Single domain film, especially for dielectrics thinner than 100 °
Indicates that it is much higher than the combination
You. As shown in the figure, a 44 mm thick 2-domain
The leakage current density for the^-3A / c
m^TwoAs high as. Single domain dielectric leakage
The current density is significantly improved, especially at thinner thicknesses. And
For example, J at 1V of 34 ° film_LIs about? 1 of the 2-domain film
0^-1A / cm^TwoFrom the value of about 10 for a single domain dielectric^-3
A / cm^TwoTo the value of. Grew as described above
Post-forming gas annealing (N_TwoAnd H_TwoCombination)
To further improve (ie, reduce) the leakage current density.
A little). As shown in FIG.
Forming gas annealing on one domain film reduces leakage current density
10^-FiveA / cm ^TwoThe value is further improved.

Studies of amorphous dielectric films are more suitable for device applications than crystalline films due to the absence of domain boundaries and lack of surface or interfacial strain in the case of crystalline films. Further, while the leakage current of the amorphous Gd ₂ O ₃ film is comparable to that of the amorphous Y ₂ O ₃ film, the dielectric constant of the Y ₂ O ₃ is not sensitive to the decrease in thickness and is essentially constant at about 18. At some point it shows a more compatible dielectric behavior than Gd ₂ O ₃ . FIG. 5 shows the dependence of J _L on V for a series of amorphous Y ₂ O ₃ films. As shown, the deposition of amorphous Y ₂ O ₃ film having a thickness of 45Å, the thickness of _{10Å ( "t eq") 10} -6 at 1V as compared to SiO ₂ equivalent of A / cm ² Gives low leakage current density. The leakage current density is determined by forming gas annealing (for example, temperature 4
After about 1 hour at 00 ° C.), it is improved by another order of magnitude. The values obtained are on the order of about 5 orders of magnitude better than the best ones combined with a 15 ° thick conventional SiO ₂ dielectric. Beyond this leakage current density, 10
When rapid thermal annealing (RTA) is performed at 00 ° C. for about 1 hour,
It can be seen that the Y ₂ O ₃ film remains essentially stable.

Specific capacitance (C / A) vs. voltage data for a MOS diode including a 196 ° thick Gd ₂ O ₃ single domain gate dielectric (after forming gas anneal) is given by 10
It is shown in FIG. 6 as a function of period over a range from 0 Hz to 1 MHz. The dielectric constant (ε) of such a film was measured to be about 2
A value of 0 was shown. As shown in the figure, the change from the accumulation of the behavior of the MOS diode to the consumption mode occurs at about 2 V, the reversal of the carriers (holes) is apparent, and 10 K
The ac signal accompanies the frequency up to Hz. FIG. 7 shows a thickness of 45.
The data of C / A vs. V for the amorphous Y ₂ O ₃ film of Å (after the post-growth gas annealing) is shown. The capacitor is a corresponding (or better) 10 ° thick SiO ₂
As high as 35 to 40 fF / μm ² comparable to
Has A value. It should be noted that the dielectric constant associated with this material remains at a value of 18 even for such a thin layer.

Although the present invention has been described in terms of a particularly preferred embodiment, it will be apparent to those skilled in the art that modifications may be made within the spirit and scope of the invention. For example, Gd ₂ O ₃
And Y ₂ O ₃ are discussed in detail, but various other rare earth oxides of the form Mn ₂ O _{3 in} single crystal and amorphous form are used to make high dielectric gate oxides according to the principles of the present invention. be able to.

[0023]

According to the present invention, an improved gate oxide material for silicon substrate devices can be produced.

[Brief description of the drawings]

FIG. 1 illustrates an example of a preferred vicinal silicon substrate for supporting the growth of the high dielectric gate oxide of the present invention.

FIG. 2 shows a graph of an X-ray diffraction scan for a set of _three different (110) Gd ₂ O ₃ single domain films.

FIG. 3 shows the relationship between the film thickness and the region of preferred orientation, both degenerate orientation of the Gd ₂ O ₃ film.
FIG. 9 is a diagram showing {222} reflection obtained from s).

FIG. 4 is a graph showing a leakage current density (J _L ) of a crystalline Gd ₂ O ₃ film versus a voltage (V).

FIG. 5 is a diagram showing a graph of leakage current density versus voltage of an amorphous Y ₂ O ₃ film.

FIG. 6 shows a single crystal Gd ₂ grown on a vicinal silicon substrate.
FIG. 4 shows the specific capacitance as a function of voltage for O ₃ .

FIG. 7 shows the specific capacitance as a function of voltage for amorphous Y ₂ O ₃ grown on a normal silicon substrate.

[Explanation of symbols]

 Reference Signs List 10 Slightly inclined Si (100) substrate 12 Miscut surface 14 surface stairs

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Ahmed Reffic Coatan United States 07059 New Jersey, Warren, Chiristic Drive 56 (72) Inventor Juenay Rainier Quo United States 07060 New Jersey, Watching, Nottingham Drive 40 ( 72) Inventor Joseph Petras Manaz United States 07901 New Jersey, Summit, Bryant Parkway 29

Claims (29)

[Claims] 1. A predetermined angular miscut (angul) that forms a main upper surface exhibiting a step-like pattern along the [110] direction.
vicinal silicon (100) substrate showing ar miscut) and 1
Dielectric constant ε ≧ 4 deposited on a stepped main surface of the vicinal silicon substrate at a predetermined thickness t under an oxygen partial pressure of 0 ⁻⁷ torr or less without forming an SiO ₂ film therebetween.
And a Mn ₂ O _{3 type} rare earth oxide. 2. The semiconductor device according to claim 1, wherein said rare earth oxide contains Gd ₂ O ₃ . 3. The method according to claim 1, wherein the Gd ₂ O ₃ is an epitaxial Gd _2.
3. The semiconductor device according to claim 2, comprising O _3. 4. The rare earth oxide has a 2-domain (1
00) The semiconductor device according to claim 2 consisting of Gd ₂ O ₃ structure. 5. The rare earth oxide has a single domain (1
00) The semiconductor device according to claim 2 consisting of Gd ₂ O ₃ structure. 6. The semiconductor device according to claim 1, wherein said rare earth oxide is made of Y ₂ O ₃ . 7. The semiconductor device according to claim 6, wherein said Y ₂ O ₃ is made of epitaxial Y ₂ O ₃ . 8. The rare earth oxide has a 2-domain (1
00) The semiconductor device according to claim 6 consisting of Y ₂ O ₃ structure. 9. The rare earth oxide has a single domain (1
00) The semiconductor device according to claim 6 consisting of Y ₂ O ₃ structure. 10. The rare earth oxide according to claim 1, wherein said rare earth oxide is 10 to 50.
The semiconductor device according to claim 1, wherein the semiconductor device is formed to include a thickness in a range of 0 °. 11. The semiconductor device according to claim 1, wherein said vicinal silicon substrate includes a predetermined angle miscut in a range of 4 ° to 6 °. 12. The semiconductor device according to claim 11, wherein the predetermined angle miscut is about 4 °, and a terrace space of about 80 ° is formed on the main surface of the silicon substrate. 13. A silicon substrate defined to include an upper main surface, and on a main surface of the silicon substrate under an oxygen partial pressure of 10 ⁻⁷ torr or less without forming a SiO ₂ film therebetween. Dielectric constant ε deposited to a given thickness t
A semiconductor device comprising an amorphous oxide of a Mn ₂ O _{3 type} rare earth oxide showing ≧ 4. 14. An amorphous rare earth oxide comprising Gd ₂ O ₃
14. The semiconductor device according to claim 13, comprising: 15. The method according to claim 15, wherein the amorphous rare earth oxide is Y.
The semiconductor device according to claim 13 consisting of ₂ O _3. 16. A method for manufacturing a semiconductor device including a high dielectric oxide layer, comprising the following steps: a) vicinal silicon (10) exhibiting a predetermined angular miscut;
0) applying a substrate on its main surface to form a step-like pattern on said main surface; b) cleaning said silicon main surface to remove impurities and oxides; D) supplying a ceramic rare earth oxidation source, e) reducing the oxygen partial pressure in said ultra-high vacuum system to a level less than or equal to 10 ^-7 torr. F) electron beam evaporation of a predetermined thickness of the ceramic rare earth oxide on the major surface of the step pattern of the vicinal silicon substrate. 17. The method according to claim 16, wherein in performing step a), the vicinal silicon (100) is miscut to a predetermined angle in the range of 4 ° to 6 °. 18. In performing step a), the vicinal silicon (100) is miscut to a predetermined angle in the range of 4 ° to 6 ° to form a stepped pattern having a step height of about 80 °. 18. The method of claim 17, wherein the method comprises: 19. The method of claim 16, wherein in performing step b), the silicon substrate is cleaned by hydrogen passivation with a buffered HF solution. 20. The method according to claim 16, wherein in performing step d), ceramic Gd ₂ O ₃ is provided. 21. The method according to claim 16, wherein in performing step d), ceramic Y ₂ O ₃ is provided. 22. The method of claim 16, wherein performing step f) forms a rare earth oxide layer having a thickness in the range of 10 ° to 500 °. 23. The method of claim 16, further comprising the step of: g) gas annealing the rare earth oxide dielectric layer at a temperature and for a time sufficient to reduce the leakage current density to a predetermined value. The described method. 24. The method according to claim 23, wherein in performing step g), the apparatus is heated at a temperature of about 400 ° C. for about 1 hour. 25. In the performance of step g), the gas anneal is a predetermined mixture of H ₂ and N _2.
The method described in. 26. In the performance of step g), a temperature of about 10
24. The method of claim 23, wherein the rapid thermal anneal is performed at 00C for about 1 hour. 27. A method of manufacturing a semiconductor device including a high dielectric oxide layer, comprising the steps of: a) silicon (10) defined to include an upper main surface;
0) providing a substrate; b) cleaning the silicon upper major surface to remove impurities and oxides; c) inserting the substrate into an ultra-high vacuum system containing an oxygen ambient atmosphere; d) ceramic rare earth oxidation. E) reducing the oxygen partial pressure in said ultra-high vacuum system to a level less than or equal to 10 ^-7 torr; f) evaporating said ceramic rare earth oxide of predetermined thickness by electron beam Forming an amorphous rare earth oxide layer on the silicon upper major surface. 28. The method according to claim 27, wherein in performing step d), ceramic Gd ₂ O ₃ is provided. 29. The method according to claim 27, wherein in performing step d), ceramic Y ₂ O ₃ is provided.