JP2001244381A - Semiconductor chip mounting substrate, semiconductor device, and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip mounting substrate excellent in electric characteristics and heat radiation characteristics and a semiconductor device packaged on this substrate at low cost. A substrate for mounting a semiconductor chip includes a first wiring layer, a first insulating layer located below the first wiring layer and made of a resin layer having no continuous inorganic reinforcing material, and a first insulating layer. A second wiring layer positioned below the second wiring layer, a second insulating layer formed of a resin layer having a continuous inorganic reinforcing material positioned below the second wiring layer, and a heat dissipating metal positioned below the second insulating layer With a plate. The substrate having such a laminated structure has a cavity for mounting a semiconductor chip having an opening on the first wiring layer side.
The thickness of the second insulating layer, or the sum of the thickness of the second insulating layer and the thickness of any insulating layer thereunder occupies 30% or more and 98% or less of the depth of the cavity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a substrate for mounting a semiconductor chip, a semiconductor device, and a method for manufacturing the same.

[0002]

2. Description of the Related Art As the number of pins and the pitch of semiconductor chips increase, the BGA (ball grid array: ball g
Rid array type packages are becoming mainstream. Conventional Q that takes out leads from four sides of package
This is because the FP (quad flat plate) type package has a limitation in reducing the pitch of the external leads, and cannot accommodate the mounting of a multi-pin chip. The BGA type package uses a printed circuit board instead of the lead frame of the QFP type package. A semiconductor chip having a fine-pitch multi-pin structure is fixed to the substrate, and the chip and the substrate are internally connected. On the substrate, solder balls serving as electrodes are arranged in a grid at a pitch of 1.27 mm or less.

Since a BGA package uses a printed circuit board instead of a lead frame, it is necessary to lower the bonding temperature and at the same time prevent the package from warping. Therefore, a heat dissipating metal plate is attached to the substrate as a heat spreader. In a cavity BGA substrate of a type in which heat radiation is enhanced by a metal plate for heat radiation, a ceramic substrate has been used so far. However, recently, resin-based substrates that enhance the reliability of solder connection, have excellent electrical characteristics, and have high productivity have been frequently used.

[0004] There are two types of resin-based substrates.
A type in which a double-sided wiring board or multilayer wiring board with a cavity window hole formed in advance is attached to a metal plate for heat dissipation,
This is a type in which a heat-resistant insulating resin such as an epoxy resin or a polyimide resin is directly laminated on a metal plate for heat dissipation in the form of a varnish or a film to form a wiring.

[0005] In addition to these, there is a type of a heat radiation board of a bonding type in which a single-sided wiring film or a glass cloth epoxy resin substrate is bonded to a metal plate for heat radiation.
In order to cope with high-speed SI and high heat generation, a resin substrate having a multilayer structure is generally used recently. Specifically, there is a tendency to provide a ground layer for controlling characteristic impedance, in addition to the signal wiring layer, and the number of layers is increased. A BGA whose thermal resistance and frequency characteristics are improved by the ground wiring layer is called an advanced BGA, and several types have been developed.

For example, Amkor Technology (Amkor Technology)
Technology) has developed a cavity BGA in which a substrate in which a window hole for mounting a chip is formed on a metal plate on which a double-sided wiring board is previously adhered is bonded on a metal plate for heat radiation. Prolinx labs has also developed a type of board in which wiring is built up using build-up technology on a metal plate with window holes.
Technology (Substrate Technologies) is a type of board in which instead of bonding a metal plate with a window hole, a heat dissipation metal plate is dug deep, and a wiring layer is built up on the heat dissipation metal plate as a ground layer. Has been proposed.
One of the features of each of these substrates is that a metal plate contributing to heat dissipation is used as a ground layer and electrically connected to a wiring layer.

[0007]

When a substrate of the above-mentioned type is used for a BGA type package, a semiconductor chip is bonded in a cavity, wire bonding is performed from the chip surface to terminals on the substrate surface, and then an LSI and a wire are bonded. And the wire bonding region is sealed with a liquid sealing material. For this reason, the depth of the cavity needs to be equal to or greater than the thickness of the LSI. Therefore, as described above, a substrate of a type in which a window hole is formed in a wiring board, a metal plate, or a metal plate for heat radiation requires deep digging, but has the following problems.

First, in a substrate of a type in which a wiring board provided with a window hole is pasted on a metal plate for heat radiation, a glass cloth resin base material using glass fiber as an inorganic reinforcing material is used for a wiring layer. The relative dielectric constant becomes higher than that of the resin alone, and the wiring layer itself becomes thicker. For this reason, when the signal wiring width of the first layer becomes a fine line of less than 100 microns due to the high density, the characteristic impedance is generally required.
It deviates greatly from 0 ohms and becomes 100 ohms or more, which causes a problem in high-speed signal processing capability. Also,
The process of accurately bonding a wiring board prepared in advance on a surface-treated metal plate for heat dissipation is costly, and as a result, the substrate is expensive.

On the other hand, in the case of a substrate of a type in which a window hole is formed in a metal plate, an upper signal layer (first layer) is formed by building up an insulating resin layer on the metal plate without using a glass cloth for the insulating layer.
The relative dielectric constant and the thickness of the insulating layer inserted between the insulating layer and the lower ground layer (second layer) can be reduced, and the characteristic impedance can be designed to be around 50 ohm, which is a general target value. However, a method of forming a window hole in the second metal plate instead of the resin substrate and stacking the wiring layers by the build-up technique uses a lot of more expensive metal materials and handles a heavy metal plate. This is disadvantageous in terms of cost, such as requiring a plurality of laminating steps. Furthermore, when the solder ball is mounted, the distance between the ball pad portion and the metal plate is short, and the conductor is also continuous as a heat conductor. Therefore, it is difficult to raise only the temperature of the ball pad portion. Cannot be easily melt-bonded.

A substrate of a type in which the number of build-up layers is reduced and the build-up wiring layer is electrically connected to the metal plate for heat radiation with the metal plate for heat radiation used as a ground is costly for metal processing in which the metal plate for heat radiation is dug deep. Take it. Furthermore, the interface where the sealing material in the cavity comes into contact is a metal surface cut out by metal working, the adhesion to the sealing material is lower than that of an organic material, and the moisture absorption heat resistance after LSI packaging is reduced. .

If an attempt is made to treat the metal cut surface with an oxidation-reduction solution or an etching solution that can be uniformly and inexpensively roughened, a part of the already formed gold-plated terminals and the heat-dissipating metal plate are electrically connected. Therefore, a battery reaction occurs in the solution, and the gold-plated terminal is contaminated.

Accordingly, a first object of the present invention is to provide an inexpensive substrate for mounting a semiconductor chip, which is excellent in electric characteristics and heat dissipation.

A second object of the present invention is to provide a semiconductor device which is packaged by mounting a semiconductor chip and which can perform high-speed processing.

It is a third object of the present invention to provide a method of manufacturing a semiconductor chip mounting substrate which is excellent in electric characteristics and heat dissipation and can easily form a laminate and a cavity.

[0015]

In order to achieve the first object, a semiconductor chip mounting substrate, which is a first feature of the present invention, is provided with a first wiring layer and a first wiring layer located below the first wiring layer. And
A first insulating layer made of a continuous resin layer having no inorganic reinforcing material, a second wiring layer located below the first insulating layer,
It has a second insulating layer made of a resin layer having a continuous inorganic reinforcing material located below the wiring layer, and a metal plate for heat radiation located below the second insulating layer. The substrate having such a laminated structure has a cavity for mounting a semiconductor chip having an opening on the first wiring layer side.

By forming the first insulating layer as a continuous resin layer having no inorganic reinforcing material, the relative dielectric constant can be reduced and the characteristic impedance of the signal line can be maintained well. Such a resin is, for example, an epoxy resin, a polyimide resin, or the like.

The resin layer having an inorganic reinforcing material as the second insulating layer is a glass cloth epoxy resin, a glass cloth polyimide resin, a glass nonwoven cloth epoxy resin, a glass nonwoven cloth polyimide resin, or the like. Such a resin is inexpensive, light, and hard to break, so that it is easy to handle. Therefore, in order to facilitate the formation of the cavity, the total thickness of the insulating layer located between the second insulating layer and the heat-dissipating metal plate below the second insulating layer is set to 30% or more of the depth of the cavity by 98% or less. %. In addition, when the resin of the second insulating layer is made of an epoxy resin material, excellent adhesion to an epoxy resin liquid sealing material generally used for chip sealing is obtained.

The heat-dissipating metal plate is, for example, a copper plate or a copper alloy plate which is excellent in heat conductivity and can be obtained relatively inexpensively. Further, iron, aluminum, and other alloys may be used. The thickness of such a metal plate for heat dissipation is preferably 0.15 mm or more so as to withstand cavity processing and die bonding of a semiconductor chip. Also,
The thickness is preferably 1.00 mm or less so that the substrate does not become too thick.

The substrate for mounting a semiconductor chip has a via hole penetrating the first insulating layer and connecting the first wiring layer and the second wiring layer. As described above, since the first insulating layer is a resin layer having no inorganic reinforcing material, laser hole processing is easy, and a highly accurate via hole can be provided.

In order to achieve the second object, a packaged semiconductor device which is a second feature of the present invention comprises a plurality of externally connected solder balls arranged in an array, and A first wiring layer closest to the mounting surface, a first insulating layer formed of a resin layer that is located below the first wiring layer and does not include a continuous inorganic reinforcing material, and a second insulating layer that is located below the first insulating layer. A wiring layer, a second insulating layer formed of a resin layer including a continuous inorganic reinforcing material positioned below the second wiring layer, a heat-dissipating metal plate positioned below the second insulating layer, and mounting of solder balls A cavity having an opening on a surface side, a semiconductor chip mounted in the cavity, and a sealing material for sealing the mounted semiconductor chip are provided.

The solder balls for connection may be, for example, solder bumps or metal bumps. Since the semiconductor device packaged in this way can maintain high electrical characteristics and heat dissipation of the wiring, the reliability of high-speed processing of the mounted highly integrated semiconductor chip can be improved.

In order to achieve the third object, a method of manufacturing a substrate for mounting a semiconductor chip, which is a third feature of the present invention, first comprises two or more conductor layers and a position between each conductor layer. Two or more insulating layers, an adhesive layer, and a heat-dissipating metal plate are laminated in this order by collective pressing. Next, a via hole connecting between two or more conductor layers is formed by laser processing. Thereafter, a cavity for accommodating the semiconductor chip is formed by machining from the conductor layer side.

The cavity may be formed to a depth reaching the adhesive layer, or may be formed to a depth reaching the metal plate for heat radiation. If the depth of the cavity is up to the adhesive layer, the sealing material is easy to adhere, but the heat dissipation of the substrate is slightly inferior. When the depth of the cavity is up to the metal plate for heat dissipation, heat dissipation is improved, but adhesion to the sealing material is slightly inferior. Therefore, in the latter case, after the cavity is formed and the substrate is cut out as a single product for a package, the metal surface at the bottom of the cavity is roughened. The roughening is performed by, for example, a blackening process or a non-uniform microetching process.

As described above, including the bonding of the heat dissipating metal plate,
By laminating a plurality of conductive layers and insulating layers by a single press, the substrate manufacturing process is simplified. In addition, of the two or more conductive layers and the insulating layer, the first conductive layer and the first insulating layer are integrated to form, for example, an adhesive film with a copper foil containing no inorganic reinforcing material. Further, the second conductive layer and the second insulating layer are integrated into, for example, a glass cloth epoxy resin copper clad board. This makes the batch lamination press easier. In this case, since the adhesive film with a copper foil does not include an inorganic reinforcing material, laser processing for forming a via hole can be easily and accurately performed. Further, the glass cloth epoxy resin copper-clad laminate is light and hard to break, and is easy to handle, so that machining for forming a cavity is simplified.

Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

[0026]

FIG. 1 shows a semiconductor chip mounting substrate 10 according to a first embodiment of the present invention, and FIG. 2 shows a package 100 using the semiconductor chip mounting substrate 10 of FIG.

The semiconductor chip mounting board 10 shown in FIG.
A wiring layer 1, a first insulating layer 2 located below the first wiring layer 1, a second wiring layer 3 located below the first insulating layer 1,
It has a second insulating layer 4 located below the second wiring layer, a metal plate 7 for heat radiation located below the second insulating layer, and a cavity 9 for mounting a semiconductor chip. In addition, a via hole 11 connecting the first wiring layer 1 and the second wiring layer 5 is provided. The first and second wiring layers are, for example, copper (Cu) or another metal having high conductivity.

As a feature of the semiconductor chip mounting substrate 10, the first insulating layer 2 is a resin layer containing no continuous inorganic reinforcing material such as a glass cloth, and the second insulating layer 4 is a continuous resin layer such as a glass cloth. It is a resin layer containing an inorganic reinforcing material.

The reason why the first insulating layer 2 is a resin layer containing no inorganic reinforcing material is that the relative dielectric constant is reduced and the wiring width of the first wiring layer 1 and the second wiring layer 3 is reduced. This is to prevent the characteristic impedance from increasing and to facilitate the formation of the via hole 11 connecting the first wiring layer 1 and the second wiring layer 3. The first insulating layer 2 includes, for example, an epoxy resin adhesive film, a polyimide resin adhesive film,
An epoxy resin adhesive film with a copper foil, a polyimide resin adhesive film with a copper foil, or a material obtained by adding a filler thereto is used. In the first embodiment, the thickness of the first wiring layer is about 30 μm, and the thickness of the first insulating layer 2 is about 70 μm.

On the other hand, the second insulating layer 4 is a resin layer provided with a continuous inorganic material such as a glass cloth or a glass non-woven fabric. In the first embodiment, a glass cloth epoxy resin copper-clad laminate, a glass cloth polyimide resin copper-clad laminate, a glass non-woven epoxy resin copper-clad laminate, a glass non-woven polyimide which can serve as the second wiring layer 3 and the second insulating layer 4 can be used. Use a resin copper-clad laminate or the like. When an epoxy resin-based insulating layer is used, there is an effect that the adhesiveness to an epoxy resin-based liquid sealing material generally used for sealing a semiconductor chip is excellent.

Such a copper-clad laminate has a certain thickness so that the depth of the cavity 9 can be adjusted. In the first embodiment, the total thickness of the second insulating layer 4 and the adhesive layer 5 is 400 μm, and occupies about 69% of the cavity depth. At this time, the total thickness of the second insulating layer 4 and the adhesive layer 5 is preferably 30% or more and 98% or less of the depth of the cavity 9 so that the cavity is formed stably. Further, the copper-clad laminate is less expensive than the copper plate, and is light and hard to break, so that it is excellent in handleability. In addition, before lamination with the first insulating layer, a wiring pattern can be formed on the copper-clad portion in advance.

The heat dissipating metal plate 7 has a function as a heat spreader, and is attached to the second insulating layer 4 via the adhesive layer 5. The adhesive layer 5 is a prepreg (plastic resin containing a reinforcing material), and is preferably made of a material equivalent to that of the second insulating layer 4. The heat dissipating metal plate 7 is a relatively inexpensive copper plate or copper alloy plate. However, iron (F
e), aluminum (Al), or an alloy thereof may be used. The thickness of the heat-dissipating metal plate 7 needs to be 0.15 mm or more so that it can withstand cavity processing and die bonding of a semiconductor chip and can be used as a package after sealing. On the other hand, the thickness is preferably 1.00 mm or less so as not to increase the size of the package. In the first embodiment, the heat-dissipating metal plate 7 is made of oxygen-free copper having a thickness of 0.4 mm.

The semiconductor chip mounting substrate 10 has a cavity 9 for mounting a semiconductor chip. The depth of the cavity 9 is slightly deeper than the thickness of the semiconductor chip to be mounted. 30% of the side wall of such a cavity 9
The above is occupied by the resin layers constituting the first insulating layer 2 and the second insulating layer 4. In the first embodiment, the cavity 9 has a depth reaching the metal plate 7 for heat radiation. In this case, the bottom surface of the cavity becomes a metal surface (copper surface). Therefore, in order to improve the adhesiveness with the sealing material when sealing after mounting the semiconductor chip, a roughening treatment layer 17 is formed on the bottom surface of the cavity.
Is provided. In addition, the depth of the cavity 9 may be up to a point reaching the resin layer on the metal plate for heat radiation.
In this case, since the adhesion between the cavity bottom surface and the sealing material is good, it is not necessary to have the roughening layer 17 on the bottom surface.

The first wiring layer 1 and the second wiring layer 3 are connected by a via hole 11. In the first embodiment,
The via holes 11 are plated with copper. The semiconductor chip mounting substrate 10 further includes a gold (Au) plating layer 1 serving as a wire bonding pad on the first wiring layer 1.
3a, and a gold (Au) plating layer 13b to be a ball pad for attaching a solder ball. A region other than the pad portion is covered with the solder resist 15.

The surface of the heat-dissipating metal plate of the substrate 10 has gold (A) in a region corresponding to the cavity 9 in which the semiconductor chip is mounted.
u) A plating layer 13c is provided, and other areas are covered with a solder resist. Only necessary parts are gold (Au)
Because of the plating, the substrate cost can be reduced.

FIG. 2 is a top view of a package 100 in which a semiconductor chip is mounted on the semiconductor chip mounting substrate 10 shown in FIG. 1, and FIG. 3 is a cross-sectional view of the package 100 along the line AA in FIG. is there. The package 100 includes a plurality of solder balls 19 arranged in an array, a first wiring layer 1 closest to the mounting surface of the solder balls, and a resin layer located below the first wiring layer and containing a continuous inorganic reinforcing material. A second insulating layer 4 made of a resin layer containing a continuous inorganic reinforcing material, and a second wiring layer 3 located thereunder; A heat-dissipating metal plate 7 located below the layer 4, a cavity 9 having an opening on the solder ball mounting surface side, a semiconductor chip 23 mounted in the cavity, and a sealing material 25 for sealing the semiconductor chip. Is provided.

That is, the package 100 has a heat-dissipating metal plate of a thickness having a certain degree of resistance as a heat spreader on the entire surface, a resin having no continuous inorganic reinforcing material as an insulating layer between wiring layers, and For the insulating layer below the two wiring layers, a copper-clad laminate having a continuous inorganic reinforcing material is used. Thus, the package 100 is realized as an inexpensive package having excellent electric characteristics and heat dissipation, and having stable strength.

FIGS. 4 and 5 are views showing a method of manufacturing the semiconductor chip mounting substrate described in the first embodiment as a second embodiment of the present invention. Each manufacturing process is as follows.

(A) First, as shown in FIG.
The above-mentioned conductor layers (two conductor layers in the second embodiment), two or more insulating layers located between the conductor layers, an adhesive layer, and a metal plate for heat dissipation are laminated in this order by collective pressing. I do.
In the second embodiment, the first conductor layer 41 and the first insulating layer 42 are integrated with the copper foil-attached adhesive film 43 and the second conductor layer 4.
A copper-clad laminate 46 in which the fourth and second insulating layers 45 are integrated;
Prepreg 47 as adhesive layer and metal plate 4 for heat radiation
8 are laminated by a batch press. Adhesive film with copper foil 4
3 has MCF-6000E manufactured by Hitachi Chemical Co., Ltd.
For the copper-clad laminate 46, a glass cloth epoxy resin copper-clad laminate MCL-E-679 manufactured by Hitachi Chemical Co., Ltd. was used. The prepreg 47 is made of GEA-679N manufactured by Hitachi Chemical Co., Ltd.
An oxygen-free copper plate having a thickness of mm was used. The selection criteria for these materials are that the pressing temperature and the pressing pressure are almost the same, and that the glass transition temperature is 160 ° C. or higher, which is suitable for wire bonding. In the second embodiment, the pressing temperature is 170 ° C. and the pressing pressure is 2.5 × 10 ⁶
N / m ² . Further, it is preferable that a necessary wiring pattern is formed in advance on the copper-clad layer as the second conductor layer 44 by photolithography or the like before pressing to form a plurality of power sources and grounds.

(B) Next, as shown in FIG. 4B, a via hole 49 connecting the first conductor layer 41 and the second conductor layer 44 is formed by laser processing. Specifically, MC
In the copper foil portion of F-6000E, a portion to be a via hole 49 is selectively etched to open a window. The first insulating layer 42 is drilled while controlling the laser output using the copper foil with the window as a conformal mask.
The laser output is applied to the second conductor layer 44 (ie, the copper clad laminate 4).
(Copper-clad portion 6) to control the laser hole to stop.

(C) Next, as shown in FIG. 4C, copper 50 is buried in the via hole 49 by electroless copper plating. The reason why the electroless copper plating is adopted is to improve the plating coverage. After filling the via hole, the first
An outer layer circuit pattern is formed on the copper foil 41 as a conductive layer by photolithography and etching. further,
Except for the pad area for wire bonding and solder ball mounting on the wiring, the solder resist layer 5
3 is formed by photolithography. Similarly, on the back surface of the heat-dissipating metal plate 48, except for the region corresponding to the cavity for mounting the semiconductor chip, the solder resist layer 53 is formed.
To form Thereafter, the pad regions 51a and 51b and the cavity corresponding region 5 are formed by electroless gold (Au) plating.
1c is formed. In this way, only the necessary parts (A
By applying u) plating, the consumption of the gold (Au) plating solution is suppressed, and the cost is suppressed. The reason for adopting the electroless gold (Au) plating is that, in the case of the electrolytic gold (Au) plating, a plating power supply line for connecting to an external power supply must be removed by etching after the gold (Au) plating process. At this time, in a high-speed signal compatible substrate as the object of the present invention, even if a small amount of power supply line remains, an adverse effect on signal transfer occurs. Therefore, electroless gold (A
A gold (Au) plating layer was formed by u) plating.

(D) Finally, as shown in FIG. 5, the cavity 57 is counterbored with a router machine. FIG. 5 (a)
5B shows an example in which the counterbore is stopped by the resin adhesive layer (prepreg) 47, and FIG. 5B shows an example in which the counterbore is stopped in the metal plate 48 for heat radiation. In the case of FIG. 5B, a blackening layer 59 is formed to roughen the bottom surface of the cavity in order to increase the adhesion between the sealing material and the die bonding material.

In order to mount the semiconductor chip on the substrate formed in this manner and obtain the package shown in FIGS. 2 and 3, the semiconductor chip 23 is fixed to the bottom of the cavity with the die bonding material 21. As the die bond material 21, for example, a polymer pond EN-4 manufactured by Hitachi Chemical Co., Ltd. is used.
900 is used. Further, although not shown, bonding pads on the chip surface and gold (Au) on the package substrate
The bonding pad of the plating area 51a is wire-bonded with a gold or aluminum wire. Thereafter, sealing is performed by potting using a liquid sealing material.
The liquid sealing material is, for example, CEL manufactured by Hitachi Chemical Co., Ltd.
-C-X7230 is used. Finally, ball pad 51
2b, the solder balls are melt-bonded to complete the package shown in FIGS.

The characteristic impedance of the semiconductor chip mounting substrate 10 manufactured as described above is 60Ω at 1 MHz, and a value which does not deviate much from 50Ω which is a general requirement standard can be achieved. The thermal resistance between the bottom surface of the cavity and the back surface of the heat-dissipating metal plate is 1.51 ° C./W when the counterbore is stopped in the adhesive layer (prepreg), and when the counterbore is stopped in the heat-dissipating metal plate. 0.25 ° C./W, and a considerable reduction in thermal resistance could be achieved. Furthermore, the reliability of the package after mounting and sealing the semiconductor chip is
JEDEC precondition level 3, 30 ℃,
192 hours treatment at 60% humidity, then 245 ° C
When reflow was performed, there was no abnormality.

As a result, low cost and electric characteristics
It has become possible to manufacture a BGA substrate and a package having excellent heat radiation characteristics.

In the first and second embodiments, the two-layer wiring of the first wiring layer and the second wiring layer has been described as an example, but a third wiring layer may be further provided. in this case,
The insulating layer between the second wiring layer and the third wiring layer is also a resin layer having no continuous inorganic reinforcing material. In the case where 1-3 layers connection is required by a via hole in such a multilayer structure, the second
A clearance hole is formed in the wiring layer in advance, and a via hole is formed by laser processing.

In the second embodiment, an adhesive film with a copper foil having a glass transition temperature of 160 ° C. or more is used for the first wiring layer. However, the first wiring layer has strength enough to withstand handling such as pattern formation before a batch lamination press. Other resin films may be used as long as the glass transition temperature after the thermosetting in the laminating press step is 130 ° C. or more and the wire bonding property of the combined heat / ultrasonic type using a gold wire is good. . Also,
Although the solder balls are connected to the ball pad 51b by reflow, a hemispherical laser hole reaching the second wiring layer from the ball pad 51b may be formed, and the second wiring layer may be used as a ball pad. Further, instead of potting using a liquid sealing material, sealing by transfer molding using a mold resin may be performed.

When the semiconductor chip mounting substrate is
It is also possible to use a multi-layer plate having more than a layer plate. Also in this case, bonding is performed between the metal plate for heat radiation and the laminated plate via a prepreg.

[0049]

As described above, according to the present invention,
Provided are a BGA type semiconductor chip mounting substrate and a packaged semiconductor device which are excellent in both electric characteristics and heat radiation characteristics.

Further, a method for manufacturing a semiconductor chip mounting substrate having excellent electric characteristics and heat radiation characteristics can be realized with reduced costs and simple steps.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip mounting board according to a first embodiment of the present invention.

2 is a BG using the semiconductor chip mounting substrate of FIG. 1;
It is a top view of A type package.

FIG. 3 is a cross-sectional view of the BGA package of FIG. 2 taken along line AA.

FIG. 4 is a view illustrating a method for manufacturing a semiconductor chip mounting substrate according to a second embodiment of the present invention.

FIG. 5 is a view showing a step that follows the step of FIG. 4;

DESCRIPTION OF SYMBOLS 1, 41 First wiring layer 2, 42 First insulating layer 3, 44 Second wiring layer 4, 45 Second insulating layer 5, 47 Adhesive layer (prepreg) 7, 48 Heat-dissipating metal plate 9, 57 Cavity 11, 49 Via hole 19 Solder ball 13a, 13b, 13c, 51a, 51b, 51c Gold (Au) plating layer 15, 53 Solder resist 21 Die bond material 23 Semiconductor chip 25 Sealant 27 Wire bonding

Claims (8)

[Claims] A first wiring layer; a first insulating layer, which is located below the first wiring layer and is made of a resin layer that does not include a continuous inorganic reinforcing material; and is located below the first insulating layer. A second wiring layer, a second insulating layer located below the second wiring layer and made of a resin layer containing a continuous inorganic reinforcing material, and a heat dissipation metal plate located below the second insulating layer; A semiconductor chip mounting substrate having a semiconductor chip mounting cavity having an opening on the first wiring layer side. 2. The total thickness of the insulating layer located between the second insulating layer and the metal plate for heat dissipation below the second insulating layer occupies 30% or more and 98% or less of the depth of the cavity. The substrate for mounting a semiconductor chip according to claim 1, wherein: 3. The heat-dissipating metal plate has a thickness of 0.15 mm.
The substrate for mounting a semiconductor chip according to claim 1 or 2, wherein the diameter is not more than 1.00 mm. 4. The semiconductor device according to claim 1, further comprising a via hole penetrating the first insulating layer and connecting the first wiring layer and the second wiring layer. Substrate for mounting semiconductor chips. 5. A plurality of solder balls for external connection arranged in an array, a first wiring layer closest to the mounting surface of the solder balls, and a continuous inorganic reinforcement located below the first wiring layer. A first insulating layer made of a resin layer containing a material, a second wiring layer located below the first insulating layer, and a resin layer located below the second wiring layer and containing a continuous inorganic reinforcing material. A second insulating layer, a heat-dissipating metal plate located below the second insulating layer, a cavity having an opening on the solder ball mounting surface side, a semiconductor chip mounted in the cavity, and the semiconductor chip. And a sealing material for sealing the semiconductor device. 6. A step of laminating two or more conductor layers, two or more insulating layers located between the conductor layers, an adhesive layer, and a heat-dissipating metal plate by collective pressing in this order; Forming a via hole connecting between the two or more conductor layers by laser processing, and forming a cavity for accommodating a semiconductor chip from the conductor layer side by machining. Substrate manufacturing method. 7. The method according to claim 6, wherein the cavity forming step forms the cavity to a depth reaching the adhesive layer. 8. The step of forming a cavity, the step of forming a cavity to a depth reaching the metal plate for heat dissipation, a step of cutting the substrate into a single product for a package after the formation of the cavity, and a step of roughening the metal surface at the bottom of the cavity after cutting the single product. 7. The method for manufacturing a semiconductor chip mounting substrate according to claim 6, further comprising the step of: