JP2002164663A - Build-up core board, build-up wiring board, and method of manufacturing the same - Google Patents

Abstract

(57) [Summary] (Modified) [PROBLEMS] To provide a novel manufacturing method capable of uniformly controlling the thickness of a heat / electrically conductive post and an insulating layer without using mechanical polishing, and as a result, to increase the speed. Provide an optimal build-up wiring board. SOLUTION: The present invention relates to a method of manufacturing a build-up core substrate having the following steps as main steps, and a build-up core substrate and a build-up wiring board made possible by the method. (1) A post forming layer is bonded to one main surface of the barrier layer, and a carrier layer is bonded to the other main surface. (2) By etching until the barrier layer is reached, a plurality of thermally and electrically conductive posts 16 are formed at a predetermined pitch to form a patterned etched product, and prepregs 12 are laminated, and heated and pressed to form a first laminated product. make. (3) removing the carrier layer from the first laminate. (4) The barrier layer is further removed to obtain a second laminated product, prepregs are laminated, and heated and pressed to produce a build-up core substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a core board of a build-up wiring board and a build-up wiring board to which a built-up layer is added and an electronic component is mounted on a surface to transmit a signal. Very little variation in the shape and dimensions that enable semiconductor packages,
Also, it relates to one having excellent heat dissipation.

[0002]

2. Description of the Related Art A semiconductor package is three-dimensionally mounted on a multi-layer substrate for high-density mounting, and electrical connections between layers are made through holes. Semiconductor devices are also sensitive to heat. Therefore, the development of semiconductor element substrates that can effectively dissipate the heat generated by the semiconductor element and that can be manufactured at a low cost with a simple structure has been actively performed. Conventionally, a plurality of through holes have been drilled at a pitch of about 1.27 mm using a drill of about 0.3 mm, and then plated with Cu or the like to conduct conduction in the vertical direction of the substrate.

For example, Japanese Patent Application Laid-Open No. 10-313071 discloses that a heat radiation pattern is formed on the other main surface of a substrate, and a heat radiation plate serving as a bonding surface when mounted on a wiring board is bonded onto the heat radiation pattern. Further, a through hole for heat radiation is formed so as to penetrate in the thickness direction of the substrate, and a metal material is filled in the through hole for heat radiation, and the heat generated by the bare chip is filled with the metal material. Also disclosed is one that is conducted to a heat sink through a heat dissipation pattern. Further, Japanese Patent Application Laid-Open No. 9-199632 discloses an electronic component mounting substrate which is excellent in heat dissipation, facilitates drilling, and enables high-density wiring in a flexible substrate.

According to JP-A-9-199632,
"A multilayer board comprising an electrically insulating flexible film and two or more conductive circuits provided in the thickness direction of the flexible film, a through hole penetrating all the flexible films, and an upper side of the multilayer board covering the through hole. And a mounting recess formed by the through-hole and the heat-dissipating metal plate for mounting an electronic component, and a through-hole provided on the multilayer substrate and conducting to a conductor circuit. The thickness of the film is 30 to 200
μm is preferred. "

[0005] According to the embodiment of JP-A-9-199632, the manufacturing method is as follows. A flexible film made of a glass fiber-containing epoxy material is prepared. The flexible film is a flexible belt-shaped film having a thickness of 0.05 mm and a width of 2.5 to 15 cm. This flexible film is wound in a roll shape in advance to form a plurality of roll bodies. Next, while pulling out the flexible film from the roll, an insulating adhesive made of a thermoplastic glass fiber-containing epoxy material is adhered to the lower surface of the flexible film. Next, a through hole is formed in a substantially central portion of the flexible film by punching. Next, a copper foil having a thickness of 35 mm is bonded to the lower surface side of the flexible film via the insulating adhesive. Then, the inside of the through hole is filled with solder.

In recent years, with the miniaturization of equipment, the pattern of semiconductor package substrates has been getting finer and finer, and is called a so-called build-up wiring board. An insulating layer is applied to both sides of a core substrate and a build-up layer is added. Then, a method of forming a pattern by a plating method is performed. FIG. 10 shows an example of a conventional build-up wiring board. The build-up wiring board 3 includes the build-up core board 1 and upper and lower build-up layers. The build-up core substrate 1 often uses a glass fiber reinforced epoxy-rigid material. The upper buildup layer 2a is C4 connected to the semiconductor (Si) chip 4 via the wiring pattern 7 and the solder balls 5a. C4 connection means controlled coll
Abbreviation for apsible chip connector, a connection method that forms an electrically and thermally effective conductive path that flows an electric signal of an LSI chip and generated heat to a substrate via a pad.

The symbol 4 may be a semiconductor device such as an LSI or a CSP. The underfill 6 has a function of sealing with a resin or the like to improve moisture resistance and impact resistance. The lower buildup layer 2b is connected to an external circuit via the solder ball 5b. In the core substrate 1, Cu plating is performed on the inner wall of the through hole 8 to fill the hole, and the inner wall of the through hole 8 is filled with resin and flattened. The upper and lower buildup layers are electrically and thermally connected. The lower build-up layer 2b normally surrounds the build-up core substrate 1 and balances vertically symmetrically,
In many cases, the entire build-up wiring board 3 is provided to provide flatness without warpage. Build-up layers 2a, 2b
Is generally 1 to 3 layers, and Cu of this layer is often formed by plating. The circuit pattern is formed by etching plated Cu or plating by an additive method.

[0008]

The through-holes 8 of the conventional build-up core substrate 1 are usually made by drilling with a 0.3 mm drill and narrowed by a glass fiber inserted as a reinforcing material, thereby reducing the pitch. Is difficult, at best 1.
Only a rough thing of about 27 mm can be made. Accordingly, the bumps and the solder balls 5 of the semiconductor chip 4 whose pitch becomes narrower year by year
There is a great mismatch with the pitch of a, and the wiring of the build-up layer 2a must be routed to a large extent, so that the interlayer coupling must be of a so-called stagger type, which increases the wiring length. This means
Under the current situation where the signal transmission speed is delayed and the operating frequency reaches 1 GHz, this is a problem contrary to the need for high speed. There is also a problem that the rewiring length in the build-up core substrate becomes longer and the signal connection of the upper build-up layer 2a is limited.

Further, there is a problem that the lower buildup layer 2b cannot be effectively used because the number of through holes is small. This is because it can be used only for connection with the solder ball 5b for BGA. In a conventional manufacturing method in which a hole is drilled, the diameter of the through hole is large and the pitch is large, and the development of the wiring tends to be biased toward the upper surface of the build-up wiring board 3. Since the through hole of the build-up core substrate is much lower than the bump density of the semiconductor chip 4, there is a problem that the channel of the lower build-up layer 2b cannot be used.

Also, in the conventional build-up core substrate 1 shown in FIG. 10, only the plating layer on the inner wall of the through hole 8 can be involved in heat radiation, and there is a problem that heat dissipation is poor. Further, there is a method in which a Cu plate of a build-up core substrate is half-etched, and after embedding a resin, polishing is performed by planar polishing means until the ends of the plurality of heat and electric conductive posts are exposed. In this case, the exposed heat / electrically conductive posts and the unexposed heat / electrically conductive posts coexist, resulting in not only large variations, but also poor heat dissipation and poor reliability and workability. there were.

In conventional etching of a Cu plate, the shape and depth of holes formed by etching usually vary. This is because the etchability varies depending on the location. Next, the prepreg is laminated to fill all the etched holes, the Cu layer side is inverted and the back side is polished, and a plurality of Cu heat / electrically conductive posts are embedded in the resin at a predetermined pitch. In the case of manufacturing, there is a problem that the thickness of the Cu layer and the thickness of the insulating layer vary each time depending on where the polishing surface is stopped.

This problem will be described in detail with reference to FIG. FIG. 11A shows a cross-sectional shape of a conventional Cu plate after etching. There is unevenness in the etching depth, and the shape deviates from the ideal trapezoid. This is shown in FIG.
When the resin is filled as shown in FIG. 11 and etching is performed from the side of the Cu plate in FIG. 11B, etching remains as shown in FIG. 11C, and the resin protrudes and a short circuit (electric short circuit) occurs. For this reason, mechanical polishing of the back surface is further required, resulting in a problem that extra man-hours are required and uniformity is poor. This has been a problem of slowing down the signal transmission speed.

In addition, the receiving pad of the semiconductor element 4 needs to be large in order to ensure reliability, and as a result, the balance between the channel capacitances of the upper build-up layer 2a and the lower build-up layer 2b deteriorates. There was also the problem of forming disturbing stray capacitances. In addition, when a glass fiber reinforced epoxy resin substrate is used, drilling of through holes not only hinders fine drilling by glass fiber, but also causes fiber breakage, lowers reliability, and reduces the reliability of the plating process in later plating steps. There are also various problems such as infiltration of the plating solution. In addition, a filler is often added to the resin in order to adjust the coefficient of thermal expansion. However, in the case of processing a micro via (through hole), there is a problem that the particle size itself of the filler is hindered. . Therefore, the present invention provides a novel manufacturing method capable of uniformly controlling the thickness of the heat / electrically conductive post and the insulating layer without using mechanical polishing. As a result, a build-up wiring board optimal for high speed operation is provided. The purpose is to provide.

[0014]

Means for Solving the Problems The present invention has the following constitution to solve the above-mentioned problems. The symbols used in FIGS. 1 to 9 are shown in parentheses () for easy understanding. The technical idea of the present invention is not limited to the embodiment shown in FIGS. Note that the post forming layer 1
0, the heat / electrically conductive post 15, and the perforated plate 19 are used differently for different ones. For example, FIG.
In the description of the etching of FIG.
In the case of the build-up core substrate of FIG.
I'm calling 9. Similarly, the prepregs 12 and 13, the filling resin 14, and the insulating material 17 are, for example, the prepregs 12 and 13 and the screen shown in FIG. In the description of the manufacturing method of the build-up core substrate by the printing method, the filling resin 14 is used as a symbol, and in FIG. 4 which functionally describes the structure of the completed build-up core substrate, an insulating material 17 is used as a symbol.

{1} A thermally and electrically conductive plate (15) having a plurality of through holes (18) in the plate thickness direction;
8) a plurality of thermally and electrically conductive posts (16) provided in the form of islands, and the thermally and electrically conductive plate provided on the outer periphery of the plurality of thermally and electrically conductive posts (16). (1
5) and an insulating material (17) for electrically insulating the plurality of thermally and electrically conductive posts (16) from each other, and to both main surfaces of the thermally and electrically conductive plate (15). A build-up core substrate (1), comprising a bonded insulating plate (12, 13). The heat and electric conductive post (16)
May be called a metal post or a metal core as a lower concept.

{2} The build-up core substrate (1) according to {1}, wherein the plurality of thermally and electrically conductive posts (16) are made of Cu or a Cu alloy. {3} The plurality of thermally and electrically conductive posts (16) have a diameter of 0.01 to 0.2 mm and a pitch of 0.1 to 1.0 m.
m, the build-up core substrate (1) according to {1}. {4} The insulating material (17) is made of glass fiber reinforced epoxy resin, glass fiber reinforced bismaleimide triazine (BT) resin, or polyether sulfone (PE).
S) The build-up core substrate (1) according to {1}, which is any one of a compounded epoxy resin, a polyimide resin, and a polyamideimide resin. {5} The build-up core substrate (1) according to {1}, wherein an insulating material (17) and a perforated plate (19) are provided on the outer periphery of the plurality of thermally and electrically conductive posts (16). ). {6} The build-up core substrate according to the above {1} (1)
And a build-up wiring board (3) including build-up layers (2a, 2b) formed on the main surface of the build-up core board (1).

{7} A method for manufacturing a build-up core substrate (1), comprising the following steps. The post forming layer (1) is formed on one main surface of the barrier layer (9).
0), the carrier layer (11) is bonded to the other main surface. {Circle around (2)} The center of formation of the plurality of thermally and electrically conductive posts (16) is determined in the post forming layer (10). {C} A predetermined area (encircled by r and R in FIG. 4) from the center of formation of the heat and electric conductive post (16), which is larger than the radius (r in FIG. 4) of the heat and electric conductive post (16). (A masked region) is placed. {D} The predetermined area (area surrounded by r and R in FIG. 4)
Is removed by etching until the barrier layer (9) is reached, and a plurality of thermally and electrically conductive posts (16) are removed.
A pattern-etched product that stands out is made (FIG. 1B).
Here, "a plurality of thermal / electrically conductive posts (16) stand" is shown in FIG. 4B, for example. ｛After roughening the pattern etched product,
The prepreg (12) is laminated and heated and pressed to produce a first laminated product (FIG. 2 (a)). {F} The carrier layer (11) is removed from the first laminate (FIG. 2B). {G} Further, the barrier layer (9) is removed to obtain a second laminated product (FIG. 2 (c)). <2> The second laminate and the prepreg (13) are laminated and heated and pressed to produce a build-up core substrate (FIG. 2).
(D)).

{8} A method of manufacturing a build-up core substrate, comprising the following steps. The post forming layer (1) is formed on one main surface of the barrier layer (9).
0), the carrier layer (11) is bonded to the other main surface. {Circle around (2)} The center of formation of a plurality of thermally and electrically conductive posts is determined in the post forming layer (10). {Circle over (3)} A predetermined area larger than the radius of the heat and electric conductive post from the center of formation of the heat and electric conductive post (FIG. 4)
(A region surrounded by r and R) is placed. {D} The predetermined area (area surrounded by r and R in FIG. 4)
Is removed by etching until the barrier layer (9) is reached, and a plurality of thermally and electrically conductive posts (16) are removed.
A protruding pattern-etched product is produced (FIG. 3A). ｛E After roughening the pattern etching product,
The cavity (18) is filled with a resin by a screen printing method (FIG. 3B). {F} The carrier layer (11) is removed by etching (FIG. 3 (c)). (4) The barrier layer (9) is further removed by etching (FIG. 3 (d)). Next, prepregs (12, 13) are laminated from both sides of the main surface, and heated and pressed (FIG. 3 (e)).

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a build-up core substrate according to the present invention will be described below with reference to the drawings. FIG. 1 is a view showing a pattern-etched product of a build-up core substrate according to the present invention. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along the line AA. FIG. 2 is a view showing one method of manufacturing the build-up core substrate according to the present invention, FIG. 3 is a view showing another method of manufacturing the build-up core substrate according to the present invention, FIG.
1 is a perspective sectional view of a build-up core substrate according to the present invention. In FIG. 1, symbol 9 is a barrier layer, symbol 10 is a post forming layer, and symbol 11 is a carrier layer. As an example of the material, the barrier layer 9 is made of Ti, Sn, Ni, etc., the post forming layer 10 is made of Cu or an alloy thereof, and the carrier layer 3 is made of Cu.
Or its alloy. In the example shown in FIG.
Although the electrically conductive post and the insulating material form a concentric circle, it is not necessarily limited to the concentric shape.

First, the post forming layer 10 and the carrier layer 11 are joined to both surfaces of the barrier layer 9 with epoxy resin or the like. Alternatively, it may rely on metallurgical diffusion bonding. Next, a center for forming the heat / electrically conductive post is determined at a predetermined pitch, and a mask for removing a concentric circle having a predetermined diameter and a radius of the heat / electrically conductive post is placed from the center of the heat / electrically conductive post. I do. Since the present invention is not limited to FIG.
There is no limitation that the pitch is a predetermined pitch and concentric. In the present invention, since a drill is not used as in the related art, the pitch can be reduced to 1.0 mm or less, which is a narrower pitch than in the related art of about 1.27 mm. In the present invention, the lower limit of the pitch has been decreasing year by year with the progress of the etching technology, and currently, it is possible to reach about 0.1 mm. It goes without saying that this lower limit will be further reduced in the future.

Then, the post forming layer 10 is concentrically removed by etching until the post forming layer 10 reaches the barrier layer 9, and a plurality of heat and electric conductive posts 1 are formed.
A pattern-etched product (FIG. 1B) in which Oa stands at a predetermined pitch is produced. FIG. 4 is a sectional perspective view in which a plurality of heat / electrically conductive posts 10a are sealed in a prepreg 12 such as a glass fiber reinforced epoxy resin. When the build-up core substrate 1 of the present invention is used, as shown in FIG.
The heat is transmitted to not only the vertical direction of the plurality of heat / electrically conductive posts 10a but also other adjacent heat / electrically conductive posts in a relay manner, and the heat is radiated.

When the barrier layer 9 is made of Ti, an ethylenediamine-based Enstrip TL-142 (trade name, manufactured by Meltex Co., Ltd.) is used as the chemical etching solution. In addition, depending on the material of the barrier layer 9, Metec S
Commercial solutions such as CB (trade name of McDermid),
A mixture of nitric acid and hydrogen peroxide and a mixed acid of chromic acid and sulfuric acid can be used.

In the present invention, since the barrier layer functions as an etching stop layer, the plurality of thermally conductive posts 10a which are precisely controlled without variation in height.
Can be obtained. Further, no extra mechanical polishing is required. According to the present invention, having excellent etching properties, the results of observing the corners of the wiring portion with a microscope,
It was confirmed that the film was etched into an ideal shape.

This feature of the invention is important. It can be understood from the characteristic impedance of the microstrip line when the substrate is used for an electronic circuit. The characteristic impedance is expressed as ln (4h / (0.536w + 0.67) expressed by natural logarithm ln when the magnetic permeability and permittivity of the material are constant.
t)) is known in many textbooks, for example, "VLSI System Design" by Kisaburo Nakazawa et al. Here, the symbol h is the thickness of the insulating layer, the symbol w is the wiring width, and the symbol t is the wiring thickness. From this relational expression, it is understood that controlling the thickness of each of the insulating layer and the conductor layer is important for controlling the impedance. When the characteristic impedance is constant (for example, 50Ω), the insulation thickness decreases as the wiring width decreases,
The tolerance is also reduced. Further, the management of the width and the thickness becomes more strict. That is, in the era of high speeds at which the operating frequency approaches 1 GHz, it is important to control the thicknesses of the insulating layer and the conductor layer.

The material of the post forming layer 10 in the present invention is preferably Cu or an alloy thereof which is a conductor having good heat and electricity. Cu is an oxygen-free copper wire (OFC: Ox
ygenFree Copper), electrolytic copper and the like can be used. However, when metallurgical bonding such as diffusion bonding is used instead of adhesion with the barrier layer 9, it is preferable to add Sn, for example, to improve heat resistance.

Next, the method for manufacturing the build-up core substrate of the present invention will be described with reference to FIG. In the pattern-etched product (FIG. 1B), a plurality of thermally and electrically conductive posts 16 (indicated by double hatching in FIG. 1B) isolated in the form of islands stand between the hollow portions 18. . As shown in FIG. 2, a prepreg 12 such as a glass fiber reinforced epoxy resin is laminated on the pattern-etched product (FIG. 1B), and heated and pressed to form a first laminated product (FIG. 2A). The carrier layer 11 is removed from the first laminate with a ferric chloride solution. The carrier layer 11 improves handling due to its rigidity.

In order to improve the adhesive strength between the pattern-etched product (FIG. 1B) and the prepreg, it is preferable to roughen the metal surface of the pattern-etched product (FIG. 1B). Although there is no particular limitation on the method of the roughening treatment, fine bumps are formed by plating or mechanically polished to improve the adhesive force between the metal surface and the epoxy resin.

As a material of the prepreg, besides glass fiber reinforced epoxy resin, glass fiber reinforced bismaleimide triazine (BT) resin, or polyether sulfone (PES: poly-et)
her sulphon) epoxy resin, polyimide resin, polyamide imide resin, RCC (resin copper foil (Resin C
oated Copper)) and the like. In addition, as the uncured or semi-cured prepreg, a reinforcing material such as glass cloth, glass single fiber, paper, polyimide resin, epoxy resin, phenolic resin, or a mixture thereof, and a curing agent for each resin. Impregnated or semi-cured (B-stage) by heating can be used. As this resin, a thermoplastic resin such as a fluororesin can also be used.

In recent years, lead-free soldering has been rapidly progressing. Due to a rise in the temperature of the reflow furnace due to the lead-free process, a higher Tg (vitrification temperature) of the base material and the build-up layer is required. It is necessary to consider the build-up core substrate and the build-up layer of the present invention.

Further, the barrier layer 9 is formed by en strip TL
-142 concentrate to remove the second layered product (Fig. 2
(C)), the second laminate and the prepreg 13 are laminated, and heated and pressed to build up a core substrate (FIG. 2 (d)).
Get. Here, the material of the barrier layer is Ti, Sn, N
i or an alloy thereof, and the material of the post forming layer is Cu
Alternatively, the alloy and the material of the carrier layer are preferably Cu or an alloy thereof. In the present invention, the barrier layer 9 can be used as a means for controlling an accurate etching depth.

Another method of manufacturing the build-up core substrate according to the present invention will be described with reference to FIG. The steps up to the step of forming a pattern-etched product in which a plurality of the heat / electrically conductive posts 10a are arranged at a predetermined pitch are the same as those described with reference to FIG. Next, the pattern-etched product (FIG. 3)
The semi-cured resin 14 is filled by heating in the concave portion of FIG. 3A by a screen printing method (FIG. 3B). And
The carrier layer 11 is removed by etching (FIG.
(C)). Further, the barrier layer 9 is removed by etching (FIG. 3D), prepregs 12 and 13 are laminated from both sides of the main surface, and heated and pressed to obtain a build-up core substrate (FIG. 3).
(E)). An example of a method for manufacturing a build-up core substrate according to the present invention has been described with reference to FIGS. 2 and 3, but the present invention is not limited thereto, and a metal foil wound on a reel,
Continuous reeling by roller using resin film
By the reel-to-reel method, photo-etching and laminating processes can be performed continuously.

FIG. 4 is a partial sectional perspective view of the build-up core substrate 1 according to the present invention. An insulating material 17 surrounds the outer periphery of the plurality of standing heat and electric conductive posts 16,
A perforated plate 19 such as u is provided on the outer periphery thereof. The use of the build-up core board 1 according to the present invention is, as exemplified in FIG. 5, a build-up wiring board 3 in which build-up layers 2a and 2b are added above and below the build-up core board 1.
And so on. Generally, a build-up wiring board is, for example, a base part made of a glass-epoxy laminate, and a through-hole connecting the surface of the base is filled with an epoxy resin, or a surface-mounted build-up, or the aforementioned build-up. It refers to a combination of a wiring board and surface mounting. A wiring conductor layer is formed on each of the upper surface of the build-up layer 2a and the lower surface of the build-up layer 2b. The number of build-up layers is not limited to one but is often a plurality.

When the build-up core substrate 1 of the present invention is used as a build-up wiring board, the encapsulated heat and electric conductive posts are selectively used by opening them with a laser, for example. Thereby, the heat / electrically conductive post can be formed with extremely high precision. The heat / electrically conductive post functions as a thermal via, and has a configuration in which heat is efficiently transmitted through the thermal via.

The manufacture of the build-up wiring board illustrated in FIG. 5 in which the build-up layers (2a, 2b) are added to the build-up core board (1) is not particularly limited, and the above-described manufacturing methods are appropriately combined. Good. For example, a metal foil obtained by pattern-etching a circuit pattern on the build-up core substrate (1), the build-up core substrate (1), and the prepreg may be overlaid and pressurized and heated. As shown in FIG.
It is also easy to manufacture a more complicated build-up wiring board.

A method of manufacturing the build-up core substrate 3 shown in FIG. 6 will be described with reference to FIGS. FIG. 7 (a) shows the heat and heat of a plurality of forests such as Cu on one surface of the barrier layer 9.
FIG. 7 (b) shows the prepreg 12
FIG. 7C shows the pattern-etched product 20 in which holes of 0.3 mm in diameter are formed at a pitch of 0.4 mm. As shown in FIG. 7D, the heat / electrically conductive post 16, prepreg 12, and pattern-etched product 20 are laminated and pressed by a heated press plate to produce a laminated product.

FIG. 8A is a diagram showing the laminated product manufactured in FIG. 7D in an inverted state. This C
u carrier layer 11 and then part of the Ti barrier layer 9
Etching is removed as shown in FIG. Next, this is laminated with the prepreg 13 shown in FIG. 8C, and heated and pressed to obtain a laminated product shown in FIG. 8D, that is, the build-up core substrate 1.

In the build-up wiring board illustrated in FIG. 6, as shown by Vcc and Vss in the drawing, it is possible to use the power supply voltage layer and the ground layer properly according to the circuit configuration. According to the present invention, in order to easily enable such a configuration, in the present situation where the voltage fluctuation is likely to occur due to an increase in the clock frequency of the chip, a stable ground (ground, ground) Also called). Although FIG. 6 shows an example of the heat and electric conductive post superimposed on two layers, according to the present invention, any number of layers can be easily manufactured.

According to the present invention, an interposer provided with a plurality of heat / electrically conductive posts can be easily obtained, and an island-shaped heat / electricity isolated from the insulating substrate as a heat / electrically conductive post by etching the substrate. An electrically conductive post portion is formed. Since the substrate of the present invention uses a conductive plate having excellent etching properties, it is suitable for high-density wiring with a narrow pitch, so that the number of conventional build-up layers can be reduced. Therefore, when the substrate of the present invention is used, the wiring density of the substrate itself can be increased, and it is particularly effective for a build-up wiring substrate on which the substrate of the present invention is laminated, for example, flip-chip mounting, Wafer Level CSP, and the like. Reducing the number of build-up layers directly leads to cost reduction.

Further, according to the present invention, a semiconductor device can be formed using a build-up wiring board. Although the semiconductor device of the present invention is not particularly limited, it is flip-chip mounted via a solder ball for guiding a signal from a semiconductor chip to the outside, and further mounted on a build-up wiring board in which a plurality of printed boards are stacked. Since the semiconductor device can transmit a signal and uses a conductive plate having a good etching property suitable for a narrow pitch, it is particularly suitable for a semiconductor device directly mounted on a build-up wiring board.

Further, in the present invention, since it is suitable for high-density wiring with a narrow pitch, the number of stacked layers in the conventional build-up can be reduced. Therefore, the wiring density can be increased by using the substrate of the present invention.

[0041]

According to the etching method using the barrier layer, it is possible to obtain a substrate enclosing the heat and electric conductive posts with extremely small variation in shape and size. Further, since short-distance wiring is enabled, it is possible to easily cope with an increase in operating frequency. Further, according to the present invention, since the metal core is used, the dimensional stability is excellent, and the rigidity is high even if it is thin.
The use of the electrically conductive post eliminates the need for a drilling or laser drilling process for through holes as in the prior art. No plating is necessary on the inner surface of the through-hole. In addition, since it can be manufactured at a high density, both the upper and lower surfaces of the build-up layer can be used, and the cost can be reduced by reducing the number of layers.

[Brief description of the drawings]

FIG. 1 is a view showing a pattern-etched product of a build-up core substrate according to the present invention.

FIG. 2 is a view illustrating one method of manufacturing the build-up core substrate according to the present invention.

FIG. 3 is a view showing another method of manufacturing a build-up core substrate according to the present invention.

FIG. 4 is a perspective view of a build-up core substrate according to the present invention.
It is a partial sectional view.

FIG. 5 is a diagram of a build-up wiring board according to the present invention.

FIG. 6 is a diagram of another build-up wiring board according to the present invention.

FIG. 7 is a view illustrating a part of a manufacturing process of the build-up core substrate illustrated in FIG. 6;

FIG. 8 is a diagram showing the remaining part of the manufacturing process of the build-up core substrate shown in FIG.

FIG. 9 is a schematic view showing a state of heat radiation of the build-up wiring board according to the present invention.

FIG. 10 is a view showing a conventional build-up wiring board.

FIG. 11 is a diagram illustrating a problem of a conventional etching method.

[Explanation of symbols]

1. Build-up core substrate, 2a. 2. Upper build-up layer 2b. Lower build-up layer, 3. build-up wiring board; 5. semiconductor chips, 5a, 5b solder balls, 6. Underfill, Wiring pattern,
8. 8. through hole, 9. barrier layer; Post forming layer 11. Carrier layer, 12,13. Prepreg,
14． 14. filled resin; Heat and electric conductive plate, 1
6. 17. thermal and electrical conductive posts; 17. insulating material;
Cavity, 19. Perforated plate, 20. Pattern etching product

Claims (8)

[Claims] 1. A thermally and electrically conductive plate having a plurality of through holes in a plate thickness direction, a plurality of island-shaped thermally and electrically conductive posts provided in the through holes, and the plurality of heat An insulating material provided on the outer periphery of the electrically conductive post and interposed between the thermally and electrically conductive plate to electrically insulate the plurality of thermally and electrically conductive posts; A build-up core substrate comprising an insulating plate bonded to both main surfaces of a conductive plate. 2. The method of claim 2, wherein the plurality of thermally and electrically conductive posts are C
The build-up core substrate according to claim 1, wherein the substrate is a u or Cu alloy. 3. The plurality of thermally and electrically conductive posts have a diameter of 0.01 to 0.2 mm and a pitch of 0.1 to 1.0 m.
The build-up core substrate according to claim 1, wherein m is m. 4. The insulating material is a glass fiber reinforced epoxy resin, a glass fiber reinforced bismaleimide triazine (B
T) Resin or polyether sulfone (PES)
2. The composition according to claim 1, wherein the resin is one of a compounded epoxy resin, a polyimide resin, and a polyamideimide resin.
The build-up core substrate as described. 5. The build-up core substrate according to claim 1, wherein an insulating material and a perforated plate are provided on the outer periphery of the plurality of heat and electric conductive posts. 6. A build-up wiring board comprising: the build-up core board according to claim 1; and build-up layers formed on both main surfaces of the build-up core board. 7. A method for manufacturing a build-up core substrate, comprising the following steps. (1) A post forming layer is bonded to one main surface of the barrier layer, and a carrier layer is bonded to the other main surface. (2) A center for forming a plurality of heat / electrically conductive posts is determined in the post forming layer. (3) A mask for removing a predetermined area larger than the radius of the heat and electric conductive post from the center of formation of the heat and electric conductive post is placed. (5) The predetermined area is removed by etching until the barrier layer is reached, thereby producing a pattern-etched product in which a plurality of heat and electric conductive posts are formed. (6) After roughening the pattern-etched product,
The prepreg is laminated and heated and pressed to form a first laminated product. (7) removing the carrier layer from the first laminate. (8) The barrier layer is further removed to obtain a second laminate. (9) The second laminate and the prepreg are laminated and heated and pressed to produce a build-up core substrate. 8. A method for manufacturing a build-up core substrate, comprising the following steps. (1) A post forming layer is bonded to one main surface of the barrier layer, and a carrier layer is bonded to the other main surface. (2) A center for forming a plurality of heat / electrically conductive posts is determined in the post forming layer. (3) A mask for removing a predetermined area larger than the radius of the heat and electric conductive post from the center of formation of the heat and electric conductive post is placed. (4) The predetermined region is removed by etching until the barrier layer is reached, thereby producing a pattern-etched product having a plurality of thermally and electrically conductive posts. (5) After roughening the pattern-etched product,
The cavity is filled with resin by a screen printing method. (6) The carrier layer is removed by etching. (7) The barrier layer is removed by etching. (8) Next, prepregs are laminated from both sides of the main surface and heated and pressed.