JP2001119317A - Radio communication device, frequency switching method for radio communication device, and recording medium - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To realize a frequency configuration that satisfies the indirect modulation scheme and the superheterodyne scheme with a smaller hardware configuration, and to enable high-speed frequency switching of wireless communication devices and wireless communication device frequency switching Providing a method and a recording medium. SOLUTION: TDMA communication is performed by including an indirect modulation type transmission unit 2, a super heterodyne type reception unit 3, and a local oscillation unit 1 for generating and supplying local oscillation signals for transmission and reception. . Here, the local oscillator 1 includes a reference oscillator 18, a phase comparator, a low-pass filter, a voltage controlled oscillator, a variable frequency divider, and a PLL frequency synthesizer including a frequency division number control circuit. A multiplier 19 for multiplying the output of the reference oscillator to set the frequency of the local oscillation signal for reception, and a frequency for controlling the frequency division control circuit of the PLL frequency synthesizer to variably set the frequency of the local oscillation signal for transmission And a setting control unit 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a time division multiplex (Time Division Multiplex)
Division Multiplex (hereinafter referred to as TDM) circuit and time division multiple access (Time Division Multiple Access:
The present invention relates to a wireless communication device such as a mobile phone for performing TDMA communication by TDMA, a frequency switching method of the wireless communication device, and a recording medium on which a program for executing the method is recorded. And a frequency configuration that satisfies both the super-heterodyne method of the receiver and the P hardware with less hardware.
The present invention relates to a wireless communication device capable of transmitting and receiving while switching the frequency of an LL frequency synthesizer at high speed, a frequency switching method of the wireless communication device, and a recording medium.

[0002]

2. Description of the Related Art In TDMA communication, one frame contains one frame.
By dividing the time using one radio frequency into several time slots, and each user using a different time slot, a plurality of users share the radio transmission path and communicate simultaneously. This TDMA communication
It is widely used in the field of mobile communication such as PDC (Personal Digital Cellular).

As a conventional example of such a radio communication apparatus for performing TDMA communication, the same inventor has filed Japanese Patent Application No. Hei 10-339.
FIG. 4 shows a configuration diagram of a wireless communication device filed in Japanese Patent Application No. 814. FIG. 1 is a configuration diagram centered on a local oscillator unit in a wireless communication device, and the local oscillator unit has a frequency configuration corresponding to an indirect modulation scheme during transmission and a frequency configuration corresponding to a super heterodyne scheme during reception. I am taking it.

[0004] In FIG. 4, a radio communication apparatus of the prior art includes a transmitting section 102 for performing transmission using an indirect modulation scheme, a receiving section 103 for performing reception using a super heterodyne scheme, and a first section.
And a local oscillator signal for transmission and reception by a second two-system PLL frequency synthesizer.
02 and a local oscillator 101 to be supplied to the receiver 103
, A transmission / reception switch 104 and an antenna 105
It is comprised including.

[0005] The transmitting unit 102 includes a modulator (MOD) 12
1, frequency converter 122, band pass filter (BP
F) 123, an automatic gain control amplifier (AGC) 124, and an amplifier 125. Also, the receiving unit 1
03 is a band pass filter (BPF) 131, an amplifier (AMP) 132, a first reception frequency converter 133, a second
Receive frequency converter 134, band pass filter (BP
F) 135 and a demodulator (DET) 136.

The local oscillator 101 further includes a temperature-compensated crystal oscillator (TCXO) 111 serving as a reference oscillator, and first and second PLL frequency synthesizer PLLs.
, A first voltage controlled oscillator (first VCO) 113, and a second voltage controlled oscillator (second VC
O) 114, a frequency setting control unit 115, a distributor 116, and a frequency divider 117. FIG. 5 shows a more detailed configuration diagram of the local oscillation unit 101.

In FIG. 5, a first PLL frequency synthesizer includes a reference oscillator 111, a first phase comparator (first P
C) 212, first low-pass filter (first LPF) 21
1, the first voltage controlled oscillator 113, the first variable frequency divider (first
PD) 213 and a first frequency division number control circuit 214. Similarly, the second PLL frequency synthesizer also includes a reference oscillator 111 and a second phase comparator (second phase comparator).
PC) 222, second low-pass filter (second LPF) 2
21, a second voltage controlled oscillator 114, a second variable frequency divider (second PD) 223, and a second frequency division number control circuit 224. Here, the PLL-IC unit 112 includes a reference oscillator 111 and a first voltage-controlled oscillator 11 among the first and second two-system PLL frequency synthesizers.
3, a configuration including components other than the first low-pass filter 211, the second low-pass filter 221, and the second voltage-controlled oscillator 114.

[0008] The memory 225 stores frequency setting information of the second PLL frequency synthesizer. That is, a fixed frequency setting is performed without performing the frequency switching control for the second PLL frequency synthesizer. On the other hand,
The frequency setting control unit 115 controls the frequency switching of the first PLL frequency synthesizer. As shown in FIG. 5, the frequency setting control unit 115 includes a register 215, a microprocessor (MPU) 216, and a timing control circuit 217.

Here, the register 215 holds frequency control information determined by software processing of the microprocessor 216. Further, the microprocessor 216 determines the switching frequency based on the designation information from the network side at a timing earlier than the slot switching timing, and sets the frequency control information based on the switching frequency in the register 215. Further, the timing control circuit 217 outputs a timing signal to the register 215 at the time of slot switching, and outputs information held in the register 215 to the first frequency division number control circuit 214. In the figure, CL
K indicates an operation clock of the microprocessor 216,
CLK ′ is a synchronous clock synchronized with the operation clock CLK. That is, the timing control circuit 217 generates a timing signal based on the synchronous clock CLK ′.

Next, the operation of the conventional radio communication apparatus having the above configuration will be described. Here, the reference numerals added to each signal line in FIG. 4 represent the signal frequency of the signal line. First, at the time of transmission, an output signal of the first voltage controlled oscillator 113 (first PLL frequency synthesizer) is supplied to the frequency converter 122 and the frequency divider 117 via the distributor 116. In the modulator 121, the signal that has been frequency-divided by N (here, frequency-divided by 1/4) by the frequency divider 117 is modulated by the transmission data TXD (I, Q). Then, the frequency converter 122 obtains a transmission frequency from the output signal of the modulator 121 and the output signal of the first voltage controlled oscillator 113, and as a modulated wave via the band-pass filter 123, the automatic gain control amplifier 124, and the amplifier 125. It is transmitted from the antenna 105.

At this time, if the output frequency of the first PLL frequency synthesizer is F1st, the transmission frequency FTX can be obtained by the following equation. FTX = F1st + (F1st / 4)

At the time of reception, the first voltage controlled oscillator 1
13 (a first PLL frequency synthesizer) and a reception signal received via the antenna 105 are input to a first reception frequency converter 133, and an output signal of the first reception frequency converter 133 is input to a first reception frequency converter 133. Obtained as the reception intermediate frequency.
Further, the second reception frequency converter 134 receives the output signal of the first reception intermediate frequency and the output signal of the second voltage controlled oscillator 114, and converts the output signal of the second reception frequency converter 134 into the second reception intermediate frequency. Obtain as frequency.

At this time, the reception frequency is set to F RX and the second P
If the output frequency of the LL frequency synthesizer is F2nd, the first reception intermediate frequency F1st-IF and the second reception intermediate frequency F2nd-IF are obtained by the following equations. F1st-IF = FRX-F1st F2nd-IF = F1st-IF-F2nd

As described above, in the wireless communication apparatus of the conventional example, both the indirect modulation scheme in the transmitting section 102 and the superheterodyne scheme in the receiving section 103 are satisfied in order to support TDMA communication such as the PDC scheme. In order to obtain a frequency configuration, the configuration of the local oscillation unit 101 including first and second two PLL frequency synthesizers is as follows.
It was realized with almost the same circuit scale as the configuration of the wireless communication device corresponding to the direct indirect method and the super heterodyne method before that. Further, with such a frequency configuration, the lock-up time of the PLL in switching the frequency of the first PLL frequency synthesizer between the transmission slot and the reception slot can be reduced.

[0015]

However, in a wireless communication device, there is a strong demand for realizing the device with less hardware (circuit) configuration in order to reduce the size and weight of the device. Also, from the viewpoint of minimizing the power consumption of the circuit in order to enable the battery to be used for a long time, there has been a strong demand for realizing the device with a smaller hardware (circuit) configuration.

The present invention has been made in view of the above-mentioned conventional circumstances, and realizes a frequency configuration that satisfies both an indirect modulation system of a transmitting unit and a superheterodyne system of a receiving unit. An object of the present invention is to provide a wireless communication device capable of transmitting and receiving while switching the frequency of a PLL frequency synthesizer at high speed by hardware, a method of switching the frequency of the wireless communication device, and a recording medium.

[0017]

According to a first aspect of the present invention, there is provided a radio communication apparatus comprising: a transmitting section for performing transmission by an indirect modulation method; and a receiving section for performing reception by a super heterodyne method. And a local oscillation unit that generates local oscillation signals for transmission and reception and supplies the oscillation signals to the transmission unit and the reception unit, respectively, and performs TDMA communication. An oscillator,
A PLL frequency synthesizer including a phase comparator, a low-pass filter, a voltage controlled oscillator, a variable frequency divider, and a frequency division number control circuit; and a frequency division number control circuit of the PLL frequency synthesizer. A frequency setting control section for variably setting the frequency of the local oscillation signal for transmission; and a multiplying means for multiplying the output of the reference oscillator to set the frequency of the local oscillation signal for reception.

In a second aspect of the present invention, in the wireless communication apparatus according to the first aspect, the local oscillation unit includes frequency dividing means for dividing an output signal of the PLL frequency synthesizer. A transmitting unit that modulates an output signal of the frequency dividing unit with transmission data; a transmission frequency conversion unit that receives an output signal of the modulation unit and an output signal of the PLL frequency synthesizer to obtain an output signal of a transmission frequency; Means, wherein the receiving unit is configured to receive the received signal and the PL.
A first receiving frequency converting means for receiving an output signal of the L frequency synthesizer to obtain an output signal of a first receiving frequency; a second receiving frequency for receiving an output signal of the first receiving frequency and an output signal of the multiplying means; And a second reception frequency conversion means for obtaining the output signal of

According to a third aspect of the present invention, there is provided a wireless communication apparatus according to the first or second aspect, wherein the multiplying means is effectively operated only during reception.

According to a fourth aspect of the present invention, in the wireless communication apparatus according to the first, second or third aspect, the frequency setting control unit includes a storage unit for holding frequency control information, and a slot switching timing. Control means for determining the switching frequency based on the designation information from the network side at an earlier timing, and setting frequency control information based on the switching frequency in the storage means, and holding information of the storage means at the slot switching timing. And a timing control unit for outputting the output signal. At the same time as the slot switching, the information held in the storage unit is supplied to the frequency division number control circuit of the PLL frequency synthesizer to switch the frequency of the output signal.

According to a fifth aspect of the present invention, there is provided a frequency switching method for a wireless communication device, comprising:
A receiving unit for performing reception in a superheterodyne system, a PLL frequency synthesizer having a reference oscillator, and a multiplying unit for multiplying the output of the reference oscillator to generate a local oscillation signal for transmission and reception and to generate the transmission unit A frequency switching method for a wireless communication device that performs TDMA communication with a local oscillation unit that supplies the reception unit, wherein the switching frequency is determined at a timing earlier than the slot switching timing based on the designation information from the network side. Determining, and storing the frequency control information based on the switching frequency; and controlling the PLL based on the storage information of the storing step at the slot switching timing.
A switching step of switching the frequency of the output signal of the frequency synthesizer.

According to a sixth aspect of the present invention, there is provided a computer-readable recording medium recorded as a program for causing a computer to execute the frequency switching method for a wireless communication device according to the sixth aspect.

In the radio communication apparatus according to the first aspect of the present invention, in order to have a frequency configuration that satisfies both the indirect modulation scheme of the transmitting section and the superheterodyne scheme of the receiving section,
A conventional local oscillator includes a PLL frequency synthesizer having a reference oscillator and a multiplying means for multiplying the output of the reference oscillator, and has a first and a second PLL frequency synthesizer. The number of circuits can be greatly reduced as compared with the configuration of the local oscillation unit, and a wireless communication device can be realized with a smaller hardware (circuit) configuration.

In particular, in the radio communication apparatus according to the first and second aspects, at the time of transmission, a signal obtained by dividing the output signal of the PLL frequency synthesizer by the frequency dividing means by the modulating means is modulated by the transmitting data, and the transmission frequency is converted. By means,
An output signal of a transmission frequency is obtained from the output signal of the modulating means and the output signal of the PLL frequency synthesizer, and transmission is performed. At the time of reception, the first reception frequency conversion means converts the received signal and the output signal of the PLL frequency synthesizer into signals. , An output signal of the first reception frequency is obtained from the output signal, and the second reception frequency conversion means obtains an output signal of the second reception frequency from the output signal of the first reception frequency and the output signal of the multiplication means, and performs reception. Like that. Thereby, when transmitting, PL
By using only the L frequency synthesizer and using the PLL frequency synthesizer and the multiplying means at the time of reception, it is possible to realize the frequency configuration in the wireless communication apparatus of the transmission indirect modulation method and the reception super heterodyne method.

In the wireless communication apparatus according to the first, second and third aspects, it is sufficient to use only the PLL frequency synthesizer at the time of transmission, as described above. Therefore, only the PLL frequency synthesizer is effectively operated and the multiplication means is used. Is stopped, and conversely, the multiplying means is activated effectively only during reception. As a result, current consumption of the wireless communication device can be reduced, and power consumption can be reduced.

A wireless communication apparatus according to a fourth aspect, a frequency switching method for a wireless communication apparatus according to a fifth aspect, and
In the recording medium according to the sixth aspect, the frequency setting control unit sets the switching frequency of the transmission local oscillation signal by the PLL frequency synthesizer at a timing earlier than the slot switching timing based on the designation information from the network side. Then, at the slot switching timing, frequency control information based on the setting information is supplied to the frequency division number control circuit of the PLL frequency synthesizer to perform the control.

That is, in the frequency switching control of the PLL frequency synthesizer, the frequency control information is held in hardware storage means such as a register based on the switching frequency determined in advance (at a timing earlier than the slot switching timing) by software processing, At the same time as the slot switching, the frequency control information is supplied to the frequency synthesizer according to the hardware timing. As a result, it is possible to eliminate the delay of the frequency setting due to the software processing at the time of switching, shorten the time of frequency switching,
P in transmission and reception slots in TDMA communication
Transmission and reception can be performed while switching the frequency of the LL frequency synthesizer at high speed.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a wireless communication apparatus, a frequency switching method for a wireless communication apparatus, and a recording medium according to the present invention will be described below in detail with reference to the drawings. In addition,
In the description of each embodiment, the wireless communication device and the frequency switching method of the wireless communication device according to the present invention will be described in detail, but the recording medium according to the present invention is used to execute the frequency switching method of the wireless communication device. Since the recording medium is a recording medium on which the program is recorded, the description thereof is included in the following description of the frequency switching method of the wireless communication device.

FIG. 1 is a configuration diagram of a wireless communication apparatus according to one embodiment of the present invention. In the local oscillator unit in the wireless communication device of the present embodiment, at the time of transmission, the indirect modulation method,
At the time of reception, a frequency configuration corresponding to each of the superheterodyne systems is adopted, and TDMA communication is performed.

In FIG. 1, the radio communication apparatus according to the present embodiment includes a transmitting unit 2 for performing transmission using an indirect modulation system, a receiving unit 3 for performing reception using a super heterodyne system, a PLL frequency synthesizer and a multiplier 19. It includes a local oscillation unit 1 that generates a local oscillation signal for trust and reception and supplies it to the transmission unit 2 and the reception unit 3, a transmission / reception switch 4, and an antenna 5.

The transmitting section 2 has a configuration including a modulator (MOD) 21, a frequency converter 22, a band-pass filter (BPF) 23, an automatic gain control amplifier (AGC) 24, and an amplifier 25. The receiving unit 3 includes a band-pass filter (BPF) 31, an amplifier (AMP) 32, a first reception frequency converter 33, a second reception frequency converter 34, a band-pass filter (BPF) 35, and a demodulator (DET). )
36.

The local oscillator 1 further includes a PLL-IC unit 12, a voltage controlled oscillator (VCO) 13, a distributor 16, and a frequency divider 1 which constitute a PLL of a PLL frequency synthesizer.
7. Temperature-compensated crystal oscillator (X'ta
l) A configuration including 18 and a multiplier 19. FIG. 2 shows a more detailed configuration diagram of the local oscillation unit 1.

In FIG. 2, the PLL frequency synthesizer includes a reference oscillator 18, a phase comparator (PC) 42, a low-pass filter (LPF) 41, a voltage controlled oscillator 13, a variable frequency divider (PD) 43, and a frequency dividing number. The control circuit 44 is provided. Here, the PLL-IC unit 12 includes P
The LL frequency synthesizer includes a phase comparator 42, a variable frequency divider (PD) 43, and a frequency division number control circuit 44.

The frequency setting control unit 15 controls the frequency switching of the PLL frequency synthesizer and the switching of the operation / non-operation of the multiplier 19, as shown in FIG.
The configuration includes a register 45, a microprocessor (MPU) 46, and a timing control circuit 47.

Here, the register 45 corresponds to the storage means in the claims, and holds the frequency control information determined by the software processing of the microprocessor 46. Further, the microprocessor 46 corresponds to the control means, determines the switching frequency based on the designation information from the network side at a timing earlier than the slot switching timing, and sets the frequency control information based on the switching frequency in the register 45. Further, the timing control circuit 47
Registers the timing signal in the register 45 when the slot is switched.
And the information held in the register 45 is output to the frequency division number control circuit 44. In the figure, CLK indicates an operation clock of the microprocessor 46, and CLK 'is a synchronous clock synchronized with the operation clock CLK. That is, the timing control circuit 47 generates a timing signal based on the synchronous clock CLK ′.

The output frequency F1st of the PLL frequency synthesizer is frequency-switched and controlled by the frequency setting control unit 15, but the output frequency F2nd of the other multiplier 19 is changed by the multiplier 19 to the output frequency of the reference oscillator 18. The frequency is multiplied by M (here, multiplied by 9), and fixed frequency setting is performed without performing frequency switching control. The switching control of the operation / non-operation of the multiplier 19 is performed by the control signal mc from the timing control circuit 47. As a result, the multiplier 19 operates effectively only at the time of reception, and the power consumption of the device can be reduced.

Next, the operation of the wireless communication apparatus according to this embodiment having the above configuration will be described in detail. In addition, reference numerals added to each signal line in FIG. 1 represent a signal frequency of the signal line. First, at the time of transmission, the output signal of the voltage controlled oscillator 13 (PLL frequency synthesizer) is supplied to the frequency converter 22 and the frequency divider 17 via the distributor 16. In the modulator 21, the signal divided by N (here, divided by）) by the divider 17 is modulated by the transmission data TXD (I, Q). And frequency converter 2
2, the output signal of the modulator 21 and the voltage-controlled oscillator 13
, A transmission frequency is obtained from the output signal, and transmitted as a modulated wave from the antenna 5 via the band-pass filter 23, the automatic gain control amplifier 24, and the amplifier 25.

At this time, if the output frequency of the PLL frequency synthesizer is F1st, the transmission frequency FTX can be obtained by the following equation. FTX = F1st + (F1st / 4)

At the time of reception, the voltage controlled oscillator 13
(PLL frequency synthesizer) output signal and antenna 5
The received signal received via the first receiving frequency converter 3
3 to obtain an output signal of the first reception frequency converter 33 as a first reception intermediate frequency. The second reception frequency converter 34 receives the output signal of the first reception intermediate frequency and the output signal of the multiplier 19, and obtains the output signal of the second reception frequency converter 34 as the second reception intermediate frequency. .

At this time, if the reception frequency is FRX, the output frequency of the PLL frequency synthesizer is F1st ', and the output frequency of the multiplier 19 is F2nd, the first reception intermediate frequency F1st-IF and the second reception intermediate frequency F2nd -IF is obtained by the following equation. F1st-IF = FRX-F1st 'F2nd-IF = F1st-IF-F2nd

As described above, the wireless communication apparatus of the present embodiment satisfies both the indirect modulation method in the transmission unit 2 and the superheterodyne method in the reception unit 3 in order to support TDMA communication such as the PDC method. In order to obtain a frequency configuration, the local oscillator 1 including a PLL frequency synthesizer having a reference oscillator 18 and a multiplier 19 for multiplying the output of the reference oscillator 18 has first and second configurations.
In this case, the number of circuits is greatly reduced as compared with the configuration of the conventional local oscillation unit having the two systems of PLL frequency synthesizers, thereby realizing a configuration with less hardware (circuit).

Since it is sufficient to use only the PLL frequency synthesizer at the time of transmission, only the PLL frequency synthesizer is effectively operated, and the operation of the multiplier 19 is stopped. Conversely, the multiplier 19 is enabled only at the time of reception. Since it is sufficient to operate the wireless communication device, the current consumption of the wireless communication device can be reduced and power consumption can be reduced.

Next, a frequency switching method in the wireless communication apparatus according to the present embodiment will be described in detail. As described above, the frequency setting controller 15 controls the voltage-controlled oscillator 13
(PLL frequency synthesizer) output signal frequency F1s
The switching of t is performed. The outline of the frequency switching control is as follows. The microprocessor 46 determines the switching frequency based on the designated information from the network side at a timing earlier than the slot switching timing, and performs the frequency control based on the switching frequency. The information is set in the register 45, and the frequency control information of the register 45 is supplied to the frequency division number control circuit 44 of the PLL frequency synthesizer at the time of slot switching according to the timing signal from the timing control circuit 47.

FIG. 3 is a timing chart for explaining the time lapse when frequency switching is performed at the time of slot switching in the wireless communication apparatus of this embodiment. As shown in FIG. 7B, the timing of the software processing of the microprocessor 46 is marked by a clock at a predetermined interval. As shown in FIG. 7A, when the slot A (the output frequency F1st = Fa of the voltage controlled oscillator 13) is switched to the slot B (F1st = Fb), first,
The process is activated by the trigger of the frequency setting process at time T1, and the switching frequency is determined based on the designated information from the network side. That is, this software processing is performed from time T1 to T2 as shown in FIG. 3C, and frequency control information based on the switching frequency determined at time T2 as shown in FIG. Is held in the register 45.

Next, at time T3, the microprocessor 46 issues a trigger for frequency switching, outputs a timing signal from the timing control circuit 47 to the register 45, and controls the frequency control from the register 45 to the frequency division number control circuit 44. PLL-IC by supplying information
Is set for the frequency (Fb).
At this time, as shown in FIG. 7E, the time from the frequency setting (time T3) to the PLL-IC to the time T4 elapses as the frequency pull-in time in the frequency synthesizer, and thereafter, at the time T4, the frequency synthesizer The output of the frequency Fb is supplied from the voltage controlled oscillator 13. Note that the frequency pull-in time from time T3 to T4 is
The frequency is permitted as an indefinite frequency switching section.

As described above, in the frequency switching method in the wireless communication apparatus according to the present embodiment, the switching frequency is determined in advance by software processing (at a timing earlier than the slot switching timing), and the frequency control information is determined based on the switching frequency. The frequency control information is stored in the register 45 and, at the same time as the slot switching, is supplied to the frequency division number control circuit 44 by hardware timing by the timing control circuit 47 to be set in the frequency synthesizer. By this frequency switching control, it is possible to eliminate the delay caused by software processing caused by the simultaneous processing of frequency setting and other software processing, shorten the frequency switching time to only the frequency pull-in time, and perform transmission and reception in TDMA communication. It is possible to perform transmission and reception while switching the frequency of the PLL frequency synthesizer at high speed in each of the slots.

In the conventional radio communication apparatus (FIGS. 4 and 5), the output frequency F of the second PLL synthesizer is
Since the 2nd can be adjusted by changing the frequency setting information in the memory 225, it is possible to design the receiver of the super heterodyne system in the wireless communication device before that as it is. On the other hand, in the wireless communication apparatus of the present embodiment, the output frequency F of the multiplier 19 is fixed to the multiplier M of the multiplier 19 determined at the time of design.
It is necessary to keep in mind that there is a disadvantage in the design cost that there is a restriction in the setting of the 2nd, and it is difficult to design using the previous super heterodyne receiver as it is.

[0048]

As described above, according to the radio communication apparatus of the present invention, the frequency configuration that satisfies both the indirect modulation scheme of the transmitting section and the superheterodyne scheme of the receiving section is provided.
It can be realized as a configuration of a local oscillator having a PLL frequency synthesizer having a reference oscillator and a multiplying means for multiplying the output of the reference oscillator. A communication device can be realized.

In particular, at the time of transmission, only the PLL frequency synthesizer is effectively operated and the operation of the multiplying means is stopped. Conversely, the multiplying means is effectively operated only at the time of reception, so that the current consumption of the radio communication apparatus is reduced. Power consumption can be reduced.

According to the radio communication apparatus, the frequency switching method of the radio communication apparatus, and the recording medium of the present invention, the frequency setting control section switches the frequency of the local oscillation signal for transmission by the PLL frequency synthesizer to the slot switching. Since the switching frequency is set based on the designation information from the network side at a timing earlier than the timing, the frequency control information based on the setting information is supplied to the frequency division number control circuit of the PLL frequency synthesizer at the slot switching timing, and the switching frequency is set. A radio that can perform transmission and reception while switching the frequency of the PLL frequency synthesizer in each of the transmission and reception slots in TDMA communication by reducing the frequency setting time due to software processing at the time of switching and shortening the frequency switching time. Frequency switching of communication devices and wireless communication devices It is possible to provide a law and a recording medium.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a wireless communication device according to an embodiment of the present invention.

FIG. 2 is a more detailed configuration diagram of a local oscillation unit in the wireless communication device of the embodiment.

FIG. 3 is a timing chart for explaining a lapse of time when frequency switching is performed at the time of slot switching in the wireless communication apparatus according to the embodiment.

FIG. 4 is a configuration diagram centering on a local oscillator unit in a conventional wireless communication device.

FIG. 5 is a more detailed configuration diagram of a local oscillation unit in a conventional wireless communication device.

[Explanation of symbols]

1,101 Local oscillator 2,102 Transmitter 3,103 Receiver 4,104 Transmission / reception switch 5,105 Antenna 18,111 Reference oscillator, Temperature compensated crystal oscillator (T
CXO) 12, 112 PLL-IC section 13 Voltage-controlled oscillator (VCO) 113 First voltage-controlled oscillator (first VCO) 114 Second voltage-controlled oscillator (second VCO) 15, 115 Frequency setting control section 16, 116 Divider 17, 117 frequency divider 21, 121 modulator (MOD) 22, 122 frequency converter 23, 123 bandpass filter (BPF) 24, 124 automatic gain control amplifier (AGC) 25, 125 amplifier 31, 131 bandpass filter (BPF) 32, 132 Amplifier (AMP) 33, 133 First reception frequency converter 34, 134 Second reception frequency converter 35, 135 Band pass filter (BPF) 36, 136 Demodulator (DET) 41, 211, 221 Low pass Filter (LPF) 42, 212, 222 Phase comparator (PC) 4 , 213, 223 variable frequency divider (PD) 44,214,224 division number control circuit 45,215 register 46,216 microprocessor (MPU) 47,217 timing control circuit 225 memory

Claims (6)

[Claims] A transmitting unit that performs transmission using an indirect modulation method; a receiving unit that performs reception using a super heterodyne method; and a local oscillation signal for transmission and reception is generated and transmitted to the transmitting unit and the receiving unit, respectively. A local oscillator for supplying;
In the wireless communication device for performing TDMA communication comprising: a local oscillator, a reference oscillator, a phase comparator, a low-pass filter, a voltage controlled oscillator, a variable frequency divider, a frequency division number control circuit, A PLL frequency synthesizer, a frequency setting control unit that controls a frequency division control circuit of the PLL frequency synthesizer to variably set the frequency of the local oscillation signal for transmission, and multiplies an output of the reference oscillator. And a frequency multiplier for setting a frequency of the local oscillation signal for reception. 2. The local oscillation section has frequency dividing means for dividing an output signal of the PLL frequency synthesizer; the transmitting section has a modulating means for modulating an output signal of the frequency dividing means with transmission data; A transmission frequency conversion unit that receives an output signal of the modulation unit and an output signal of the PLL frequency synthesizer to obtain an output signal of a transmission frequency, wherein the reception unit includes a reception signal and an output of the PLL frequency synthesizer. A first reception frequency conversion unit that receives a signal to obtain an output signal of a first reception frequency; and receives an output signal of the first reception frequency and an output signal of the multiplication unit to obtain an output signal of a second reception frequency. And a second reception frequency conversion means.
A wireless communication device according to claim 1. 3. The wireless communication apparatus according to claim 1, wherein the multiplying means is operated effectively only during reception. 4. A frequency setting control unit comprising: storage means for holding frequency control information; and a switching frequency determined based on designated information from a network at a timing earlier than a slot switching timing, and a frequency based on the switching frequency. Control means for setting control information in the storage means; and timing control means for outputting information held in the storage means at the slot switching timing. At the same time as the slot switching, the information held in the storage means is stored in the PLL. 4. The wireless communication apparatus according to claim 1, wherein the frequency is supplied to a frequency division number control circuit of the frequency synthesizer to switch the frequency of the output signal. 5. A transmitting unit for performing transmission using an indirect modulation method, a receiving unit for performing reception using a superheterodyne method, a PLL frequency synthesizer including a reference oscillator, and a multiplying unit for multiplying an output of the reference oscillator. A local oscillation unit for generating local oscillation signals for transmission and reception and supplying the local oscillation signals to the transmission unit and the reception unit.
A frequency switching method for a wireless communication device that performs communication, comprising: a determination step of determining a switching frequency based on specification information from a network side at a timing earlier than a slot switching timing; and storing frequency control information based on the switching frequency. A switching step of switching the frequency of the output signal of the PLL frequency synthesizer based on the storage information of the storage step at the slot switching timing. 6. A computer-readable recording medium recorded as a program for causing a computer to execute the frequency switching method for a wireless communication device according to claim 5.