JP2001119031A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

(57) Abstract: A semiconductor device which is an offset type transistor formed on an SOI substrate and which does not generate a leak current flowing through an interface between a silicon layer and a buried oxide film due to a potential difference between the silicon layer and a support substrate. A manufacturing method is provided. A semiconductor device and a method of manufacturing the same, wherein a leak stopper layer having the same conductivity type as the silicon layer and a high impurity concentration is formed under a source region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an SOI structure (Si
1. Field of the Invention The present invention relates to a semiconductor device using an SOI substrate having a silicon-on-insulator structure and a method of manufacturing the same, and more particularly, to a semiconductor device capable of eliminating a leak current flowing at a buried oxide film interface and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional structure of an offset transistor having an offset structure formed on an SOI substrate is described below.
This will be described with reference to the cross-sectional view of FIG.

FIG. 2 shows a conventional structure of an offset transistor formed on an SOI substrate. The SOI substrate 1 has a structure in which a buried oxide film 19 is provided on a support substrate 17 and a silicon layer 3 is provided on the buried oxide film 19. A gate oxide film 15 is provided on the surface of the silicon layer 3, and a gate electrode 21 is provided on the gate oxide film 15. The source region 7 is provided at one end of the gate electrode 21. The offset drain region 9 is provided on the gate electrode 21 on the side opposite to the source region 7. The drain region 5 is provided in the offset drain region 9 apart from the gate electrode 21. Metal electrode 11 is electrically connected to drain region 5 and source region 7. Except for the region to which the metal electrode 11 is connected, the insulating film 2 is formed on the surface of the silicon layer 3.
3 is provided. In the insulating film 23, a contact hole 31 for providing the metal electrode 11 is provided.

In the offset type transistor, an offset drain region 9 having a concentration lower than the impurity concentration of the drain region 5 is provided between the drain region 5 and a PN junction formed by the silicon layer 3. Therefore, when the drain region 5 and the silicon layer 3 are reverse-biased, the depletion layer is more likely to expand, so that the transistor can be used at a high power supply voltage.

Next, a conventional technique for manufacturing an offset transistor formed on the SOI substrate shown in FIG. 2 will be described with reference to the drawings. 2 to 5 are cross-sectional views illustrating a method of manufacturing an offset transistor according to a conventional technique in the order of steps.

As shown in FIG. 3, the SOI substrate 1 has a structure in which a buried oxide film 19 is provided on a support substrate 17 and a silicon layer 3 is provided on the buried oxide film 19. First, a photoresist (not shown) is formed on the entire upper surface of the SOI substrate 1 by a spin coating method. Subsequently, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so that a region where the offset drain region 9 is formed is opened.

Subsequently, using a photoresist as an ion implantation blocking film, impurities (not shown) of a conductivity type different from that of the silicon layer 3 are ion-implanted over the entire surface of the SOI substrate 1. After that, the photoresist is removed. Subsequently, the offset drain region 9 is formed by performing a heat treatment to diffuse the impurities.

Next, as shown in FIG. 4, an oxidation process is performed to form a gate oxide film 15 on the entire upper surface of the SOI substrate 1. Next, a film of a gate electrode material is formed on the entire upper surface of the gate oxide film 15.

Next, a photoresist (not shown) is formed on the entire upper surface of the gate electrode material by a spin coating method. Subsequently, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so as to open an area other than a region where the gate electrode 21 is formed. Subsequently, the gate electrode 21 is formed by etching until the gate electrode material in the photoresist opening is completely removed. After that, the photoresist is removed.

Next, as shown in FIG. 5, a photoresist 25 is formed on the entire upper surface of the SOI substrate 1 by a spin coating method. Subsequently, an exposure process and a development process are performed using a predetermined photomask, and the photoresist 25 is patterned so that regions where the drain region 5, the source region 7, and the gate electrode 21 are formed are opened. Subsequently, the photoresist 25 is used as an ion implantation blocking film, and further, an impurity of a conductivity type different from that of the silicon layer 3 is ion-implanted into the entire surface of the SOI substrate 1 in a self-aligned manner with the gate electrode 21, and the drain region 5 is formed. The source region 7 is formed. After that, the photoresist is removed.

Next, an insulating film 23 is formed over the entire upper surface of the SOI substrate 1. Subsequently, the impurities implanted into the drain region 5 and the source region 7 are electrically activated by performing a heat treatment in a nitrogen atmosphere. The heat treatment in the nitrogen atmosphere also serves to planarize the surface of the insulating film 23.

Next, as shown in FIG. 2, a photoresist (not shown) is formed on the entire upper surface of the insulating film 23 by a spin coating method. Subsequently, an exposure process and a development process are performed using a predetermined photomask, and a photoresist (not shown) is patterned so that the contact hole 31 is opened.

Subsequently, etching is performed until the insulating film 23 in the photoresist opening is completely removed, and a contact hole 31 is formed. After that, the photoresist is removed. Subsequently, a metal electrode 11 is formed on the entire upper surface of the SOI substrate 1.
Of a metal electrode material for forming a film.

Next, a photoresist (not shown) is formed on the entire upper surface of the SOI substrate 1 by a spin coating method.
Subsequently, using a predetermined photomask, an exposure process,
A development process is performed, and a photoresist (not shown) is patterned so as to open an area other than the area where the metal electrode 11 is to be formed.

Subsequently, etching is performed until the metal electrode material in the photoresist opening is completely removed.
Form one. After that, the photoresist is removed.

Thus, an offset transistor using an SOI substrate according to the conventional technique as shown in FIG. 2 can be formed.

[0017]

When an offset transistor formed on an SOI substrate is used, the potential of the silicon layer 3 and the potential of the support substrate 17 may be different. For example, in a CMOS circuit, when the support substrate 17 is grounded, the potential of the silicon layer 3 of the P-channel type offset transistor may be different because the silicon layer 3 becomes a power supply voltage.

In the state where the positive and negative potentials of the silicon layer 3 and the supporting substrate 17 deplete the silicon layer 3 on the buried oxide film 19 side, if the potential difference is large, an inversion layer is formed at the interface between the silicon layer 3 and the buried oxide film 19. It is formed. Further, a depletion layer of the PN junction of the source region 7 and a depletion layer extending from the buried oxide film 19 side are connected. When the depletion layer is connected, the potential of the support substrate 17 influences the potential of the PN junction of the source region 7 irrespective of the potential of the silicon layer 3, the potential barrier is lowered, and carriers are supplied to the inversion layer. You.
Normally, the drain region 5 has a reverse bias with respect to the silicon layer 3, so that carriers flow into the drain region 5 from the inversion layer.

Therefore, a leak current flowing at the interface between the silicon layer 3 and the buried oxide film 19 occurs due to the potential difference between the silicon layer 3 and the support substrate 17.

As described above, in the semiconductor device according to the prior art described with reference to FIG. 2, a leak current flowing through the interface between silicon layer 3 and buried oxide film 19 occurs due to the potential difference between silicon layer 3 and support substrate 17. .

[Object of the Invention] It is an object of the present invention to solve the above-mentioned problems and to provide a semiconductor device capable of preventing a leak current generated in the semiconductor device and a method of manufacturing the same.

[0022]

In order to achieve the above object, a semiconductor device and a method of manufacturing the same according to the present invention employ the following structure and manufacturing method.

A semiconductor device according to the present invention is a semiconductor device provided on an SOI substrate, comprising a gate oxide film provided on a silicon layer, a gate electrode provided on the gate oxide film, and one end of the gate electrode. A source region of a different conductivity type from the silicon layer, an offset drain region provided on the side opposite to the source region of the gate electrode of a different conductivity type from the silicon layer, and a silicon layer provided in the offset drain region apart from the gate electrode; A drain electrode of a type, a metal electrode electrically connected to the drain region and the source region, and a leak stopper layer having the same conductivity type as the silicon layer and a high impurity concentration below the source region.

A semiconductor device according to the present invention is a semiconductor device provided on an SOI substrate, comprising a gate oxide film provided on a silicon layer, a gate electrode provided on the gate oxide film, and one end of the gate electrode. A source region of a different conductivity type from the silicon layer, an offset drain region provided on the side opposite to the source region of the gate electrode of a different conductivity type from the silicon layer, and a silicon layer provided in the offset drain region apart from the gate electrode; Drain region, a metal electrode electrically connected to the drain region and the source region, and a leak stopper layer under the source region having the same conductivity type as the silicon layer not in contact with the buried oxide film and having a high impurity concentration. It is characterized by the following.

The semiconductor device according to the present invention includes a step of selectively implanting impurity atoms of a silicon layer and a different conductivity type into an SOI substrate and applying a heat treatment to form an offset drain region; Forming a leak stopper layer by selectively ion-implanting impurity atoms of the same conductivity type as the layer and applying heat treatment;
A step of forming a gate oxide film on the surface of the silicon layer by performing an oxidation treatment in an oxidizing atmosphere; a step of forming a gate electrode by forming a gate electrode material over the entire surface and performing a photoetching treatment; A step of forming a drain region and a source region by selectively ion-implanting a layer and impurity atoms of a different conductivity type; a step of forming a contact hole by forming an insulating film over the entire surface and performing a photoetching process; Forming a metal electrode material over the entire surface and performing a photo-etching process to form the metal electrode.

[Operation] In the offset transistor of the present invention, the impurity concentration of the leak stopper layer provided below the source region is higher than the impurity concentration of the silicon layer.
The depletion layer is difficult to stretch. Therefore, the depletion layer extending from the PN junction of the source region and the depletion layer extending from the buried oxide film side are not connected. As a result, the supply of carriers is cut off, so that no leak current flows even if an inversion layer is formed at the interface between the silicon layer and the buried oxide film.

Therefore, the leakage current caused by the potential difference between the silicon layer and the supporting substrate does not occur in the semiconductor device of the present invention.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments for carrying out the present invention will be described below with reference to the drawings. First, the structure of a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

[Structure of Semiconductor Device: FIG. 1] FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention.
The structure of the semiconductor device according to the embodiment of the present invention will be described with reference to FIG.

First, the structure of the SOI substrate 1 will be described. A buried oxide film 19 is provided on the support substrate 17. The thickness of the buried oxide film 19 is about 1 μm. The silicon layer 3 is provided on the buried oxide film 19. The thickness of the silicon layer 3 is about 1 μm.

Next, the structure of the offset transistor will be described. A gate oxide film 15 made of a silicon oxide film is provided on the silicon layer 3. A gate electrode 21 is provided on the gate oxide film 15. Polycrystalline silicon is used for the gate electrode 21. The source region 7 is provided at one end of the gate electrode 21. The offset drain region 9 is provided in a region of the gate electrode 21 opposite to the source region 7. The drain region 5 is provided in the offset drain region 9 apart from the gate electrode 21. As an impurity of the drain region 5 and the source region 7, a phosphorus atom is used in the case of N type, and a boron atom is used in the case of P type. The leak stopper layer 1 is formed in a region below the source region 7.
3 is provided. The leak stopper layer 13 has the same conductivity type as the silicon layer 3 and has a higher impurity concentration than the silicon layer 3. As an impurity of the leak stopper layer 13, a phosphorus atom is used in the case of N-type, and a boron atom is used in the case of P-type. An insulating film 23 is provided on the silicon layer 3, and a contact hole 31 is provided on the drain region 5 and the source region 7. Insulating film 23
Uses a silicon oxide film doped with boron atoms and phosphorus atoms. The metal electrode 11 is provided in the contact hole 31. The metal electrode 11 has a drain region 5 and a source region 7
Is electrically connected to Aluminum is used for the metal electrode 11.

In the semiconductor device of the present invention, since the impurity concentration of the leak stopper layer 13 is higher than that of the silicon layer 3, the depletion extending from the interface between the silicon layer 3 and the buried oxide film 19 due to the potential difference between the silicon layer 3 and the support substrate 17. The layer and the depletion layer extending from the PN junction of the source region are less likely to extend. Therefore, the depletion layer at the PN junction of source region 7 and the depletion layer from buried oxide film 19 are not connected.

Even if an inversion layer is formed at the interface between the silicon layer 3 and the buried oxide film 19 due to the potential difference between the silicon layer 3 and the support substrate 17, carriers are not supplied from the source region 7 because the depletion layer is not connected. . Therefore, no leak current flows through the interface between the silicon layer 3 and the buried oxide film 19.

[Description of Method of Manufacturing Semiconductor Device: FIG. 1, and FIGS. 6 to 10] Next, a method of manufacturing the structure of the semiconductor device shown in FIG. 1 will be described with reference to the drawings. 1 and 6 to 10 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

As shown in FIG. 6, the SOI substrate 1 has a buried oxide film 19 on a support substrate 17 and a silicon layer 3 on the buried oxide film 19. First, the conductivity type is P-type and the impurity concentration is 1 × 10 ¹⁶ cm.
^{- 3} about the surface of the silicon layer 3 is formed on the whole upper surface by spin coating a photoresist (not shown). Next, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so that a region where the offset drain region 9 is formed is opened.

[0036] Subsequently, using the photoresist as an ion implantation blocking layer, implantation energy 50 KeV, a dose of 1 × 10 ^{1 3} implanted cm ^- the N-type impurity at about ^two conditions (not shown) are implanted. A phosphorus atom is used as the N-type impurity. Thereafter, the photoresist is removed using sulfuric acid (H ₂ SO ₄ ). Subsequently, heat treatment is performed in a nitrogen atmosphere at a temperature of 1100 ° C. for a time period of about 4 hours to diffuse impurities and form an offset drain region 9.

Next, as shown in FIG. 7, a photoresist (not shown) is formed on the entire upper surface of the SOI substrate 1 by a spin coating method. Next, an exposure process and a development process are performed using a predetermined photomask, and the leak stopper layer 1 is formed.
The photoresist is patterned so that the region for forming 3 is opened.

Subsequently, using a photoresist as an ion implantation blocking film, an implantation energy of 100 KeV,
Dose of 1 × 10 ^{1 3} implanted cm ^- P ² about conditions
A type impurity (not shown) is ion-implanted. A boron atom is used as the P-type impurity. Thereafter, the photoresist is removed using sulfuric acid.

Subsequently, at a temperature of 1000 in a nitrogen atmosphere.
A heat treatment is performed at about 3 ° C. for about 3 hours to diffuse impurities and form a leak stopper layer 13.

Next, as shown in FIG. 8, heat treatment is performed in an oxygen atmosphere at a temperature of 1000 ° C. for about 2 hours.
A gate oxide film 15 having a thickness of about 80 nm is formed. Further, a gate electrode material made of polycrystalline silicon is formed on the entire upper surface of the gate oxide film 15 by using a chemical vapor deposition method (CVD method) using monosilane (SiH ₄ ) as a reaction gas.

Subsequently, a photoresist (not shown) is formed on the entire upper surface of the SOI substrate 1 by a spin coating method. Next, an exposure process and a development process are performed using a predetermined photomask, and the photoresist is patterned so as to open an area other than a region where the gate electrode 21 is formed. Subsequently, using a reactive ion etching method using sulfur hexafluoride (SF ₆ ) and oxygen (O ₂ ) as an etching gas, etching is performed until the gate electrode material in the photoresist opening is completely removed, The gate electrode 21 is formed.
Thereafter, the photoresist is removed using sulfuric acid.

Next, as shown in FIG. 9, a photoresist 25 is formed on the entire upper surface of the SOI substrate 1 by a spin coating method. Next, an exposure process and a development process are performed using a predetermined photomask, and the photoresist 25 is patterned so that a region where the drain region 5 and the source region 7 are formed and a part of the gate electrode 21 are opened. .

[0043] Subsequently, using the photoresist as an ion implantation blocking film, further self-aligned manner with respect to the gate electrode 21, implantation energy 60 KeV, implantation dose 3 × 10 ^{1 5} cm- N-type impurity at about ^two conditions By ion implantation, a drain region 5 and a source region 7 are formed. A phosphorus atom is used as the N-type impurity. Thereafter, the photoresist is removed using sulfuric acid.

Next, as shown in FIG. 10, monosilane (SiH ₄ ) and phosphine (P
H ₃₎ and diborane (B ₂ H ₆₎ and oxygen chemical vapor deposition using (by CVD), an insulating film 23 of thickness 0.5μm approximately composed of a silicon oxide film containing phosphorus and boron as impurities To form a film on the entire surface. Thereafter, heat treatment is performed in a nitrogen atmosphere at a temperature of 900 ° C. for about 30 minutes. As a result, the impurities implanted into the drain region 5 and the source region 7 are activated. The heat treatment in the nitrogen atmosphere also serves to planarize the surface of the insulating film 23.

Next, as shown in FIG. 1, a photoresist (not shown) is formed on the entire upper surface of the insulating film 23 by a spin coating method. Next, an exposure process and a development process are performed using a predetermined photomask, and contact holes 3 are formed.
The photoresist is patterned so that the region for forming 1 is opened.

Subsequently, carbon tetrafluoride (CF) was used as the reaction gas.
₄₎ and helium (He) and trifluoromethane (CHF ₃₎
Is etched until the insulating film 23 and the gate oxide film 15 in the photoresist opening are completely removed by a reactive ion etching method using
To form Thereafter, the photoresist is removed using sulfuric acid.

Subsequently, a metal electrode material (not shown) for forming a metal electrode is formed in a film thickness of about 1 μm on the entire upper surface of the SOI substrate 1 by a sputtering method. Aluminum is used as the metal electrode material.

Next, a photoresist (not shown) is formed on the entire upper surface of the metal electrode material (not shown) by a spin coating method. Then, using a predetermined photomask,
Exposure processing and development processing are performed, and the photoresist is patterned so that openings are formed in areas other than the area where the metal electrode 11 is to be formed.

Subsequently, using a photoresist (not shown) as an etching mask, a reactive ion etching method using boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ) as a reaction gas is used to form a photoresist in the photoresist opening. Is etched until the metal electrode material is completely removed to form a metal electrode 11. Thereafter, the photoresist is removed using nitric acid (HNO ₃ ).

As a result, as shown in FIG. 1, an offset transistor having a leak stopper layer 13 below the source region 7 can be formed.

In the embodiment of the present invention described above, the case of the N-channel type offset transistor is shown. However, the same effect as that of the embodiment of the present invention can be obtained in the case of the P-channel type offset transistor. can get.
The method for manufacturing a P-channel type offset transistor is the same as the method described with reference to FIGS. 1 and 6 to 10 except that the conductivity type of the silicon layer 3 and the leak stopper layer 13 is N-type, and the offset drain region 9 and the drain region 5
And the conductivity type of the source region 7 may be P-type. It is preferable to use phosphorus atoms as impurities of the leak stopper layer 13. As the impurity atoms in the offset drain region 9, the drain region 5, and the source region 7, boron atoms may be used.

In the embodiment of the present invention described above, the leak stopper layer 13 is in contact with the buried oxide film 19, but as shown in FIG.
Is not in contact with the buried oxide film 19, the same effect as the embodiment of the present invention can be obtained. The method of manufacturing a semiconductor device having this structure is similar to that shown in FIG.
3 was carried out in a nitrogen atmosphere at a temperature of 10
The heat treatment at 00 ° C. for about 3 hours may be performed for about 1 hour.

According to the manufacturing method described in the embodiment of the present invention, a leak stopper layer 13 having a higher impurity concentration than silicon layer 3 is formed below source region 7 in an offset transistor using SOI substrate 1. . If a semiconductor device having this structure is used, the depletion layer extending from the buried oxide film 19 and the depletion layer extending from the PN junction of the source region 7 are not connected due to the potential difference between the silicon layer 3 and the support substrate 17. Therefore, no carrier is supplied from the source region 7, so that no leak current flows at the interface between the silicon layer 3 and the buried oxide film 19.

[0054]

As is apparent from the above description, the semiconductor device and the method of manufacturing the same according to the present invention are offset transistors formed on an SOI substrate and have a lower impurity concentration below the source region than the silicon layer. A leak stopper layer is formed.

If a semiconductor device having this structure is used,
Due to the potential difference between the silicon layer and the buried oxide film, the depletion layer extending from the PN junction of the source region does not connect to the depletion layer extending from the buried oxide film. As a result, no carrier is supplied from the source region, and no leak current flows at the interface between the silicon layer and the buried oxide film.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a structure of a semiconductor device and a method of manufacturing the same in a conventional technique.

FIG. 3 is a cross-sectional view illustrating a structure of a semiconductor device and a method of manufacturing the same in a conventional technique.

FIG. 4 is a cross-sectional view illustrating a structure of a semiconductor device and a method of manufacturing the same in a conventional technique.

FIG. 5 is a cross-sectional view showing a structure of a semiconductor device and a method of manufacturing the same in a conventional technique.

FIG. 6 is a cross-sectional view illustrating a structure of a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a structure of a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a structure of a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a structure of a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating a structure of a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

FIG. 11 is a cross-sectional view illustrating a structure of a semiconductor device according to an embodiment of the present invention.

[Explanation of symbols]

1: SOI substrate 3: Silicon layer
5: Drain region 7: Source region 9: Offset drain region 11: Metal electrode 13: Leak stopper layer 15: Gate oxide film 17: Support substrate 19: Buried oxide film 21: Gate electrode 23: Insulating film 25: Photoresist 31: Contact hole

Claims (3)

[Claims] 1. A semiconductor device provided on an SOI substrate, comprising a gate oxide film provided on a silicon layer, a gate electrode provided on the gate oxide film, and a silicon layer provided on one end of the gate electrode. A drain region of a different conductivity type from the silicon layer and provided on the side opposite to the source region of the gate electrode; and a silicon layer provided in the offset drain region apart from the gate electrode and a drain region of a different conductivity type. A semiconductor device, comprising: a metal electrode electrically connected to a drain region and a source region; and a leak stopper layer having the same conductivity type as the silicon layer and a high impurity concentration below the source region. 2. A semiconductor device provided on an SOI substrate, comprising a gate oxide film provided on a silicon layer, a gate electrode provided on the gate oxide film, and a silicon layer provided on one end of the gate electrode. A drain region of a different conductivity type from the silicon layer and provided on the side opposite to the source region of the gate electrode; and a silicon layer provided in the offset drain region apart from the gate electrode and a drain region of a different conductivity type. A metal electrode electrically connected to the drain region and the source region; and a leak stopper layer under the source region having the same conductivity type as the silicon layer not in contact with the buried oxide film and having a high impurity concentration. Semiconductor device. A step of forming an offset drain region by selectively ion-implanting impurity atoms of a conductivity type different from that of the silicon layer into the SOI substrate and applying a heat treatment to the SOI substrate; Forming a leak stopper layer by selectively ion-implanting the impurity atoms of the above and performing a heat treatment; and forming a gate oxide film on the surface of the silicon layer by performing an oxidation treatment in an oxidizing atmosphere. Forming a gate electrode material by forming a gate electrode material over the entire surface and performing a photoetching process; forming a drain region and a source region by selectively ion-implanting a silicon layer and impurity atoms of a different conductivity type; Forming a contact hole by forming an insulating film over the entire surface and performing a photo-etching process; Forming a metal electrode by performing a photo-etching process on the entire surface of the semiconductor device.