JP2001119001A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) [Problem] To provide a technique capable of obtaining a desired threshold voltage and improving BV _ds0 without increasing the cost. SOLUTION: An n-type semiconductor region 11 constituting a source is surrounded by a p-type semiconductor region 10a by oblique ion implantation from the source side of a p-type impurity using a protective insulating film 7a and a lower floating gate electrode 8a as a mask, at the same time ensuring the threshold voltage, the BV _ds0 of n-type semiconductor region 11 constituting the drain portion where with reference temperament without introducing the p-type impurity, thereby improving the BV _ds0.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to a semiconductor integrated circuit device having an AND-type batch erase nonvolatile semiconductor memory device. .

[0002]

2. Description of the Related Art An AND-type batch erasing nonvolatile semiconductor memory device (AND-type flash memory) is disclosed in
As described in JP-B-176705, a plurality of storage MISFETs (Metal Insulator Semiconductor Fi
eld Effect Transistor) and a switch MISFET.
In this memory cell block, the source of each storage MISFET is shared by the sub-source line formed by the buried diffusion layer wiring, and connected to one of the source and drain of the switch MISFET. Shared by other switches M
The structure is connected to one of the source and the drain of the ISFET.

Each storage MISFET, that is, a memory cell, is formed with a T-shaped cross-sectional shape composed of a lower floating gate electrode and an upper floating gate electrode, and an interlayer insulating film formed on the floating gate electrode. And a semiconductor region (source region) constituting a source and a semiconductor region (drain region) constituting a drain. A tunnel insulating film is formed between the lower floating gate electrode and the semiconductor substrate, and information is written or erased in the memory cell by a tunnel current passing through the tunnel insulating film.

By the way, the memory MISFET is miniaturized with the high integration of the flash memory, and the
There is a problem that the threshold voltage of the ET decreases. Therefore, for example, an impurity of the same conductivity type as that of the semiconductor substrate is implanted into the semiconductor substrate by ion implantation to store the memory M.
By surrounding the source region and the drain region of the ISFET with the same semiconductor region as the semiconductor substrate, a decrease in threshold voltage is suppressed.

[0005] USP 4,771,012 concerning manufacturing technology
In this example, a structure in which a diffusion layer is symmetrical with respect to the gate electrode and extends below the gate electrode is realized by ion-implanting the substrate obliquely from four directions.

[0006]

However, in developing the flash memory, the present inventor has found that the breakdown voltage (BV _ds0 ) between the source region and the drain region of the storage MISFET has a threshold voltage. It has been found that a problem arises in that the ion implantation for adjustment or punch-through control causes a reduction.

As a method of avoiding the above problem, for example, an impurity of the same conductivity type as that of the semiconductor substrate is implanted into the source region by ion implantation at a higher concentration than the semiconductor substrate, and only the source region is formed of the semiconductor region made of the impurity. A method of enclosing with is considered. However, in this method, it is necessary to cover the drain region with, for example, a resist mask to prevent the impurity from being implanted into the drain region, so that the number of steps increases.

An object of the present invention is to provide a technique capable of obtaining a desired threshold voltage and improving _BVds0 without increasing the cost.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In a method of manufacturing a semiconductor integrated circuit device according to the present invention, a tunnel insulating film formed on a surface of a semiconductor substrate, and a lower floating gate electrode formed on the semiconductor substrate via the tunnel insulating film. And forming a flash memory having an MISFET having an upper floating gate electrode and a control gate electrode formed on the upper floating gate electrode via an interlayer insulating film, the tunnel insulating film is formed on the surface of the semiconductor substrate. Forming a first conductive film and a first insulating film, and sequentially processing the first insulating film and the first conductive film to form a protective insulating film made of the first insulating film and the first conductive film. Forming the lower floating gate electrode made of a first conductive film; and performing a _first oblique ion implantation from one direction having an angle θ ₁ with respect to a normal direction of the semiconductor substrate. A step of introducing a first impurity of the same conductivity type as that of the semiconductor substrate into the semiconductor substrate to form a pair of first semiconductor regions; and ion implantation at an angle substantially equal to a normal direction of the semiconductor substrate. ,
Introducing a second impurity of a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate to form a pair of second semiconductor regions forming a source and a drain.

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein a tunnel insulating film formed on a surface of a semiconductor substrate and a lower floating gate electrode formed on the semiconductor substrate via the tunnel insulating film. And forming a flash memory having an MISFET having an upper floating gate electrode and a control gate electrode formed on the upper floating gate electrode via an interlayer insulating film, the tunnel insulating film is formed on the surface of the semiconductor substrate. Forming a first conductive film and a first insulating film, and sequentially processing the first insulating film and the first conductive film to form a protective insulating film made of the first insulating film and the first conductive film. Forming the lower floating gate electrode made of a first conductive film; and performing a _first oblique ion implantation from one direction having an angle θ ₁ with respect to a normal direction of the semiconductor substrate. Introducing a first impurity of the same conductivity type as that of the semiconductor substrate into the semiconductor substrate to form a pair of first semiconductor regions; and forming a pair of first semiconductor regions having an angle θ ₂ with respect to a normal direction of the semiconductor substrate. Introducing a second impurity of a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate by performing a second oblique ion implantation from the direction of, and forming a pair of second semiconductor regions constituting a source and a drain. Have

(3) A method for manufacturing a semiconductor integrated circuit device according to the present invention, wherein a tunnel insulating film formed on a surface of a semiconductor substrate and a lower floating gate electrode formed on the semiconductor substrate via the tunnel insulating film. And forming a flash memory having an MISFET having an upper floating gate electrode and a control gate electrode formed on the upper floating gate electrode via an interlayer insulating film, the tunnel insulating film is formed on the surface of the semiconductor substrate. Forming a first conductive film and a first insulating film, and sequentially processing the first insulating film and the first conductive film to form a protective insulating film made of the first insulating film and the first conductive film. Forming the lower floating gate electrode made of a first conductive film; and performing a _first oblique ion implantation from one direction having an angle θ ₁ with respect to a normal direction of the semiconductor substrate. A step of introducing a first impurity of the same conductivity type as that of the semiconductor substrate into the semiconductor substrate to form a pair of first semiconductor regions; and ion implantation at an angle substantially equal to a normal direction of the semiconductor substrate. ,
Introducing a second impurity of a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate to form a pair of second semiconductor regions constituting a part of a source and a drain; A third impurity of a conductivity type opposite to that of the semiconductor substrate is introduced into the semiconductor substrate by a second oblique ion implantation from another direction having an angle θ ₂ to form another part of the source and the drain. Forming a pair of third semiconductor regions.

(4) The method of manufacturing a semiconductor integrated circuit device according to the present invention is the method of manufacturing a flash memory according to (2), wherein the width of the second semiconductor region forming a source and the second forming a drain are included. The width of the semiconductor region is substantially equal, and the lower floating gate electrode is shifted to the drain side by (the thickness of the first insulating film and the first conductive film) × tan θ ₂ .

(5) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a flash memory according to (3), wherein the width of the third semiconductor region forming the source and the third forming the drain are different. The width of the semiconductor region is substantially equal, and the lower floating gate electrode is shifted to the drain side by (the thickness of the first insulating film and the first conductive film) × tan θ ₂ .

(6) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the method of manufacturing a flash memory according to (2), after forming the pair of first semiconductor regions, the protective insulating film and the lower portion may be formed. A side wall spacer composed of a second insulating film is formed on the side wall of the floating gate electrode, and then the second oblique ion implantation is performed.

(7) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the method of manufacturing a flash memory described in (3), after forming the pair of second semiconductor regions, the protective insulating film and the lower portion may be formed. A side wall spacer composed of a second insulating film is formed on the side wall of the floating gate electrode, and then the second oblique ion implantation is performed.

(8) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the method of manufacturing a flash memory according to any one of (1) to (7), the first oblique ion implantation is performed from a source side. And the second oblique ion implantation is oblique ion implantation from the drain side.

(9) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a flash memory according to any one of (1) to (7), wherein the angle θ ₁ and the angle θ ₂ are 15 About 30 degrees.

(10) In the method of manufacturing a semiconductor integrated circuit device according to the present invention, in the method of manufacturing a flash memory according to any one of (1) to (7), after forming the lower floating gate electrode, This is for forming an in-place film on a semiconductor substrate.

According to the above means, the first from one direction
Of the semiconductor region forming the source of the memory cell is surrounded by the semiconductor region of the opposite conductivity type to the semiconductor region forming the source, and the BV _ds0 of the semiconductor region forming the drain of the memory cell is regulated by oblique ion implantation. Since the impurity of the conductivity type opposite to that of the semiconductor region forming the drain is not introduced into the portion where the drain is formed, the threshold voltage can be secured and the decrease in BV _ds0 can be suppressed without increasing the number of steps.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

Embodiment 1 A method for manufacturing a storage MISFET (memory cell) of a flash memory according to an embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 1, a p-type well 2 is formed by ion-implanting a p-type impurity, for example, boron (B) into a semiconductor substrate 1. The above p-type well 2
Is, for example, about 1 × 10 ¹⁶ cm ⁻³ .
Next, an element isolation groove 3a is formed in the p-type well 2, and an element isolation region 3 is formed by embedding an insulating film 3b in the element isolation groove 3a.

Next, as shown in FIG. 2, in order to suppress punch-through between a semiconductor region (source region) forming a source and a semiconductor region (drain region) forming a drain, a p-type well 2 is formed. Then, a punch-through control layer 4 is formed by ion-implanting a p-type impurity, for example, B. The impurity concentration of the punch-through control layer 4 is, for example, about 1 × 10 ¹⁸ cm ⁻³ .

Next, as shown in FIG. 3, a silicon oxide film having a thickness of about 9 nm to be the tunnel insulating film 5 is formed by, for example, a thermal oxidation method or a chemical vapor deposition (Chemical Vapor Deposition).
n; CVD), a polycrystalline silicon film 6 and a silicon nitride film 7 are sequentially deposited on the semiconductor substrate 1 by, for example, a CVD method, as shown in FIG. The thickness of the polycrystalline silicon film 6 is, for example, about 70 nm,
The thickness of the silicon nitride film 7 is, for example, about 170 nm.

Thereafter, the silicon nitride film 7 and the polycrystalline silicon film 6 are sequentially etched using the resist pattern as a mask to form a part of the floating gate electrode by the polycrystalline silicon film 6, as shown in FIG. The lower floating gate electrode 8a to be formed is formed. The processed silicon nitride film 7 is used as the protective insulating film 7 for the lower floating gate electrode 8a.
Functions as a. Next, as shown in FIG. 6, an in-place film 9 is formed on the semiconductor substrate 1 by, for example, a thermal oxidation method or a CVD method. The in-place film 9 is provided to reduce damage that is likely to occur at the end of the lower floating gate electrode 8a and the end of the tunnel insulating film 5 at the time of oblique ion implantation to be described later. It is about 20 to 30 nm.

Next, as shown in FIG. 7, the protective insulating film 7a
P-type impurities, for example, B, are implanted into the p-type well 2 by oblique ion implantation from one direction using the lower floating gate electrode 8a as a mask, and the p-type semiconductor region 10a on the source side and the p-type semiconductor region on the drain side. Form 10b. The p-type impurity has an angle θ with respect to the normal direction of the semiconductor substrate 1, for example, 15 to 30 degrees, and is ion-implanted from the source side.

As a result, the p-type semiconductor region 10a provided on the source side is formed below the lower floating gate electrode 8a, while the p-type semiconductor region 10b provided on the drain side is formed as the lower floating gate electrode. It is not formed under 8a. The impurity concentration of the p-type semiconductor regions 10a and 10b is, for example, about 1 × 10 ¹⁸ cm ⁻³ .

Next, as shown in FIG. 8, the protective insulating film 7a
And n-type impurities are implanted into the p-type well 2 by ion implantation at substantially the same angle as the normal direction of the semiconductor substrate 1 using the lower floating gate electrode 8a as a mask.
A pair of n-type semiconductor regions 11 constituting a drain are formed. The n-type impurity is, for example, arsenic (As), and the dose of ion implantation is, for example, about 1 × 10 ¹⁵ cm ⁻² .

Next, as shown in FIG. 9, a silicon oxide film 12 of, for example, about 500 nm is formed on the semiconductor substrate 1 by CV.
After the deposition by the D method, as shown in FIG. 10, the silicon oxide film 12 is subjected to chemical mechanical polishing (Chemical Mechanical Polishing).
The surface is flattened by polishing using a polishing (CMP) method, thereby forming an isolation insulating film 12a composed of the silicon oxide film 12.

In the steps so far, the structure in which the lower floating gate electrode 8a is separated between different memory cell blocks is different from the structure in which one memory cell block is still separated for each memory cell. It is not formed and remains integrally formed.

Next, the protective insulating film 7a is removed by hot phosphoric acid or the like, and then a polycrystalline silicon film 13 of, eg, about 40 nm is deposited on the semiconductor substrate 1 by a CVD method as shown in FIG.

Thereafter, as shown in FIG. 12, by etching the polycrystalline silicon film 13 using the resist pattern as a mask, an upper floating gate electrode 8b constituting another part of the floating gate electrode 8 is formed. You. That is, the upper floating gate electrode 8b is connected to the lower floating gate electrode 8a.
To form a T-shaped floating gate electrode 8.
Since the floating gate electrode 8 is formed in a T-shape as described above, the area of the floating gate electrode 8 with respect to the control gate electrode is increased, and the capacitance between the floating gate electrode 8 and the control gate electrode is increased to perform coupling. And the controllability of the memory cell by the control gate electrode can be improved.

At this stage, the floating gate electrode 8 is separated on the element isolation region 3 in different memory cell blocks, but is separated for each memory cell in one memory block. It remains unified.

Next, as shown in FIG. 13, an interlayer insulating film 14 of, eg, about 14 nm is deposited on the floating gate electrode 8. The interlayer insulating film 14 may have, for example, a four-layer structure including a silicon oxide film, a silicon nitride film, a silicon oxide film, and a silicon nitride film from below. The silicon oxide film and the silicon nitride film can be formed by, for example, a CVD method.

Next, as shown in FIG. 14, a polycide film 15 of about 100 nm serving as a control gate electrode is deposited on the interlayer insulating film 14 by a CVD method.
As shown in FIG. 5, an insulating film 16 is further deposited. The insulating film 16 is, for example, a silicon oxide film. Thereafter, the insulating film 16 and the polycide film 15 are sequentially etched using the resist pattern as a mask, so that the polycide film 1 is etched.
5 is formed.

Next, the insulating film 16 and the control gate electrode 1
By using the mask 7 as a mask, the interlayer insulating film 14, the upper floating gate electrode 8b, and the lower floating gate electrode 8a are sequentially etched to separate the memory cells in the memory cell block. After the formation of the memory cell, an insulating film having a thickness of, for example, about 1000 nm is deposited on the semiconductor substrate 1 by a CVD method (not shown).

FIG. 16 shows the threshold voltage (V) of the memory cell.
_th ) and the gate length (Lg). FIG. 17 is a graph showing the relationship between _{BVds0 of} the memory cell and Lg. Solid lines represent V _th and BV _ds0 in the memory cell of the first embodiment, and dotted lines represent V _th and BV _ds0 in the conventional memory cell.

As shown in FIGS. 16 and 17, substantially the same V _th -Lg characteristic can be obtained in the memory cell of the first embodiment and the memory cell of the conventional system. BV _ds0 -Lg characteristic is improved about 1.5 about 0V than BV _ds0 -Lg characteristics of the memory cell of the conventional method.

As described above, according to the first embodiment, p
The n-type semiconductor region 11 forming the source is surrounded by the p-type semiconductor region 10a, and the BV _{ds0 of the} n-type semiconductor region 11 forming the drain is implanted by injecting the impurity into the semiconductor substrate by oblique ion implantation from one direction. Is not formed at the position where the rule is satisfied,
Without increasing the number of steps, it is possible to secure the threshold voltage and at the same time suppress the decrease in _BVds0 .

(Embodiment 2) FIG. 1 shows a method of manufacturing a memory cell of a flash memory according to another embodiment of the present invention.
8 and FIG.

First, in the first embodiment, the lower floating gate electrode 8a constituting a part of the floating gate electrode 8 is formed on the semiconductor substrate 1 in the same manner as in the manufacturing method described with reference to FIGS. After the formation, an in-place film 9 is formed on the semiconductor substrate 1 and then a p-type impurity is implanted into the p-type well 2 by oblique ion implantation from one direction,
A p-type semiconductor region 10a on the source side and p-type
The type semiconductor region 10b is formed.

Next, as shown in FIG.
a and the lower floating gate electrode 8a as a mask, an n-type impurity, for example, As is implanted into the p-type well 2 by oblique ion implantation from another direction to form a source n
The n-type semiconductor region 11b that forms the type semiconductor region 11a and the drain is formed.

The n-type impurity has an angle of, for example, 15 to 30 degrees with respect to the normal direction of the semiconductor substrate 1 and is ion-implanted from the drain side. The n-type semiconductor region 11a,
The impurity concentration of 11b is lower than the impurity concentration of n-type semiconductor region 18, for example, about 1 × 10 ²⁰ cm ⁻³ . Thereby, the n-type semiconductor region 11b constituting the drain
Is formed under the lower floating gate electrode 8a,
The n-type semiconductor region 11a constituting the source is not formed below the lower floating gate electrode 8a.

Thereafter, similarly to the manufacturing method described in the first embodiment, an upper floating gate electrode 8b constituting another part of the floating gate electrode 8, an interlayer insulating film 14, and a control gate electrode 17 are sequentially formed. Thereby, the memory cell shown in FIG. 19 is formed.

As described above, according to the second embodiment, it is possible to suppress a decrease in BV _ds0 not only in the drain region but also in the source region of the memory cell. This allows
When a voltage (drain voltage) is applied to the drain and a positive voltage is applied to the floating gate electrode 8 to form a channel, the drain voltage is transmitted to the source through the channel, and the BV _{ds0 of} the source region is low. Therefore, it is possible to avoid the problem that the drain voltage decreases.

(Embodiment 3) FIG. 2 shows a method of manufacturing a memory cell of a flash memory according to another embodiment of the present invention.
This will be described with reference to FIGS.

First, the lower floating gate electrode 8a constituting a part of the floating gate electrode 8 is formed on the semiconductor substrate 1 in the same manner as in the manufacturing method described with reference to FIGS. After the formation, an in-place film 9 is formed on the semiconductor substrate 1 and then a p-type impurity is implanted into the p-type well 2 by oblique ion implantation from one direction,
A p-type semiconductor region 10a on the source side and p-type
The type semiconductor region 10b is formed.

Next, as shown in FIG.
The n-type impurity, for example, phosphorus (P) is ion-implanted from the p-type well 2 at substantially the same angle as the normal direction of the semiconductor substrate 1 using the a and lower floating gate electrode 8a as a mask.
And a pair of n forming part of the source and drain
A type semiconductor region 18 is formed. The n-type semiconductor region 18
Is, for example, about 1 × 10 ¹⁸ cm ⁻³ .

Next, as shown in FIG. 21, oblique ion implantation from another direction using the protective insulating film 7a and the lower floating gate electrode 8a as a mask causes n-type impurities,
For example, As is injected into the p-type well 2 to form an n-type semiconductor region 11a forming another part of the source and an n-type semiconductor region 11b forming another part of the drain.

The n-type impurity has an angle of, for example, 15 to 30 degrees with respect to the normal direction of the semiconductor substrate 1, and is ion-implanted from the drain side. The n-type semiconductor region 11a,
The impurity concentration of 11b is lower than the impurity concentration of n-type semiconductor region 18, for example, about 1 × 10 ²⁰ cm ⁻³ .

Thereafter, similarly to the manufacturing method described in the first embodiment, an upper floating gate electrode 8b, an interlayer insulating film 14, and a control gate electrode 17 constituting another part of the floating gate electrode 8 are sequentially formed. Thereby, the memory cell shown in FIG. 22 is formed.

As described above, according to the third embodiment, n
By providing the type semiconductor region 18, an offset between the source region and the lower floating gate electrode 8 a can be prevented, so that a decrease in BV _ds0 of the source region can be suppressed and a decrease in the source read current can be avoided. Can be.

(Embodiment 4) FIG. 2 shows a method of manufacturing a memory cell of a flash memory according to another embodiment of the present invention.
This will be described with reference to FIGS.

First, a polycrystalline silicon film 6 and a silicon nitride film 7 are deposited on a semiconductor substrate 1 in the same manner as in the manufacturing method described with reference to FIGS. As shown in FIG. 23, the silicon nitride film 7 and the polycrystalline silicon film 6 are sequentially etched using the resist pattern as a mask, so that the lower floating gate electrode 8a forming a part of the floating gate electrode by the polycrystalline silicon film 6 is formed. Form.

Here, the lower floating gate electrode 8a is not disposed at the center of the active region surrounded by the element isolation region 3, and the width of the drain-side active region is smaller than the width of the source-side active region. So as to be shifted toward the drain side. The shift amount (L _off ) is determined by the n-type semiconductor region 1 as described later.
It depends on the angle of oblique ion implantation when forming 1a and 11b.

Next, as shown in FIG.
Above, for example, a thermal oxidation method or a CVD method, for example, 20 to
An in-place film 9 having a thickness of about 30 nm is formed.
Next, the protective insulating film 7a and the lower floating gate electrode 8a
Is implanted into the p-type well 2 by oblique ion implantation from one direction using as a mask to form a p-type semiconductor region 10a on the source side and a p-type semiconductor region 10b on the drain side.

The p-type impurity has an angle of, for example, 15 to 30 degrees with respect to the normal direction of the semiconductor substrate 1 and is ion-implanted from the source side. p-type semiconductor regions 10a, 1
The impurity concentration of 0b is, for example, about 1 × 10 ¹⁸ cm ⁻³ .

Then, an n-type impurity, for example, As, is implanted into the p-type well 2 by oblique ion implantation from another direction using the protective insulating film 7a and the lower floating gate electrode 8a as a mask, and the n-type impurity forming the source is formed. Semiconductor region 11a
And an n-type semiconductor region 11b constituting the drain is formed.

The n-type impurity has an angle of θ with respect to the normal direction of the semiconductor substrate 1 and is obliquely ion-implanted from the drain side. Since the above-mentioned n-type impurity is implanted by oblique ion implantation, a space between the end of the lower floating gate electrode 8a and the end of the n-type semiconductor region 11a constituting the source is provided.
Interval at which the threshold voltage can be adjusted (L _off = h
(Tan θ) is secured, and at the same time, the width (Ws) of the n-type semiconductor region 11a forming the source and the width (Wd) of the n-type semiconductor region 11b forming the drain become substantially equal.

Thereafter, similarly to the manufacturing method described in the first embodiment, an upper floating gate electrode 8b, an interlayer insulating film 14, and a control gate electrode 17 forming another part of the floating gate electrode 8 are sequentially formed. Thereby, the memory cell shown in FIG. 25 is formed.

In the fourth embodiment, the source and the drain are constituted by the pair of n-type semiconductor regions 11a and 11b. However, the pair of n-type semiconductor regions 11a and 11b and the pair of n-type semiconductor regions described in the third embodiment are used. The source and the drain may be constituted by the n-type semiconductor region 18.

As described above, according to the fourth embodiment, a decrease in the area of the n-type semiconductor region 11a constituting the source due to oblique ion implantation can be suppressed, so that an increase in resistance as a diffusion layer wiring can be prevented. .

(Embodiment 5) FIG. 2 shows a method of manufacturing a memory cell of a flash memory according to another embodiment of the present invention.
This will be described with reference to FIGS.

First, the lower floating gate electrode 8a forming a part of the floating gate electrode 8 on the semiconductor substrate 1 is formed on the semiconductor substrate 1 by the same manufacturing method as in the third embodiment, as shown in FIG.
Is formed, an in-place film 9 is formed on the semiconductor substrate 1. Then, a p-type impurity, for example, B is implanted into the p-type well 2 by oblique ion implantation from one direction to form a p-type semiconductor region 10a on the source side and a p-type semiconductor region 10b on the drain side. Impurities are implanted into the p-type well 2 by ion implantation,
A pair of n-type semiconductor regions 18 forming a drain are formed.

Next, as shown in FIG.
After an insulating film 19 is deposited thereon by a CVD method, the insulating film 1
9 is anisotropically etched by RIE (Reactive Ion Etching), and as shown in FIG.
Insulating film 7a and lower floating gate electrode 8 covered with
A side wall spacer 19a composed of the insulating film 19 is formed on the side wall of a.

Next, as shown in FIG.
a, an n-type impurity, for example, As, is implanted into the p-type well 2 by oblique ion implantation from another direction using the lower floating gate electrode 8a and the sidewall spacer 19a as a mask to form another part of the source. The n-type semiconductor region 11a and the n-type semiconductor region 11b constituting another part of the drain are formed.

The n-type impurity has an angle of, for example, 15 to 30 degrees with respect to the normal direction of the semiconductor substrate 1, and is ion-implanted from the drain side. The n-type semiconductor region 11a,
The impurity concentration of 11b is lower than the impurity concentration of n-type semiconductor region 18, for example, about 1 × 10 ²⁰ cm ⁻³ . Thus, the n-type semiconductor region 11b forming another part of the drain is formed under the sidewall spacer 19a, but the n-type semiconductor region 11a forming the other part of the source is formed on the side wall. It is not formed under the spacer 19a.

Next, as shown in FIG.
A silicon oxide film 12 of, for example, about 500 nm is
After the deposition by the VD method, as shown in FIG. 30, the silicon oxide film 12, the protective insulating film 7a, and the sidewall spacers 19a are polished by the CMP method, and the surfaces thereof are planarized. Insulating film 1 constituted by the gate and sidewall spacers 19a
2a is formed.

Next, the protective insulating film 7a is removed by hot phosphoric acid or the like, and then a polycrystalline silicon film 13 of, eg, about 40 nm is deposited on the semiconductor substrate 1 by a CVD method as shown in FIG.

Thereafter, as shown in FIG. 32, by etching the polycrystalline silicon film 13 using the resist pattern as a mask, an upper floating gate electrode 8b constituting another part of the floating gate electrode 8 is formed. You.

Next, as shown in FIG. 33, an interlayer insulating film 14 of, for example, about 14 nm is deposited on the floating gate electrode 8. The interlayer insulating film 14 may have, for example, a four-layer structure including a silicon oxide film, a silicon nitride film, a silicon oxide film, and a silicon nitride film from below.

Next, as shown in FIG. 34, a polycide film 15 of about 100 nm serving as a control gate electrode is deposited on the interlayer insulating film 14 by a CVD method.
As shown in FIG. 5, an insulating film 16 is further deposited. Thereafter, the insulating film 16 and the polycide film 15 are sequentially etched using the resist pattern as a mask to form a control gate electrode 17 composed of the polycide film 15.

Next, the insulating film 16 and the control gate electrode 1
Using the mask 8 as a mask, the interlayer insulating film 14, the upper floating gate electrode 8b, and the lower floating gate electrode 8a are sequentially etched to separate the memory cells in the memory cell block. After forming the memory cell, an insulating film is deposited on the semiconductor substrate 1 by a CVD method, though not shown.

In the fifth embodiment, the source and the drain are constituted by the pair of n-type semiconductor regions 11a and 11b and the pair of n-type semiconductor regions 19, but are constituted only by the pair of n-type semiconductor regions 11a and 11b. May be.

As described above, according to the fifth embodiment, the tunnel insulating film at the end of the lower floating gate electrode 8a at the time of ion implantation is formed by the sidewall spacer 19a provided on the side wall of the lower floating gate electrode 8a. 5 can be reduced, and the reliability of the tunnel insulating film 5 can be improved.

The device having the following features is manufactured by the method described in the embodiment. Without using a mask, the structure of the diffusion layer differs between the drain side and the source side with respect to the gate electrode and is asymmetric, so that layers formed by implanting ions obliquely with respect to the semiconductor substrate have the same impurity concentration. However, the structure is different between the drain side and the source side centering on the gate electrode. For example, in FIG. 35 of the fifth embodiment, the n-type impurity concentration layers 11a and 11b having a lower concentration than the diffusion layer 18 having a symmetrical structure of the drain and the source are formed by the layer 11a forming a part of the source and the drain 11a. (The shortest distance from the gate electrode depends on the layer 11b forming a part of the source.)
a is longer than the layer 11b forming a part of the drain). The p-type impurity concentration layers 10a and 10b are different between the source-side layer 10a and the drain-side layer 10b (the shortest distance from the gate electrode is shorter in the source-side layer 10a than in the drain-side layer 10b). In the case where the mask has an asymmetric structure, conventionally, only one of the respective layers 10a and 10b or only one of the layers 11a and 11b is formed.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0081]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, it is possible to secure the threshold voltage and improve the BV _ds0 without increasing the number of steps, so that the desired threshold voltage can be obtained without increasing the cost. BV _ds0 can be improved simultaneously with obtaining the voltage. In addition, the operating voltage range is thereby expanded, so that the degree of freedom in circuit design is improved.

[Brief description of the drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing a storage MISFET of an AND flash memory according to Embodiment 1 of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the first embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the first embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the first embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the first embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the first embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the first embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the first embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the first embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the first embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the first embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the first embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the first embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the first embodiment of the present invention;

FIG. 16 is a graph showing a relationship between a threshold voltage and a gate length of a memory cell.

FIG. 17 is a graph showing a relationship between BV _{ds0 of a} memory cell and a gate length.

FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the second embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the second embodiment of the present invention;

20 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to Embodiment 3 of the present invention; FIG.

FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the third embodiment of the present invention;

FIG. 22 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the third embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the fourth embodiment of the present invention;

FIG. 24 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the fourth embodiment of the present invention;

FIG. 25 is an essential part cross sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the fourth embodiment of the present invention;

FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the fifth embodiment of the present invention;

FIG. 27 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the fifth embodiment of the present invention;

FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the fifth embodiment of the present invention;

FIG. 29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the fifth embodiment of the present invention;

FIG. 30 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the fifth embodiment of the present invention;

FIG. 31 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the fifth embodiment of the present invention;

FIG. 32 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the fifth embodiment of the present invention;

FIG. 33 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the fifth embodiment of the present invention;

FIG. 34 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the fifth embodiment of the present invention;

FIG. 35 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the storage MISFET of the AND flash memory according to the fifth embodiment of the present invention;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 p-type well 3 element isolation region 3 a element isolation groove 3 b insulating film 4 punch-through control layer 5 tunnel insulating film 6 polycrystalline silicon film 7 silicon nitride film 7 a protective insulating film 8 floating gate electrode 8 a lower floating gate electrode 8 b Upper floating gate electrode 9 Implus blue film 10a P-type semiconductor region 10b P-type semiconductor region 11 N-type semiconductor region 11a N-type semiconductor region 11b N-type semiconductor region 12 Silicon oxide film 12a Isolation insulating film 13 Polycrystalline silicon film 14 Interlayer insulating film Reference Signs List 15 polycide film 16 insulating film 17 control gate electrode 18 n-type semiconductor region 19 insulating film 19a sidewall spacer

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) BH09

Claims (10)

[Claims] A tunnel insulating film formed on a surface of a semiconductor substrate; a lower floating gate electrode and an upper floating gate electrode formed on the semiconductor substrate via the tunnel insulating film; Having a control gate electrode formed with an interlayer insulating film interposed therebetween
A method of manufacturing a semiconductor integrated circuit device for forming a flash memory having: (a) forming a first conductive film and a first conductive film after forming the tunnel insulating film on a surface of the semiconductor substrate;
(B) sequentially processing the first insulating film and the first conductive film to form a protective insulating film made of the first insulating film and the lower portion made of the first conductive film; Forming a floating gate electrode; and (c) oblique ion implantation from one direction having an angle θ ₁ with respect to the normal direction of the semiconductor substrate, thereby implanting a first impurity of the same conductivity type as the semiconductor substrate. Introduced into the semiconductor substrate, a pair of first
Forming a semiconductor region; and
Introducing a second impurity of the opposite conductivity type to the semiconductor substrate into the semiconductor substrate to form a pair of second semiconductor regions forming a source and a drain. Method. 2. A tunnel insulating film formed on a surface of a semiconductor substrate; a lower floating gate electrode and an upper floating gate electrode formed on the semiconductor substrate via the tunnel insulating film; Having a control gate electrode formed with an interlayer insulating film interposed therebetween
A method of manufacturing a semiconductor integrated circuit device for forming a flash memory having: (a) forming a first conductive film and a first conductive film after forming the tunnel insulating film on a surface of the semiconductor substrate;
(B) sequentially processing the first insulating film and the first conductive film to form a protective insulating film made of the first insulating film and the lower portion made of the first conductive film; Forming a floating gate electrode; and (c) oblique ion implantation from one direction having an angle θ ₁ with respect to the normal direction of the semiconductor substrate, thereby implanting a first impurity of the same conductivity type as the semiconductor substrate. Introduced into the semiconductor substrate, a pair of first
Forming a semiconductor region, the (d). The by implantation oblique ion from other directions having an angle theta ₂ with respect to the normal direction of the semiconductor substrate, a second impurity opposite conductivity type to the semiconductor substrate Forming a pair of second semiconductor regions forming a source and a drain by introducing the semiconductor substrate into the semiconductor substrate. A tunnel insulating film formed on a surface of the semiconductor substrate; a lower floating gate electrode and an upper floating gate electrode formed on the semiconductor substrate via the tunnel insulating film; MISFET having a control gate electrode formed with an interlayer insulating film interposed therebetween
A method of manufacturing a semiconductor integrated circuit device for forming a flash memory having: (a) forming a first conductive film and a first conductive film after forming the tunnel insulating film on a surface of the semiconductor substrate;
(B) sequentially processing the first insulating film and the first conductive film to form a protective insulating film made of the first insulating film and the lower portion made of the first conductive film; Forming a floating gate electrode; and (c) oblique ion implantation from one direction having an angle θ ₁ with respect to the normal direction of the semiconductor substrate, thereby implanting a first impurity of the same conductivity type as the semiconductor substrate. Introduced into the semiconductor substrate, a pair of first
Forming a semiconductor region; and
A step of introducing a second impurity of a conductivity type opposite to that of the semiconductor substrate into the semiconductor substrate to form a pair of second semiconductor regions constituting a part of a source and a drain; and (e) a method of the semiconductor substrate. A third impurity of a conductivity type opposite to that of the semiconductor substrate is introduced into the semiconductor substrate by oblique ion implantation from another direction having an angle θ ₂ with respect to the line direction to form another part of the source and the drain. Forming a pair of third semiconductor regions to form a semiconductor integrated circuit device. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein a width of said second semiconductor region forming a source is substantially equal to a width of said second semiconductor region forming a drain, and The lower floating gate electrode is provided on the drain side (thickness of the first insulating film and the first conductive film) × ta.
The method of manufacturing a semiconductor integrated circuit device, characterized in that deviates n.theta ₂ degrees. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein a width of said third semiconductor region forming a source is substantially equal to a width of said third semiconductor region forming a drain, and The lower floating gate electrode is provided on the drain side (thickness of the first insulating film and the first conductive film) × ta.
The method of manufacturing a semiconductor integrated circuit device, characterized in that deviates n.theta ₂ degrees. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein after forming the pair of first semiconductor regions in the step (c), the protective insulating film and the lower floating gate electrode are formed. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a side wall spacer made of a second insulating film on a side wall; and then performing the oblique ion implantation in the step (d). 7. The method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein after forming the pair of second semiconductor regions in the step (d), the protective insulating film and the lower floating gate electrode are formed. A method for manufacturing a semiconductor integrated circuit device, comprising: forming a side wall spacer formed of a second insulating film on a side wall; and then performing the oblique ion implantation in the step (e). 8. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said oblique ion implantation from one direction is oblique ion implantation from a source side. Characterized in that the oblique ion implantation from the direction is oblique ion implantation from the drain side. 9. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein said angle θ ₁ and said angle θ ₂ are about 15 to 30 degrees. Of manufacturing a semiconductor integrated circuit device. 10. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein an in-place film is formed on the semiconductor substrate after the step (b). A method for manufacturing a semiconductor integrated circuit device.