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JP2001118950A - Method for manufacturing built-up multi-layered board - Google Patents

Method for manufacturing built-up multi-layered board

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Publication number
JP2001118950A
JP2001118950A JP29538199A JP29538199A JP2001118950A JP 2001118950 A JP2001118950 A JP 2001118950A JP 29538199 A JP29538199 A JP 29538199A JP 29538199 A JP29538199 A JP 29538199A JP 2001118950 A JP2001118950 A JP 2001118950A
Authority
JP
Japan
Prior art keywords
resin
built
chromate film
manufacturing
plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29538199A
Other languages
Japanese (ja)
Inventor
Nobuo Fuji
信男 藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal SMI Electronics Device Inc
Original Assignee
Sumitomo Metal SMI Electronics Device Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal SMI Electronics Device Inc filed Critical Sumitomo Metal SMI Electronics Device Inc
Priority to JP29538199A priority Critical patent/JP2001118950A/en
Publication of JP2001118950A publication Critical patent/JP2001118950A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a built-up multi-layered board using a resin material roughened with chromic acid, which is excellent in its via connection reliability. SOLUTION: In the method for manufacturing a built-up multi-layered board, a surface of a resin board is roughened with chromic acid, a chromate film formed on a wiring surface of a via bottom is removed, a via connection strength is increased to build up multiple substrates into a multi-layered board.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体搭載用のI
Cパッケージ、MCMおよび電子部品搭載用の多層プリ
ント回路基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an I / O
The present invention relates to a method for manufacturing a multilayer printed circuit board for mounting a C package, an MCM, and an electronic component.

【0002】[0002]

【従来の技術】近年、MPUの高周波駆動化が急速に進
み、パッケージ構造はW/BタイプのPGA(Pin
Grid Array)からフリップチップBGA(B
allGrid Array)に、また、パッケージ材
料の高周波化に有利な低誘電率樹脂材料とCuメッキ配
線に移行しつつある。今後ICパッケージは樹脂材料/
Cu配線を使用したフリップチップBGAに急速に移行
するものと予想される。こうした状況で近年ビルトアッ
プ基板が注目されている。プリント基板をコア基板、樹
脂材料を層間絶縁材、Cuメッキを配線形成に使用した
ビルトアップ多層基板はMPU搭載用のICパッケー
ジ、MCM、電子部品搭載用の高密度実装基板として注
目されており、プリント基板メーカー、ICパッケージ
メーカー、半導体メーカー等で精力的に開発が進められ
ている。
2. Description of the Related Art In recent years, high-frequency driving of MPUs has rapidly progressed, and the package structure has been W / B type PGA (Pin).
From Grid Array) to Flip Chip BGA (B
all Grid Array), and a low-dielectric resin material and Cu-plated wiring, which are advantageous in increasing the frequency of the package material. IC packages will be made of resin materials /
It is expected that there will be a rapid shift to flip chip BGA using Cu wiring. Under these circumstances, a built-up substrate has recently been receiving attention. A built-up multilayer board using a printed board as a core board, a resin material as an interlayer insulating material, and Cu plating for wiring formation has attracted attention as an IC package for mounting an MPU, an MCM, and a high-density mounting board for mounting electronic components. The development is being vigorously pursued by printed circuit board manufacturers, IC package manufacturers, semiconductor manufacturers, and the like.

【0003】ビルトアップ基板の製造工程では、層間絶
縁層に使用される樹脂とCu導体の密着信頼性を確保す
るため、樹脂表面を適当な酸化剤で部分溶解させ、樹脂
表面に凹凸を形成させる粗化処理(デスミア処理)が通
常行われている。酸化剤としては、KMnO4またはC
rO3が通常使用されている。
In the manufacturing process of a built-up substrate, the resin surface is partially dissolved with an appropriate oxidizing agent to form irregularities on the resin surface in order to secure the adhesion reliability between the resin used for the interlayer insulating layer and the Cu conductor. Roughening processing (desmear processing) is usually performed. As the oxidizing agent, KMnO 4 or C
rO 3 is commonly used.

【0004】ここで粗化処理にCrO3を使用する樹脂
においては、樹脂表面の粗化と共にビア接続界面となる
Cu表面には、CrO3によりクロメート皮膜が形成さ
れる。クロメート皮膜が形成されたCuにめっきを行っ
ても金属間結合ができないため、めっき層の接着強度が
著しく低下する。このようなことは多層回路基板の層間
接続にはあってはならないことである。したがって、現
在では、CrO3を粗化処理を行う場合には、ビア接続
強度の低下を抑えるため、ビア底の配線表面に針状のめ
っきを行っている。この針状めっきの針高さは2〜3μ
mあるが、それでもKMnO4を用いた粗化処理の場合
の接続強度の半分位しか強度が得られていない。また、
配線の微細化が進むにつれて、上記針状のめっきでは、
配線の密なところで短絡が発生し使用できなくなる。
Here, in a resin using CrO 3 for the roughening treatment, a chromate film of CrO 3 is formed on the Cu surface which becomes the via connection interface together with the roughening of the resin surface. Even if plating is performed on Cu on which a chromate film has been formed, metal-to-metal bonding cannot be performed, so that the adhesive strength of the plating layer is significantly reduced. This must not be the case for the interlayer connection of the multilayer circuit board. Therefore, at present, when performing roughening treatment on CrO 3 , needle-like plating is performed on the wiring surface at the bottom of the via in order to suppress a decrease in via connection strength. The needle height of this needle plating is 2-3μ
m, but still only about half the connection strength in the case of the roughening treatment using KMnO 4 . Also,
As the miniaturization of wiring progresses, in the needle-shaped plating,
A short circuit occurs in a dense wiring, and it cannot be used.

【0005】[0005]

【発明が解決しようとする課題】本発明は、クロム酸で
粗化処理を行う樹脂材料を使用したビルトアップ多層基
板の製造において、ビア接続信頼性に優れた製造法を提
供するものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a built-up multilayer board using a resin material subjected to a roughening treatment with chromic acid and having excellent via connection reliability.

【0006】[0006]

【課題を解決するための手段】本発明は、樹脂基板表面
をクロム酸により粗化処理すると共に、ビア底部の配線
表面に生成したクロメート皮膜を除去する処理を行い、
ビア接続強度を上昇させて、基板を多層にビルトアップ
することを特徴とするビルトアップ多層基板の製造法で
ある。
According to the present invention, a surface of a resin substrate is roughened with chromic acid, and a chromate film formed on a wiring surface at the bottom of a via is removed.
A method for manufacturing a built-up multilayer substrate, characterized in that a via connection strength is increased to build up a substrate in multiple layers.

【0007】本発明の対象となるビルトアップ多層基板
の製造法において、回路形成法はサブトラクティブ、セ
ミアディティブ、フルアディティブ法のいずれの手法で
も可能であるが、ここではセミアディティブ法について
説明する。それは下記の各工程よりなる。
In the method of manufacturing a built-up multilayer substrate to which the present invention is applied, a circuit forming method can be any of a subtractive, semi-additive and full-additive method. Here, the semi-additive method will be described. It consists of the following steps.

【0008】(1)基板1上にCu導体回路2を形成す
る。化学Cuメッキ3を行い、感光性のめっきレジスト
を用いてパターン電解Cuめっき4を行う。めっきレジ
スト剥離後、エッチングにより配線間の化学Cu膜を除
去して回路を形成する(図1参照)。
(1) A Cu conductor circuit 2 is formed on a substrate 1. Chemical Cu plating 3 is performed, and pattern electrolytic Cu plating 4 is performed using a photosensitive plating resist. After removing the plating resist, the chemical Cu film between the wirings is removed by etching to form a circuit (see FIG. 1).

【0009】(2)形成したCu回路導体表面をエッチ
ング処理または針状等の表面粗化処理5を行う(コア基
板上のCu導体回路完成)。クロム酸に対する金属保護
膜を形成してもかまわない(図2参照)。
(2) The surface of the formed Cu circuit conductor is subjected to a surface roughening treatment 5 such as an etching process or a needle-like process (the completion of the Cu conductor circuit on the core substrate). A metal protective film for chromic acid may be formed (see FIG. 2).

【0010】(3)次にビルトアップ絶縁樹脂6を形成
する。樹脂形成方法は、液状樹脂の塗布、樹脂シートの
ラミネートのいずれの手法でもよい(図3参照)。
(3) Next, a built-up insulating resin 6 is formed. The resin forming method may be any method of applying a liquid resin or laminating a resin sheet (see FIG. 3).

【0011】(4)絶縁樹脂6の所定の位置に層間接続
用のビアホール7を形成する。感光性樹脂を使用したフ
ォトビア法、熱硬化性樹脂を使用したレーザービア法の
いずれの手法でもよい(図4参照)。
(4) A via hole 7 for interlayer connection is formed at a predetermined position of the insulating resin 6. Either a photo via method using a photosensitive resin or a laser via method using a thermosetting resin may be used (see FIG. 4).

【0012】(5)樹脂表面6をクロム酸で粗化処理す
る。この際、ビアホール7底の金属表面にクロメート皮
膜8が形成される(図5参照)。
(5) The resin surface 6 is roughened with chromic acid. At this time, a chromate film 8 is formed on the metal surface at the bottom of the via hole 7 (see FIG. 5).

【0013】(6)クロメート皮膜8を除去する。クロ
メート皮膜を除去する処理は、プラズマアッシング、グ
ルコン酸ソーダーが考えられる。また、クロメート皮膜
が形成された金属を溶かすエッチング液を用いることも
できる。例えば、Cuの場合、過硫酸ソーダ/硫酸、過
酸化水素/硫酸のエッチング液が考えられる(図6参
照)。
(6) The chromate film 8 is removed. Plasma ashing and sodium gluconate can be considered as the treatment for removing the chromate film. Further, an etchant for dissolving the metal on which the chromate film has been formed can also be used. For example, in the case of Cu, an etching solution of sodium persulfate / sulfuric acid and hydrogen peroxide / sulfuric acid can be considered (see FIG. 6).

【0014】(7)クロム酸で粗化した樹脂表面6に化
学メッキ処理9をする(図7参照)。
(7) Chemical plating 9 is applied to the resin surface 6 roughened with chromic acid (see FIG. 7).

【0015】(8)前記(2)と同様の手法でCu導体
回路を形成する。
(8) A Cu conductor circuit is formed in the same manner as in the above (2).

【0016】(9)形成したCu回路導体表面をエッチ
ング処理等の表面粗化処理または針状等の表面粗化処理
を行う。クロム酸に対する金属保護皮膜を形成してもよ
い(2層目のCu導体回路完成)。
(9) The surface of the formed Cu circuit conductor is subjected to a surface roughening treatment such as an etching treatment or a surface roughening treatment such as a needle shape. A metal protective film for chromic acid may be formed (the second-layer Cu conductor circuit is completed).

【0017】(10)以降、ビルトアップを継続する場
合には、上記(4)〜(9)の工程を繰り返し行う。
After (10), if the build-up is to be continued, the above steps (4) to (9) are repeated.

【0018】本発明によれば、樹脂基板表面をクロム酸
をもって粗化処理することによって、層間の絶縁樹脂と
導体との密着信頼性を確保するとともに、同時にビアホ
ール底の金属表面に生成するクロメート膜を除去するこ
とによって、該面の金属間結合を確実にしてビア接続信
頼性に優れたものとすることができる。
According to the present invention, the surface of the resin substrate is roughened with chromic acid to ensure the reliability of adhesion between the interlayer insulating resin and the conductor, and at the same time, the chromate film formed on the metal surface at the bottom of the via hole By removing, the metal-to-metal coupling on the surface can be ensured and the via connection reliability can be improved.

【0019】[0019]

【発明の実施の形態】本発明の実施例並びに比較例に基
づいて本発明を具体的に説明する。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be specifically described based on examples of the present invention and comparative examples.

【0020】表1に各例の処理内容を示す。Cu配線表
面をエッチングにより粗化するにはメック社のCZ処理
を施した。また、配線の電解Cuめっきにはリーロナル
社のカパーグリームST−901を添加剤として用い
た。このめっき液を用いるとクロム酸に対してクロメー
ト膜生成により耐食性を有するようになる。
Table 1 shows the processing contents of each example. In order to roughen the surface of the Cu wiring by etching, a CZ treatment of Mec was applied. In addition, Copper Glyme ST-901 manufactured by Relonal was used as an additive for electrolytic Cu plating of the wiring. When this plating solution is used, a chromate film is formed against chromic acid to have corrosion resistance.

【0021】[0021]

【表1】 [Table 1]

【0022】実施例1では過硫酸ソーダ100g/L+
硫酸50ml/Lのエッチング液を室温2分浸漬にて使
用した。実施例2では日本マクダーミット社製の過酸化
水素−硫酸系エッチング液のメテックスG−5Sを42
℃、30秒浸漬にて使用した。実施例3では5%グルコ
ン酸ソーダ+10%NaOH溶液を35℃、5分浸漬に
て処理を施した。実施例4ではO2プラズマ(4000
W、250mTorr、O2ガス、処理時間3分)にて
クロメート膜除去を行った。比較例1ではクロメート除
去は一切行わない。比較例2は過マンガン酸を使用して
いるプロセスなので、クロメート皮膜は形成されない場
合である。
In Example 1, sodium persulfate 100 g / L +
An etching solution of 50 ml / L of sulfuric acid was used by immersion for 2 minutes at room temperature. In Example 2, a hydrogen peroxide-sulfuric acid-based etching solution Metex G-5S manufactured by McDermitt Japan was used for 42 times.
It was used by immersion at 30 ° C. for 30 seconds. In Example 3, treatment was performed by immersing a 5% sodium gluconate + 10% NaOH solution at 35 ° C. for 5 minutes. In the fourth embodiment, the O 2 plasma (4000
W, 250 mTorr, O 2 gas, processing time 3 minutes) to remove the chromate film. In Comparative Example 1, no chromate was removed. Comparative Example 2 is a process in which permanganic acid is used, so that no chromate film is formed.

【0023】表1の処理を施したパッケージのビアシェ
ア強度を表2に示す。ビアシェアはO2プラズマアッシ
ングにより絶縁層である樹脂を除去し、ビアを剥き出し
状態にしてから行った。破壊モードとしてはビアが接合
界面から剥離したものをL、接合界面から剥離せずシェ
アによりビアが変形したものをWとして表示した。Wと
表示したものは表示された強度よりも界面強度が大きい
と予測される。
Table 2 shows the via shear strength of the package subjected to the processing of Table 1. The via shear was performed after removing the resin as an insulating layer by O 2 plasma ashing to expose the via. As the destruction mode, L indicates that the via peeled off from the bonding interface, and W indicates that the via deformed due to shear without separating from the bonding interface. Those indicated as W are predicted to have higher interface strength than the displayed strength.

【0024】[0024]

【表2】 [Table 2]

【0025】比較例1ではクロメート皮膜除去は行われ
ていない。このときのシェア強度はほとんどのビアで測
定不能で0gであった。触れた時点で剥がれる状態であ
る。比較例2は過マンガン酸処理により樹脂を粗化して
いるため、クロメート皮膜は形成されていない。シェア
強度も大きく、破壊モードはすべてWである。ビアが変
形しているだけで、ビア接続部での剥離はない。比較例
1と2からクロム酸処理によるクロメート皮膜がビア接
続強度に大きく影響していることが明らかである。実施
例1〜4では、クロメート除去により比較例2と同等の
強度を有している。ビアは変形のみで、ビア接続部での
剥離はみられない。完全にクロメート皮膜の除去ができ
たものと認められる。
In Comparative Example 1, the chromate film was not removed. At this time, the shear strength was 0 g, which could not be measured in most vias. It is in a state where it comes off when touched. In Comparative Example 2, the resin was roughened by the permanganic acid treatment, and thus no chromate film was formed. The shear strength is large, and all the destruction modes are W. Only the via is deformed, and there is no peeling at the via connection portion. From Comparative Examples 1 and 2, it is clear that the chromate film obtained by the chromic acid treatment greatly affects the via connection strength. Examples 1 to 4 have the same strength as Comparative Example 2 due to chromate removal. The via is only deformed, and no peeling at the via connection portion is observed. It is recognized that the chromate film was completely removed.

【0026】[0026]

【発明の効果】本発明によればクロム酸による粗化処置
により、多層基板同士の接合面並びにビア接続界面にお
ける金属結合を確実にさせ、ビア接続強度を上昇させ、
信頼性に優れたビア接続を可能にし、しかもそのことが
容易に実現できる製造法が得られる。
According to the present invention, the roughening treatment with chromic acid ensures the metal bonding at the joint surface between the multilayer substrates and the via connection interface, and increases the via connection strength.
A manufacturing method that enables via connection with excellent reliability and that can be easily realized is obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】回路形成までの説明図である。FIG. 1 is an explanatory diagram up to the formation of a circuit.

【図2】回路導体表面の粗化処理の説明図である。FIG. 2 is an explanatory diagram of a roughening treatment of a circuit conductor surface.

【図3】絶縁樹脂形成の説明図である。FIG. 3 is an explanatory diagram of formation of an insulating resin.

【図4】ビアホール形成の説明図である。FIG. 4 is an explanatory diagram of via hole formation.

【図5】ビアホール部の拡大図で粗化処理の説明図であ
る。
FIG. 5 is an enlarged view of a via hole and is an explanatory diagram of a roughening process.

【図6】クロメート皮膜除去の説明図である。FIG. 6 is an explanatory diagram of chromate film removal.

【図7】化学メッキ処理の説明図である。FIG. 7 is an explanatory diagram of a chemical plating process.

【符号の説明】[Explanation of symbols]

1 基板 2 Cu導体回路 3 化学Cuメッキ 4 電解Cuメッキ 5 表面粗化処理 6 絶縁樹脂 7 ビアホール 8 クロメート皮膜 9 化学メッキ処理 Reference Signs List 1 substrate 2 Cu conductor circuit 3 chemical Cu plating 4 electrolytic Cu plating 5 surface roughening treatment 6 insulating resin 7 via hole 8 chromate film 9 chemical plating treatment

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 樹脂基板表面をクロム酸により粗化処理
すると共に、ビア底部の配線表面に生成したクロメート
皮膜を除去する処理を行い、ビア接続強度を上昇させ
て、基板を多層にビルトアップすることを特徴とするビ
ルトアップ多層基板の製造法。
1. A surface of a resin substrate is roughened with chromic acid, and a process of removing a chromate film formed on a wiring surface at a bottom portion of a via is performed to increase a via connection strength and build up a multilayer substrate. A method for manufacturing a built-up multilayer substrate, characterized by comprising:
【請求項2】 クロメート皮膜を除去するための処理は
エッチングまたはプラズマアッシングによる請求項1記
載のビルトアップ多層基板の製造法。
2. The method for manufacturing a built-up multilayer substrate according to claim 1, wherein the process for removing the chromate film is etching or plasma ashing.
JP29538199A 1999-10-18 1999-10-18 Method for manufacturing built-up multi-layered board Pending JP2001118950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29538199A JP2001118950A (en) 1999-10-18 1999-10-18 Method for manufacturing built-up multi-layered board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29538199A JP2001118950A (en) 1999-10-18 1999-10-18 Method for manufacturing built-up multi-layered board

Publications (1)

Publication Number Publication Date
JP2001118950A true JP2001118950A (en) 2001-04-27

Family

ID=17819903

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29538199A Pending JP2001118950A (en) 1999-10-18 1999-10-18 Method for manufacturing built-up multi-layered board

Country Status (1)

Country Link
JP (1) JP2001118950A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003100850A1 (en) * 2002-05-28 2003-12-04 Hitachi Chemical Co., Ltd. Substrate, wiring board, semiconductor package-use substrate, semiconductor package and production methods for them

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003100850A1 (en) * 2002-05-28 2003-12-04 Hitachi Chemical Co., Ltd. Substrate, wiring board, semiconductor package-use substrate, semiconductor package and production methods for them

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