JP2001118397A - Semiconductor storage device - Google Patents

Abstract

(57) Abstract: Provided is a semiconductor memory device capable of suppressing an increase in layout area and increasing initial fault screening efficiency when performing initial fault screening in a test mode. A test mode detection circuit for detecting a test mode, and a memory cell in which a storage node of a dummy region arranged in a memory cell array is short-circuited to each potential line for supplying a power supply voltage and a ground voltage, Either activate the word line in the dummy area to determine the bit line, or use an equalizing transistor inside the sense amplifier to equalize the bit line, and alternately determine each bit line to the ground voltage and power supply voltage. As a result, stress is applied between the bit lines, and a plurality of outputs of the predecode circuit are activated in the row direction in the test mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a test mode in which a test potential is supplied to a memory cell array to test the quality of the test.

[0002]

2. Description of the Related Art Conventionally, a semiconductor memory device widely used as a memory element of a computer system connected to home appliances, OA equipment, industrial equipment, and the like includes:
A memory cell array in which a plurality of memory cells are arranged in a matrix, a word line for driving a memory cell corresponding to each row of the memory cells, and a potential stored in a memory cell corresponding to each column to a sense amplifier. Bit lines associated with each other are formed so as to be connected to each other, and a test mode is provided for supplying a test potential to the memory cell array to test the memory cells.

An example of a semiconductor memory device having such a test mode and configured for the purpose of improving the reliability of the device is disclosed in, for example, JP-A-10-340598. FIG. 7 is a schematic configuration diagram of a stress accelerating means in a conventional semiconductor memory device.
In FIG. 7, 1 equalizes the bit lines BL1 and BL2 of the memory cell array to the power supply voltage or the ground voltage in the test mode of the semiconductor memory device.
At the time of normal operation, this is an equalizing level generating circuit that is arranged around a memory cell of a chip and generates an equalizing level (equalizing potential) for the purpose of equalizing to a half level of the power supply voltage. Reference numeral 2 denotes a row decoder, in which an equalizing potential line receiving an equalizing level generated by the equalizing level generating circuit 1 is routed.
Reference numerals 3 and 4 denote sense amplifier arrays, which include equalizing transistors for supplying the equalizing potential generated by the equalizing level generating circuit 1 to equalize the bit lines BL1 and BL2.

In the conventional semiconductor memory device configured as described above, when the test mode detecting circuit for detecting the test mode detects the test mode, the transistors TE1, TE2, TE3 in the equalize level generating circuit 1
And TE4, the potential VBL is applied to the bit lines BL1 and BL2 from the periphery of the chip toward the inside of the core.
1, a ground potential and a power supply potential are supplied as VBL2, and reliability is accelerated between the bit lines BL1 and BL2. On the other hand, in the case of the normal mode other than the test mode, by controlling the control line #n, the bit line B
An intermediate potential is supplied to L1 and BL2 from the intermediate potential generation circuit as potentials VBL1 and VBL2.

[0005]

However, in the conventional semiconductor memory device as described above, in the test mode, the ground potential and the power supply potential are supplied to the bit lines to accelerate the reliability between the bit lines. And for that,
It is necessary to provide two equalizing potential lines in the row decoder 2 for the test mode, and there is a problem that a transistor size in a peripheral circuit increases and a layout area increases.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and provides a semiconductor memory device capable of reducing an increase in layout area for a circuit configuration and achieving higher reliability acceleration in a test mode. provide.

[0007]

In order to solve the above-mentioned problems, a semiconductor memory device according to the present invention comprises a test mode detecting circuit for detecting a test mode, and an equalizing potential generating circuit when a test detection signal is not output. By providing an equalizing potential, stopping the supply of the equalizing potential when the test detection signal is output, and providing an equalizing potential switching circuit for switching to a power supply voltage or a ground voltage and a bit line of the memory cell array around the sense amplifier, It is possible to alternately switch between the supply of the ground voltage and the supply of the power supply voltage to the bit line, and furthermore, by arranging this equalizing potential switching circuit around the sense amplifier row, it is possible to suppress an increase in the transistor size and the equalizing potential line. It is characterized by doing.

As described above, the increase in the layout area for the circuit configuration can be reduced, and in the test mode, the screening efficiency at the time of performing the initial failure screening in the test mode can be increased, and higher reliability can be accelerated. Obtainable.

[0009]

A semiconductor memory device according to a first aspect of the present invention includes a memory cell array in which a plurality of memory cells are arranged in a matrix, and a memory cell corresponding to each row among the plurality of memory cells. A word line to be driven and a bit line associated to connect a potential stored in a memory cell corresponding to each column among the plurality of memory cells to a sense amplifier are formed.
What is claimed is: 1. A semiconductor memory device having a test mode for testing a pass / fail by supplying a test potential, wherein a test mode detection circuit for detecting the test mode and outputting a test detection signal, and equalizing the memory cell array to the bit line. An equalizing circuit for receiving an equalizing start signal for starting and supplying an equalizing potential for the equalizing, an equalizing potential generating circuit for generating the equalizing potential, and an output state of a test detection signal from the test mode detecting circuit Controlling an equalizing potential switching circuit for switching the equalizing potential and the test potential to supply the bit line to the bit line, and controlling the switching of the equalizing potential switching circuit to control the potential supply to the bit line. A control circuit for controlling the equalization potential The equalizing potential is supplied from the equalizing potential generating circuit to the bit line when the test detection signal is not output, and the supply of the equalizing potential from the equalizing potential generating circuit is stopped when the test detecting signal is output. The equalizing potential switching circuit is configured to supply the test potential and alternately supply different potentials to the bit lines.

According to this structure, it is possible to alternately switch the bit line to each of the ground voltage and the power supply voltage. By arranging the equalizing potential switching circuit around the sense amplifier array, the transistor size and the equalizing potential can be changed. Suppress line growth. According to a second aspect of the present invention, the semiconductor memory device includes a dummy region of the memory cell array as a test potential supply unit that is supplied to a bit line connected to the memory cell array according to the first embodiment through an equalizing potential switching circuit. Placed, and the storage node of that area,
Alternately, short-circuit the dummy cell array to the power supply line supplying the ground voltage and the power supply line supplying the power supply voltage, and equalize from the equalize potential generation circuit when the test detection signal is output from the test mode detection circuit. A control circuit for stopping the supply of the potential to the bit lines of the dummy cell array and driving the word lines of the dummy cell array is provided.

According to this configuration, the word line in the dummy area is driven from the output result of the test mode detection circuit to fix the bit line to each of the power supply voltage or the ground voltage, and to use the existing dummy cell array. This completely reduces the layout area involved. According to a third aspect of the present invention, there is provided a semiconductor memory device including a word line selecting circuit for physically selecting the word line according to the first or second aspect, wherein the word line selecting circuit detects a test from a test mode detecting circuit. Only when outputting a signal, a plurality of word lines are selected so as to be physically alternated, and different potentials are alternately supplied to the word lines.

According to this structure, the means for selecting the word line in the dummy area sets the word line corresponding to each column of the memory cell array in accordance with the output signal of the test mode detection circuit.
Only in the test mode, a plurality of the word lines are selected so that the physical selection is alternated, the potential of one word line is the ground voltage, and the potential of the other word line is boosted to the word line drive level. .

According to a fourth aspect of the present invention, in the semiconductor memory device according to the third aspect, when a test detection signal is output from the test mode detection circuit according to the third aspect, boosting by a supply potential to the word line selected by the word line selection circuit is started. As soon as possible, a means for boosting the word line in the dummy region and activating the sense amplifier when boosting the word line in the dummy region is provided.

According to this configuration, the means for raising the word line in the dummy area raises the word line earlier than the timing for starting the boosting of the word line for driving the memory cell in the test mode, and By activating the sense amplifier when boosting the line, the potential of the bit line is further stabilized, and the acceleration of reliability is improved. According to a fifth aspect of the present invention, there is provided a semiconductor memory device.
When a test detection signal is output from the test mode detection circuit according to any one of the above, the sense amplifier is held in an equalized state.

According to this configuration, the means for maintaining the equalized state can maintain the equalized state without activating the sense amplifier in the test mode. According to a sixth aspect of the present invention, when a test detection signal is output from the test mode detection circuit according to any one of the first to fifth aspects, a plurality of bits of an address corresponding to the word line selection circuit are selected. The state is set, and only the remaining bits are input to the word line selection circuit to arbitrarily perform multiple selection.

According to this configuration, the word line multiple selection means is realized by selecting a plurality of bits of the input address of the word line selection circuit and inputting only the lower bits arbitrarily selected to the word line selection circuit. Thus, the layout area can be suppressed, and the word line having the same logical address is physically separated by decoding the word line selection signal from the input address.

According to a seventh aspect of the present invention, there is provided a semiconductor memory device according to any one of the first to sixth aspects, further comprising: a charge storage element connected to a precharge power supply wiring;
A first transfer element connected between the charge storage element and a first bit line associated with the memory cell to transfer charges; and a second transfer element associated with the charge storage element and the memory cell. A second transfer element connected between the first and second bit lines and a second transfer element for transferring a charge, wherein when a test detection signal is output from the test mode detection circuit, a first sense amplifier row of the sense amplifiers and a second Each supply potential for the first bit line and the second bit line in the first memory cell block sandwiched between the sense amplifier rows is set to a different voltage level.

According to this configuration, for the memory cell, the charge storage element connected to the precharge power supply line and the first transfer connected between the charge storage element and the first bit line for transferring the charge. An element, and a second transfer element connected between the charge storage element and the second bit line for transferring electric charges, and are interposed between the first sense amplifier row and the second sense amplifier row. By alternately supplying the power supply voltage and the ground voltage to the first bit line and the second bit line in the first memory cell block, the voltage supplied to the sense amplifier in the test mode The level is made different between the first sense amplifier row and the second sense amplifier row to enable stress application.

In the semiconductor memory device according to the present invention, the word line of the dummy region according to the present invention is arranged so as to be sandwiched between the first sense amplifier row and the second sense amplifier row. The storage nodes connected to the word line of the dummy region among the storage nodes are alternately
The power supply line supplying the ground voltage and the power supply line supplying the power supply voltage are short-circuited.

According to this configuration, the first sense amplifier row and the second sense amplifier row are interposed between the first sense amplifier row and the second sense amplifier row so that the potentials of the ground voltage and the power supply voltage can be alternately supplied to the bit lines of the memory cells. A storage node in a memory cell connected to a word line in the dummy region is short-circuited to a ground voltage or a power supply voltage. According to a ninth aspect of the present invention, the memory cell according to the eighth aspect is configured such that the word line selection circuit physically alternates the word lines in the dummy area only when the test mode detection circuit outputs the test detection signal. It is configured to be selected as follows.

According to a tenth aspect of the present invention, when a test detection signal is output from the test mode detection circuit according to any one of the first, second, or fourth to ninth aspects, a semiconductor memory device according to an input address is used. And means for changing the selection of a plurality of word lines. According to this configuration, the word line selection signal is decoded from the input address, and the word lines having the same logical address are physically separated.

In the semiconductor memory device according to the present invention, when a test detection signal is output from the test mode detection circuit according to any one of the first, second, or fourth to tenth aspects, a plurality of words are output. A configuration is provided that includes means for executing selection of a line based on the count value of a refresh counter provided therein. According to this configuration, when stress is applied without applying an input address, stress applying is performed by providing a means for variably selecting a word line by a refresh counter provided therein. .

Hereinafter, a semiconductor memory device according to an embodiment of the present invention will be specifically described with reference to the drawings. (Embodiment 1) A semiconductor memory device according to Embodiment 1 of the present invention will be described. FIG. 1 is a block diagram showing a schematic configuration of the semiconductor memory device according to the first embodiment. As shown in FIG. 1, a test mode detecting circuit 7 for detecting a test mode is provided, and drives a memory cell array 12 in which a plurality of memory cells are arranged in a matrix and memory cells corresponding to each row of the memory cell array 12. The potential stored in the word line 13 and the memory cell corresponding to each column is applied to the sense amplifier P output terminal (SAP) 8 and the sense amplifier N output terminal (SA).
N) A bit line 14 associated with the sense amplifier SA1 having each output terminal 9 and an equalizing circuit 15 arranged around the sense amplifier SA1 for equalizing the bit line 14 with an equalizing start signal EQ.
And an equalizing potential generating circuit (not shown) for supplying the equalizing potential VBP, and supplying the equalizing potential VBP from the equalizing potential generating circuit during normal operation when the test mode detection circuit 7 does not output the test detection signal TE. In the test mode when the test detection signal TE is output, the equalizing potential VBP from the equalizing potential generating circuit is output.
, The equalizing potential switching circuit 5, which supplies the power supply voltage or the ground voltage supplied to the storage device,
6.

In such a semiconductor memory device, when the test mode detection circuit 7 detects the test mode, the output TE of the test mode detection circuit 7 reaches a high level, which is input to the predecode circuit 11 as a test detection signal. . The test detection signal TE is also input to the equalizing potential switching circuits 5 and 6 to stop the supply of the equalizing potential VBP used in the normal state, and determine the predetermined power supply voltage or ground voltage from the output result of the predecoding circuit 11. Are supplied to the equalizing circuit 15 as the equalizing level of the bit line 14, and the potentials of the ground voltage and the power supply voltage are supplied to the bit line 14 so as to be physically alternated. (Second Embodiment) A semiconductor memory device according to a second embodiment of the present invention will be described.

FIG. 2 is a block diagram showing a schematic configuration of the semiconductor memory device according to the second embodiment. In FIG. 2, means for alternately supplying the potential of the bit line 14 using the ground voltage and the power supply voltage is used to connect the storage nodes of the dummy cells 22 and 23 which are the memory cell arrays arranged in the dummy region in the memory cell array to the ground voltage. And the power supply line supplying the power supply voltage, and the dummy word lines 20 and 21 are driven based on the output result of the test mode detection circuit, so that the bit line 1
4 can be fixed to each of the power supply voltage and the ground voltage.

Further, as these memory cell arrays,
Since an existing dummy cell array is used, it is not necessary to form a new memory cell array region, an increase in layout area due to the formation of the memory cell array region can be suppressed, and a potential difference can be alternately applied to the bit lines 14. it can. Here, the predecode circuit 1 in the semiconductor memory device according to the first and second embodiments is described.
1 will be described.

FIG. 3 is a configuration diagram of the predecode circuit 11 in the semiconductor memory devices according to the first and second embodiments. As shown in FIG. 3, the predecode circuit 11 includes outputs ADDEXT and XA of a predecode signal generation circuit for selecting a word line connected to each memory cell.
NOR is applied to each of DDEXT and test detection signal TE.
The element 24 and the element 25 are connected.

According to this configuration, when the test detection signal TE from the test mode detection circuit 7 is at a low level, that is, during normal operation, signals generated in accordance with ADDEXT and XADDEXT are output as they are as PADD and PXADD. Test detection signal T from
When E is at the high level, that is, in the test mode, the PAD
Both D and PXADD are output at a high level and are multiply selected. Thus, by arranging it before the driver at the final stage of the predecode signal generation circuit, the layout size of the memory cell array and the like can be reduced.
A multiple selection means is obtained.

In the first and second embodiments,
If these predecode signal generating circuits are provided for all input address terminals, multiple word lines can be selected. Also, for example, only the lowest one address is NOR
It is also possible to divide the number of word lines and select them collectively, for example, by performing multiple selection of half of all word lines by using the elements as simple inversion elements.

Further, a sense amplifier control circuit acting on the semiconductor memory device of the first embodiment will be described. FIG. 4 shows a sense amplifier control circuit for activating the sense amplifier SA1 in the semiconductor memory device of the first embodiment. 4, a decoder (NAND element) 27 receives a row address predecode signal PXADD from the predecode circuit 11 shown in FIG. A flip-flop 29 is set in response to a sense amplifier enable signal SE that enables the sense amplifier SA1. The flip-flop 29 receives a signal XTE obtained by inverting the test detection signal TE output from the test mode detection circuit 7, In the test mode, when the signal XTE is at a low level, the operation of the NAND element 28 causes the signal EQ to be fixed at a high level.

During normal operation (XTE = High), the row address predecode signal output from the decoder 27 transitions first, and when both PXADDn and PXADDm are at high level, the signal EQ is generated as low level.
When the sense amplifier enable signal SE changes to low level, the output of the flip-flop 29 changes to high level to disable the sense amplifier SA1, and the signal EQ
Is raised to the high level, and in the test mode, the equalized state is always maintained regardless of how these signals transition.

By doing so, it is possible to perform the equalizing and sensing operations in the normal operation, and to perform only the equalizing operation in the test mode. The difference is whether the element 28 is NAND or The difference is only the difference between the inverters and whether the inverters are used or not. Third Embodiment A semiconductor memory device according to a third embodiment of the present invention will be described.

FIG. 5 is a block diagram showing a schematic configuration of the semiconductor memory device according to the third embodiment. In this semiconductor memory device, as shown in FIG. 5, a predecode circuit 31, a word line 33, a bit line 34, an equalizing circuit 35, equalizing potential switching circuits 36 and 37, and a test mode detecting circuit 38 are respectively shown in FIG. The memory cell array 32 has the same configuration as the predecode circuit 11, the word line 13, the bit line 14, the equalize circuit 15, the equalize potential switching circuits 6, 5, and the test mode detection circuit 7, and the memory cell array 32 includes two transfer elements TS1, TS2 and 1 Read from the storage node by the open bit line 3
4 for reading.

For example, when the bit lines 14 shown in FIG. 1 are physically and alternately fixed to the ground voltage and the power supply voltage, the bit line 34 connected to one transfer element TS1 and the other transfer element TS2 Is equalized in a state where the bit line 34 connected to is inverted. (Fourth Embodiment) A semiconductor memory device according to a fourth embodiment of the present invention will be described.

FIG. 6 is a block diagram showing a schematic configuration of a semiconductor memory device according to the fourth embodiment. In this semiconductor memory device, as shown in FIG. 6, dummy word lines 40 and 43 and bit line 44 are configured similarly to dummy word lines 20 and 21 and bit line 14 shown in FIG. 2, respectively.
Further, similarly to the semiconductor memory device of the third embodiment, a memory cell including two transfer elements and one storage element is used.

In such a semiconductor memory device, the storage node of the memory cell arranged in the dummy region is short-circuited to each of the ground voltage or the power supply voltage, and the dummy word line (WLa) 40 on the dummy region 42 side is set. And the dummy word line (WLb) 43 on the side of the dummy region 45 is raised, and the other dummy word lines are not activated, the potential of the bit line 44 becomes the potential based on the power supply voltage and the ground voltage, In addition, when the combination of the activated word lines is reversed, the bit line 44 can have the opposite potential.

At this time, if only one of the word lines to which a stress is really required is always provided, it is possible to avoid a potential short-circuit at the storage node and to control the manner of applying the potential. In FIG. 8, the refresh counter 50 can be enabled in the test mode for the address generation circuit units ADD1 and ADD2 in the semiconductor memory device of each of the above embodiments, and can be used as an address.

Thus, the test mode detection circuits 7, 3
When the test detection signal TE generated in step 8 is input to the refresh counter 50, the refresh counter 50 operates, and by inputting the output of the refresh counter 50 to the pre-decoding circuit 51, the address generation can be automated. Since most circuits are used in a normal state, the layout area can be reduced.

In each of the above embodiments, examples of the test in the test mode may be a stress application in a burn-in process or a batch write.

[0040]

As described above, according to the present invention, the test mode detecting circuit for detecting the test mode and the equalizing potential from the equalizing potential generating circuit when the test detecting signal is not output are supplied to the test mode detecting circuit. At the time of output, the supply of the equalizing potential is stopped, and an equalizing potential switching circuit for switching to the power supply voltage or the ground voltage and the bit line of the memory cell array are provided around the sense amplifier. It is possible to alternately switch between the supply of voltage and the supply of voltage. Further, by arranging this equalizing potential switching circuit around the sense amplifier array, it is possible to suppress an increase in the transistor size and the equalizing potential line.

Further, stress can be applied between the word lines and the bit lines, and data can be written to the bit lines in the test mode. In addition, the collective writing of data to the bit lines in the test mode can be realized by using existing circuits, avoiding an increase in the number of circuit elements, and without increasing the layout area.

As described above, the increase in the layout area for the circuit configuration can be reduced, and in the test mode, the screening efficiency in performing the initial fault screening in the test mode can be increased, and the higher reliability can be achieved. Can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a semiconductor memory device according to a first embodiment of the present invention;

FIG. 2 is a block diagram illustrating a schematic configuration of a semiconductor memory device according to a second embodiment of the present invention;

FIG. 3 is a schematic diagram of a predecode circuit according to the first and second embodiments of the present invention.

FIG. 4 is a schematic diagram of a sense amplifier control circuit according to the first embodiment of the present invention.

FIG. 5 is a block diagram illustrating a schematic configuration of a semiconductor memory device according to a third embodiment of the present invention;

FIG. 6 is a block diagram illustrating a schematic configuration of a semiconductor memory device according to a fourth embodiment of the present invention;

FIG. 7 is a block diagram showing a configuration of a stress accelerating unit in a conventional semiconductor memory device;

FIG. 8 is a schematic diagram of an address generation circuit unit in each embodiment of the present invention.

[Explanation of symbols]

 11, 51 Predecode circuit 5, 6 Equalize potential switching circuit 13 Word line 14 Bit line 15 Equalize circuit 20, 40, 43 Dummy word line 22, 42, 45 Memory cell array 24, 25 NOR element 26, 28 NAND in dummy area Element 27 Decoder (NAND element) 29 Flip-flop 50 Refresh counter

Claims (11)

[Claims] A memory cell array in which a plurality of memory cells are arranged in a matrix; a word line for driving a memory cell corresponding to each row of the plurality of memory cells; and a column in each of the plurality of memory cells. A semiconductor memory having a test mode in which a test potential is supplied to the memory cell array by forming a test potential by forming a bit line associated with the sense amplifier to connect the potential stored in the corresponding memory cell to the sense amplifier; A test mode detection circuit for detecting the test mode and outputting a test detection signal; and receiving, on the bit line, an equalization activation signal for activating the equalization for the memory cell array, for performing the equalization. An equalizing circuit for supplying an equalizing potential, and an equalizing potential generating circuit for generating the equalizing potential. An equalizing potential switching circuit that switches the equalizing potential and the test potential to the bit line based on an output state of a test detection signal from the test mode detecting circuit, and the switching of the equalizing potential switching circuit. And a control circuit for controlling the supply of a potential to the bit line. The control circuit controls the equalizing potential switching circuit to generate the equalizing potential when the test detection signal is not output to the bit line. An equalizing potential is supplied from a circuit, and when a test detection signal is output, the supply of the equalizing potential from the equalizing potential generating circuit is stopped and the test potential is supplied, so that different potentials are alternately supplied to the bit lines. A semiconductor memory device configured to control the equalizing potential switching circuit. 2. As a means for supplying a test potential supplied through a equalizing potential switching circuit to a bit line connected to a memory cell array, the test node is arranged in a dummy region of the memory cell array, and storage nodes in the region are alternately arranged. A short-circuited dummy cell array in the power supply line supplying the ground voltage and the power supply line supplying the power supply voltage,
And a control circuit for stopping the supply of the equalizing potential from the equalizing potential generating circuit to the bit lines of the dummy cell array and driving the word lines of the dummy cell array when the test mode detecting circuit outputs the test detecting signal. 2. The semiconductor memory device according to claim 1, wherein: 3. A word line selection circuit for physically selecting a word line is provided, and the word line selection circuit is configured to alternate the word lines physically only when a test detection signal is output from a test mode detection circuit. 3. The semiconductor memory device according to claim 1, wherein a plurality of memory cells are selected and different potentials are alternately supplied to the word lines. 4. A method for boosting a word line in a dummy area earlier than the start of boosting by a supply potential to a word line selected by a word line selection circuit when a test detection signal is output from a test mode detection circuit, and 4. The semiconductor memory device according to claim 3, further comprising means for activating a sense amplifier when boosting a word line in the region. 5. The semiconductor memory device according to claim 1, wherein a sense amplifier is held in an equalized state when a test detection signal is output from a test mode detection circuit. 6. When outputting a test detection signal from a test mode detection circuit, a plurality of bits of an address corresponding to a word line selection circuit are selected, and only the remaining bits are input to the word line selection circuit. 6. The semiconductor memory device according to claim 1, wherein a multiple selection is performed. 7. A charge transfer device connected to a precharge power supply line and connected between a charge storage device and a first bit line associated with the memory cell to transfer a charge to a memory cell. And a second transfer element connected between the charge storage element and a second bit line associated with the memory cell to transfer charges, and When the test detection signal is output, the first sense amplifier row of the sense amplifiers and the second
7. The supply potentials for the first bit line and the second bit line in the first memory cell block sandwiched between the sense amplifier columns are set to different voltage levels. The semiconductor memory device according to any one of the above. 8. A word line of a dummy area is arranged between a first sense amplifier row and a second sense amplifier row, and a memory cell is stored in a word of the dummy area among the storage nodes. The storage nodes connected to the line alternately
8. The semiconductor memory device according to claim 7, wherein a short circuit is provided between a power supply line supplying a ground voltage and a power supply line supplying a power supply voltage. 9. The memory cell according to claim 1, wherein the word line selection circuit selects the word lines of the dummy area so as to be physically alternated only when the test mode detection circuit outputs the test detection signal. 9. The semiconductor memory device according to claim 8, wherein: 10. The apparatus according to claim 1, further comprising means for changing selection of a plurality of word lines according to an input address when a test detection signal is output from the test mode detection circuit. 10. The semiconductor memory device according to claim 1. 11. A system according to claim 1, further comprising means for selecting a plurality of word lines based on a count value of a refresh counter provided therein when the test detection signal is output from the test mode detection circuit. 11. The semiconductor memory device according to claim 1, 2 or 4 to 10.