JP2001111641A - Demodulator of sub-synchronous detection system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a demodulator that can conduct proper demodulation independently of a phase difference between a carrier of an input signal and an oscillation signal in the inside of the demodulator. SOLUTION: This demodulator is provided with an error detector 10 that detects a phase difference between the carrier of the input signal and the oscillated signal from the local oscillator 3, an NCO 12 that outputs an AGC stop signal to an AGC 7 when the phase difference detected by the error detector 10 is a phase difference causing malfunction to the AGC 7, and the AGC 7 that amplifies an Ich1 and a Qch1 with a multiple factor just before receiving the AGC stop signal in the case of receiving the AGC stop signal from the NCO 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a quasi-synchronous detection system capable of performing a normal demodulation operation regardless of a frequency difference and a phase difference between a carrier wave of an input modulated wave signal and an oscillation signal of a local oscillator inside a demodulator. It relates to a demodulator.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a configuration of a conventional quasi-synchronous detection type demodulator. The demodulator using the quasi-synchronous detection method shown in FIG. 7 includes multipliers 1 and 2, a local oscillator 3, a π / 2 phase shifter 4, A / D converters (A / D converters) 5, 6, and AGC (automatic amplitude correction circuit) 10
7, a complex multiplier 8, an AGC 9, and an error detector 10
And an NCO (Numerically Controlled Oscillator) 112.

FIG. 8 is a block diagram showing an internal configuration of AGC 107 shown in FIG. AGC 107 shown in FIG.
Is composed of a multiplier 20, absolute value calculators 21 and 22, an adder 23, and an averaging circuit 124.

Hereinafter, the operation will be described. The IF input signal is a multi-level quadrature modulation signal. For example, QPSK. The local oscillator 3 oscillates at substantially the same frequency as the carrier frequency of the IF input signal. The local oscillator 3 outputs the oscillation signal to the multiplier 1 and the π / 2 phase shifter 4. The π / 2 phase shifter 4 shifts the phase of the oscillation signal of the local oscillator 3 by π / 2, and outputs the shifted signal to the multiplier 2.

[0005] The multiplier 1 extracts an in-phase signal Ich0, which is an in-phase component of the IF input signal. On the other hand, the multiplier 2
An orthogonal signal Qch0, which is an orthogonal component of the F input signal, is extracted. Then, the in-phase signal Ich0 and the quadrature signal Qch0
Are input to AD converters 5 and 6, respectively.
A / D converters 5 and 6 convert in-phase signal Ich0 and quadrature signal Qch0 into digital in-phase signal Ic, respectively.
h1 and a digital quadrature signal Qch1. Then, digital in-phase signal Ich1 and digital quadrature signal Qch1 are output to AGC 107.

In the quasi-synchronous detection system, synchronous detection is performed using an oscillation signal independent of a carrier. Therefore, the digital in-phase signal Ich1 and the digital quadrature signal Qch1 include the carrier frequency of the IF input signal and the local oscillator 3 The influence of the difference between the oscillation frequency and the phase difference between the two signals is included.

[0007] Before removing these effects, it is necessary to match the amplitude levels of the digital in-phase signal Ich1 and the digital quadrature signal Qch1. Therefore, the digital in-phase signal Ich1 and the digital quadrature signal Qch1 are input to the AGC 107.

In the AGC 107, the digital in-phase signal I
ch1 is input to the absolute value calculator 21 and the digital quadrature signal Qch1 is input to the absolute value calculator 22. The absolute value calculator 21 calculates the absolute value of the amplitude of the digital in-phase signal Ich1, and outputs a value obtained by multiplying the value by −1 to the adder 23. On the other hand, the absolute value calculator 22 calculates the absolute value of the amplitude of the digital quadrature signal Qch1 and outputs it to the adder 23.

An adder 23 adds the outputs of the absolute value calculators 21 and 22 and outputs the result to an averaging circuit 124. The averaging circuit 124 averages the output from the adder 23. Then, the averaging circuit 124 calculates an amplitude correction multiplier, which is a multiplier for amplitude correction, based on the averaged value, and outputs the multiplier to the multiplier 20. The multiplier 20 amplifies the digital in-phase signal Ich1 according to the amplitude correction multiplier. Where A
The output of the GC 107 is output to the signal Ich2 and the signal Qch.
Let it be 2.

As described above, AGC 107 adjusts the amplitude levels of digital in-phase signal Ich1 and digital quadrature signal Qch1 to obtain signal Ich2 and signal Qc.
Output to the complex multiplier 8 as h2. The complex multiplier 8
The signal Ich3 and the signal Qch3 are output to the AGC 9 from which the difference between the carrier frequency of the IF input signal included in the signal Ich2 and the signal Qch2 and the oscillation frequency of the local oscillator 3 and the influence of both phase differences have been removed. AGC 9
A signal Ich4 and a signal Qch4 expressing the signal Ich3 and the signal Qch3 at regular signal levels are output.

In general, since the carrier frequency of the IF input signal does not match the oscillation frequency of the local oscillator 3,
The signal point positions of the signal Ich4 and the signal Qch4 are shifted from their normal positions. Therefore, the error detector 10 detects a shift related to the phase of the signal point positions of the signals Ich4 and Qch4 from the normal signal point position, and outputs an error signal indicating the shift amount to the complex multiplier 8. Also, the signals Ich4, Qc
A deviation of the amplitude level of h4 from the normal signal level is detected, and an error signal indicating a deviation amount related to the amplitude is output to the AGC 9. The AGC 9 adjusts the signal Ich3 and the signal Qch3 in the amplitude direction based on the error signal from the error detector 10.

[0012]

However, in the demodulator using the conventional quasi-synchronous detection method, when the phase difference between the carrier of the IF input signal and the oscillation signal of the local oscillator 3 has a specific value, the AGC 107 has a sufficient value. The gain could not be adjusted. For example, the amplitude of the digital in-phase signal Ich1 is a / 2, and the amplitude of the digital quadrature signal Qch1 is a.

If the carrier frequency of the IF input signal and the frequency of the oscillation signal of the local oscillator 3 are equal and their phases are also equal, the signal space diagram of the digital synchronization signal Ich1 and the digital quadrature signal Qch1 is shown in FIG. As shown. Since there is no phase difference between the carrier of the IF input signal and the oscillation signal of the local oscillator, the magnitude of the amplitude of the digital in-phase signal Ich1 becomes | a / 2 |
Becomes Similarly, the magnitude of the digital quadrature signal Qch1 is | a |.

In the AGC 107 shown in FIG. 8, the output of the absolute value calculator 21 is | a / 2 |. Similarly, the output of the absolute value calculator 22 is | a |. Then, the output of the adder 23 is | a / 2 |. Averaging circuit 12
4 calculates the amplitude correction multiplication factor 2.0 from the output (| a / 2 |) from the adder 23 and outputs the value to the multiplier 22. The multiplier 22 amplifies the amplitude level of the digital in-phase signal Ich1 to 2.0 times. Therefore, there is no difference between the amplitude levels of the signal Ich2 and the signal Qch2 output from the AGC 107. At this time, the AGC 107 can operate normally.

On the other hand, the carrier of the IF input signal and the oscillation signal of the local oscillator 3 have the same frequency, but have a phase difference of π /
Take the case of 4 as an example. At this time, the signal space diagram of the digital in-phase signal Ich1 and the digital quadrature signal Qch1 is as shown in FIG.

At this time, the magnitude of the amplitude of the digital in-phase signal Ich1 is as follows: ｛(a / √2) × 2 + (3a / √2) × 2｝ / 4 = a√2 (1) .

On the other hand, the magnitude of the amplitude of the digital quadrature signal Qch1 is as follows: {(a / √2) × 2 + (3a / √2) × 2｝ / 4 = a√2 (1)

In the AGC 107 shown in FIG. 8, the output of the absolute value calculator 21 is | a√2 |, and the output of the absolute value calculator 22 is | a√2 |. That is, the output values of the absolute value calculator 21 and the absolute value calculator 22 become the same, and the output of the adder 23 becomes 0. That is, although the amplitude levels are different, it is considered that the amplitude levels match. Therefore, the averaging circuit 124
Cannot calculate an appropriate amplitude correction multiplication factor. Therefore, the AGC 107 cannot properly adjust the amplitude levels of the digital in-phase signal Ich1 and the digital quadrature signal Qch1.

As described above, depending on the phase difference between the carrier of the IF input signal and the oscillation signal of the local oscillator 3, AG
C107 may not be able to properly adjust the amplitude levels of digital in-phase signal Ich1 and digital quadrature signal Qch1. Here, QPSK is taken as an example, but the above problem always occurs when demodulating a signal generated by the multilevel quadrature modulation scheme.

In the AGC 107, the digital in-phase signal Ich
1 and the digital quadrature signal Qch1 are not properly adjusted in amplitude level, so that the demodulated signal Ic
The distortion occurs in h4 and the signal Qch4. Then, there is a problem that a code error occurs in the signal Ich4 and the signal Qch4.

An object of the present invention is to provide a quasi-synchronous detection type demodulator capable of performing a normal demodulation operation regardless of a phase difference between a carrier of an IF input signal and an oscillation signal of a local oscillator.

[0022]

According to a first aspect of the present invention, there is provided a demodulator based on a quasi-synchronous detection system for demodulating an in-phase component and a quadrature component of an input modulated wave signal using an oscillation signal from a local oscillator. A / D conversion means for digitally converting the signal demodulated by the demodulation means, and an in-phase component of the input modulation wave signal irrespective of a frequency difference and a phase difference between a carrier wave of the input modulation wave signal and an oscillation signal from the local oscillator. Amplitude correcting means for correcting the amplitude level of the quadrature component to coincide with the amplitude level of the quadrature component, phase adjusting means for eliminating the phase error of the amplitude-corrected signal, and amplitude for eliminating the amplitude error of the amplitude-corrected signal And an adjusting means.

In the demodulator based on the quasi-synchronous detection system according to the second aspect of the present invention, the amplitude correction means determines that the phase difference between the carrier of the input modulated wave signal and the oscillation signal from the local oscillator causes the amplitude correction means to malfunction. The configuration is provided with a rotation angle monitoring means for determining whether or not a specific phase difference occurs.

According to a third aspect of the present invention, in the demodulator based on the quasi-synchronous detection method, the amplitude correcting means detects an amplitude level of a signal input to the amplitude correcting means when the rotation angle monitoring means detects a specific phase difference. Is provided with an amplitude amplifying means for amplifying at a multiplication factor immediately before a specific phase difference is detected.

According to a fourth aspect of the present invention, in the quasi-synchronous detection type demodulator, the rotation angle monitoring means determines whether the phase difference between the carrier of the input modulated wave signal and the oscillation signal of the local oscillator is a specific phase difference. A configuration is provided that includes a comparison circuit for comparing whether or not the phase difference is detected, and a counting circuit for counting a specific phase difference detected by the comparison circuit.

In the quasi-synchronous detection type demodulator according to the present invention, when the rotation angle monitoring means detects a specific phase difference, the amplitude amplifying means immediately before the specific phase difference is detected. Multiplier holding means for holding a multiplier for adjusting the amplitude level of a signal input to the input means, and multiplying means for adjusting the amplitude level of a signal input to the amplitude correction means in accordance with the multiplier held by the multiplier holding means And a configuration including:

[0027]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram for explaining an embodiment of a quasi-synchronous detection type demodulator according to the present invention. The demodulator using the quasi-synchronous detection method shown in FIG. 1 includes multipliers 1 and 2, a local oscillator 3, a π / 2
Phase shifter 4, A / D converters (A / D converters) 5, 6
, AGC (automatic amplitude correction circuit) 7, and complex multiplier 8
, An AGC 9, an error detector 10, and an NCO (Numerically Controlled Oscillator) 12. Here, the AGC 7 and the NCO 12 are examples of an amplitude correction unit.

FIG. 2 is a block diagram showing an internal configuration of AGC 7 shown in FIG. The AGC 7 shown in FIG. 2 includes a multiplier 20, absolute value calculators 21 and 22, an adder 23,
And an averaging circuit 24. Averaging circuit 24
Is an example of the multiplication factor holding means.

FIG. 3 is a block diagram showing the internal configuration of the error detector 10 shown in FIG. The error detector 10 shown in FIG. 3 includes signal point error detectors 31 and 32,
34, 36 and an adder 35.

FIG. 4 is a block diagram showing an internal configuration of AGC 9 shown in FIG. AGC 9 shown in FIG.
F41, a multiplier 42 and a multiplier 43. The LPF 41 is a low-pass filter.

FIG. 5 is a block diagram showing an internal configuration of NCO 12 shown in FIG. The NCO 12 shown in FIG.
Integrator 51, rotation angle monitoring circuit 54, rotation angle control unit 5
2 and 53.

FIG. 6 is an explanatory diagram showing the internal configuration of the complex multiplier 8 shown in FIG. The complex multiplier 8 shown in FIG.
It comprises adders 61 and 62 and multipliers 63, 64, 65 and 66.

First, the operation of the entire demodulator shown in FIG. 1 will be described with reference to FIGS. An input signal (IF input signal) is input to multipliers 1 and 2. In the present embodiment, the IF input signal is a multilevel quadrature modulated signal. Examples of the multilevel quadrature modulation signal include QPSK, QAM, and the like.
Here, QPSK is used.

The local oscillator 3 oscillates at substantially the same frequency as the carrier frequency of the IF input signal, and outputs the oscillated signal to the multiplier 1 and the π / 2 phase shifter 4. π /
The two-phase shifter 4 applies the oscillation signal to the multiplier 2 by shifting the phase of the oscillation signal by π / 2. The multiplier 1 extracts an in-phase signal Ich0, which is an in-phase component of the IF input signal. Similarly, multiplier 2
Extracts a quadrature signal Qch0, which is a quadrature component of the IF input signal. Then, the in-phase signal Ich0 and the quadrature signal Q
ch0 is output to A / D converters 5 and 6, respectively.

The A / D converters 5 and 6 output the in-phase signal Ic.
h0 and the quadrature signal Qch0 are converted into a digital in-phase signal Ich1 and a digital quadrature signal Qch1, respectively. Here, the amplitude levels of the digital in-phase signal Ich1 and the digital quadrature signal Qch1 are theoretically the same, but actually the devices (MIX, OPAM)
Due to restrictions such as P), they are not the same.

Therefore, it is necessary to make the amplitude levels of the digital in-phase signal Ich1 and the digital quadrature signal Qch1 the same. Thus, the A / D converters 5 and 6 respectively provide the digital in-phase signal Ich1 and the digital quadrature signal Qch.
1 is output to the AGC 7.

As shown in FIG. 2, in the AGC 7, the digital in-phase signal Ich1 is input to the absolute value calculator 21.
The digital quadrature signal Qch1 is input to the absolute value calculator 22. The absolute value calculator 21 calculates the digital in-phase signal Ic.
The absolute value of the amplitude level of h1 is calculated, and a value obtained by multiplying the absolute value by −1 is output to the adder 23. On the other hand, the absolute value calculator 2
2 calculates the absolute value of the amplitude level of the digital quadrature signal Qch1 and outputs it to the adder 23.

The adder 23 comprises absolute value calculators 21 and 2
The values output in 2 are added and output to the averaging circuit 24. The averaging circuit 24 includes, for example, a low-pass filter and an adder. The averaging circuit 24 acquires an average value of the values input from the adder 23. Then, an amplitude correction multiplier, which is a coefficient for making the amplitude level of the digital in-phase signal Ich1 equal to the amplitude level of the digital quadrature signal Qch1, is calculated from the average value, and is output to the multiplier 20.

The multiplier 20 amplifies the amplitude level of the digital in-phase signal Ich1 according to the amplitude correction multiplier. On the other hand, the digital quadrature signal Qch1 is output as it is because it is not processed inside the AGC 7. Here, the signals after passing through the AGC 7 are referred to as a signal Ich2 and a signal Qch2. As described above, the amplitude level of the signal Ich2 becomes the same as the amplitude level of the signal Qch2.

For example, if the amplitude level of the digital in-phase signal Ich1 is 2.5 Vp-p and the digital quadrature signal Qc
It is assumed that the amplitude level of h1 is 5.0 Vpp. At this time, the averaging circuit 24 sets the amplitude correction multiplication factor to 2.0
Is output to the multiplier 20. Multiplier 20 amplifies the amplitude level of digital in-phase signal Ich1 to 2.0 times. That is, the amplitude level of the signal Ich2 is 5.0 Vp
−p. On the other hand, the amplitude level of signal Qch2 is the same as that of digital quadrature signal Qch1, so that
p. Therefore, at the output of the AGC 7, the signal Ich2
And the signal Qch2 has no difference in amplitude level.

In general, the carrier frequency of the IF input signal and the frequency of the oscillation signal of the local oscillator 3 do not exactly match. Therefore, compared with the case where the frequency of the oscillation signal of the local oscillator 3 and the carrier frequency of the IF input signal are equal and the phases of both signals are the same, the signal Ich
2 and the signal Qch2 include an effect based on the difference between the frequencies of both signals. Therefore, the influence of the frequency difference between the signal Ich2 and the signal Qch2 must be corrected. Therefore, the AGC 7 outputs the signal Ich2 and the signal Qch2 to the complex multiplier 8.

The complex multiplier 8 corrects the influence of the phase direction based on the frequency difference between the signal Ich2 and the signal Qch2, and outputs the corrected signal to the signal Ich3 and the signal Qch3.
To the AGC 9. The AGC 9 receives the signal Ich3
And the amplitude level of the signal Qch3,
4 and a signal Qch4. The signal Ich4 and the signal Qch4 are demodulated signals of the IF input signal.

The error detector 10 obtains a displacement (Ad) in the amplitude direction and a displacement (Pd1) in the phase direction of the signal Ich4 and the signal Qch4 with respect to the normal signal point position.
Here, the normal signal point position is defined as the signal Ich4 when the carrier frequency of the IF input signal and the frequency of the oscillation signal of the local oscillator 3 are equal and the phases of the signals are the same.
And the signal point position of the signal Qch4. Then, the error detector 10 outputs the signal Ad to the AGC 9, and outputs the signal Pd
1 is output to the NCO 12.

Signal Ich4 and signal Qch4 are referred to as signal Di and signal Dq, respectively. In the error detector 10 shown in FIG. 3, the signal Di is the signal point error detector 3
1 and input to multipliers 34 and 36. On the other hand, signal D
Similarly, q is input to the signal point error detector 32 and the multiplier 33.

The signal point error detector 31 detects an error in the phase direction and the amplitude direction of the signal Di with respect to the normal signal point position, and outputs the information to the multiplier 33 as an error signal Ei. Similarly, the signal error detector 32 outputs the error signal E
q is output to the multiplier 34. The multiplier 33 outputs a value (−Dq · Ei) obtained by multiplying the result (Dq · Ei) obtained by multiplying the signal Dq and the error signal Ei by −1 to the adder 35.

The multiplier 36 uses the value (Di · Ei) obtained by multiplying the signal Di and the error signal Ei as the signal Ad to set the AGC 9
Output to The multiplier 34 multiplies the signal Di by the error signal Eq, and outputs the result (Di · Eq) to the adder 35. The adder 35 adds the outputs of the multipliers 33 and 34, and adds the result (Di · Eq−Dq · E).
i) is output to the NCO 12 as the signal Pd1.

In the AGC 9, the LPF 41 removes a jitter component of the signal Ad. The LPF 41 outputs the signal Ad from which the jitter component has been removed to the multiplier 42 and the multiplier 4.
Output to 3. The multiplier 43 amplifies the amplitude level of the signal Ich3 according to the value of the signal Ad, and outputs the result as the signal Ich4. Similarly, multiplier 42 outputs signal Qch4. As described above, the AGC 9 outputs the signal Ich4 and the signal Q based on the signal Ad output from the error detector 10.
The amplitude level of ch4 can be corrected.

As shown in FIG. 5, in the NCO 12, the integrator 51 removes the jitter component of Pd1 and outputs the rotation angle signal A
Create ng. Then, the rotation angle signal Ang is input to the rotation angle control units 52 and 53 and the rotation angle monitoring circuit 54. Using the rotation angle signal Ang, the rotation angle controllers 52 and 53 output to the complex multiplier 8 sin (Ang) and cos (Ang), which are parameters for adjusting the phases of the signal Ich2 and the signal Qch2, respectively. The rotation angle monitoring circuit 54 monitors the rotation angle signal Ang for each symbol, and determines whether the phase difference between the carrier of the IF input signal and the oscillation signal of the oscillator 3 is a specific phase difference.

In the complex multiplier 8, the output cos (Ang) from the NCO 12 is input to the multiplier 65 and the multiplier 66. Further, sin (Ang) is input to the multiplier 63 and the multiplier 64. The multiplier 65 multiplies Ich2 by cos (Ang), and outputs the result, Ich2
Output cos (Ang) to the adder 61; Multiplier 6
6 multiplies Qch2 by cos (Ang) and outputs the result, Qch2 · cos (Ang), to adder 62.

The multiplier 63 outputs Ich2 and sin (An
g), and outputs Ich2 · sin (Ang) to the adder 62. The multiplier 64 includes Qch2 and sin (A
ng), and the resulting value is multiplied by -1.
The ch2 · sin (Ang) is output to the adder 61. The adder 61 adds the outputs of the multipliers 45 and 44.

Then, the resulting Ich2 · cos
(Ang) -Qch2 · sin (Ang) is output as Ich3. The adder 62 adds the outputs of the multiplier 63 and the multiplier 66. And the result, Ich
2 · sin (Ang) + Qch2 · cos (Ang) is output as Qch3. As described above, the signal Ich3
And the phase of signal Qch3 is adjusted.

Next, a description will be given mainly of the features of the present invention. The rotation angle monitoring circuit 54 includes a comparison circuit and a counter. The comparison circuit monitors the rotation angle signal Ang for each symbol and determines whether the phase difference between the carrier of the IF input signal and the oscillation signal of the local oscillator 3 is a specific phase difference. As a specific phase difference, for example, π /
4, there are N times (π is an integer) of π / 4.

If the phase difference is a specific one, the comparison circuit
Is output to the counter. If the phase difference is not a specific phase difference, the comparison circuit outputs 0 to the counter. When a fixed number of 1s are continuously input, the counter counts AGC to AGC7.
Outputs stop signal.

In the AGC 7, the averaging circuit 124
An AGC stop signal is received. As already explained, IF
When the phase difference between the carrier of the input signal and the oscillation signal of the local oscillator 3 has a specific value, the output of the adder 23 becomes 0. That is, when the AGC stop signal is input, the output from the adder 23 becomes 0, so that it is not possible to calculate an appropriate amplitude correction multiplier.

Therefore, the averaging circuit 124 outputs to the multiplier 20 the amplitude correction multiplier immediately before the AGC stop signal is input. For example, if the amplitude correction multiplication factor immediately before the input of the AGC stop signal is 2.0, 2.0 is output to the multiplier 20. Then, the multiplier 20 outputs the digital in-phase signal Ich with the amplitude correction multiplier immediately before the input of the AGC stop signal.
Amplify 1.

In a conventional quasi-synchronous detection type demodulator,
When the carrier frequency of the IF input signal and the oscillation frequency of the local oscillator 3 are the same or substantially equal, or when the modulator and the demodulator use the same oscillator in the radio station itself, the IF signal is turned back as a device maintenance signal. In this case, if the phase difference between the carrier of the IF input signal and the oscillation signal of the oscillator 3 was π / 4 or N times π / 4 (N is an integer), the AGC 7 did not operate normally. Furthermore, A
When the GC 7 does not operate normally, distortion occurs in the demodulated signal, and a code error occurs in the demodulated signal.

However, according to the present invention, NCO 12
When the phase difference between the carrier of the IF input signal and the oscillation signal of the oscillator 3 is a specific phase difference, the AGC stop signal is sent to the AGC 7
Output to The AGC 7 outputs the digital in-phase signal Ic at the amplitude correction multiplier immediately before the AGC stop signal is input.
h1 and the digital quadrature signal Qch1 can be amplified. Therefore, the AGC 7 can operate normally regardless of the phase difference between the carrier of the IF input signal and the oscillation signal of the oscillator 3. Therefore, the signal Ich4 which is a demodulated signal
No distortion occurs in Qch4 and Qch4. Therefore,
Good demodulation control can be performed.

[0058]

According to the first aspect of the present invention, a demodulating means for demodulating an in-phase component and a quadrature component of an input modulated wave signal using an oscillating signal from a local oscillator, and a digital signal demodulated by the demodulating means. A / D conversion means for converting,
Amplitude correction means for correcting the amplitude level of the in-phase component and the amplitude level of the quadrature component of the input modulated wave signal to be the same regardless of the frequency difference and phase difference between the carrier wave and the oscillation signal of the input modulated wave signal; A phase adjustment unit for eliminating a phase error of the corrected signal, and an amplitude adjustment unit for eliminating an amplitude error of the amplitude-corrected signal. There is an effect that the demodulation operation can be performed regardless of the phase difference.

According to the second aspect of the present invention, in the amplitude correction means, the phase difference between the carrier of the input modulated wave signal and the oscillation signal from the local oscillator is a specific phase difference at which the amplitude correction means malfunctions. Since the configuration is provided with the rotation angle monitoring means for determining whether or not the rotation angle is determined, the rotation angle monitoring means has an effect that a specific phase difference can be detected.

According to the third aspect of the present invention, when the rotation angle monitoring means detects a specific phase difference, the amplitude correction means
The amplitude correction means is provided with an amplitude amplifying means for amplifying the amplitude level of the signal input to the amplitude correction means at a multiplication factor immediately before a specific phase difference is detected. In this case, it is possible to amplify the amplitude level of the signal input thereto.

According to the fourth aspect of the invention, the rotation angle monitoring means compares the phase difference between the carrier of the input modulated wave signal and the oscillation signal of the local oscillator with a specific phase difference. And a counting circuit that counts a specific phase difference detected by the comparing circuit, so that the output from the comparing circuit outputs to the outside that the counting circuit has detected the specific phase difference. It has the effect that it can be done.

According to the fifth aspect of the present invention, when the rotation angle monitoring means detects a specific phase difference, the amplitude amplifying means adjusts a signal inputted to the amplitude correction means immediately before the specific phase difference is detected. A configuration including: a multiplier holding unit that holds a multiplier for adjusting the amplitude level; and a multiplier that adjusts the amplitude level of a signal input to the amplitude corrector in accordance with the multiplier held by the multiplier. Therefore, when a specific phase difference is detected, the amplitude amplifying means has an effect that it can amplify the amplitude level of a signal input to itself at a multiplier immediately before the specific phase difference is detected. .

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment according to the present invention.

FIG. 2 is a block diagram showing an internal configuration of AGC 7 shown in FIG.

FIG. 3 is a block diagram showing an internal configuration of an error detector 10 shown in FIG.

FIG. 4 is a block diagram showing an internal configuration of AGC 9 shown in FIG.

FIG. 5 is a block diagram showing an internal configuration of an NCO 12 shown in FIG.

FIG. 6 is a block diagram showing an internal configuration of the complex multiplier 8 shown in FIG.

FIG. 7 is a block diagram showing a configuration of a conventional quasi-synchronous detection type demodulator.

FIG. 8 is a block diagram showing an internal configuration of AGC 107 shown in FIG.

FIG. 9 is an explanatory diagram showing a signal space diagram of the digital in-phase signal Ich1 and the digital quadrature signal Qch1 when the carrier of the IF input signal and the oscillation signal of the local oscillator 3 are synchronized.

FIG. 10 is an explanatory diagram showing a signal space diagram of the digital in-phase signal Ich1 and the digital quadrature signal Qch1 when the phase difference between the carrier of the IF input signal and the oscillation signal of the local oscillator 3 is π / 4.

[Explanation of symbols]

 1, 2 multiplier 3 local oscillator 4 π / 2 phase shifter 5, 6 A / D converter 7 AGC 8 complex multiplier 9 AGC 10 error detector 12 NCO

Claims (5)

[Claims] 1. A demodulator for demodulating an in-phase component and a quadrature component of an input modulated wave signal using an oscillation signal from a local oscillator, an A / D converter for digitally converting a signal demodulated by the demodulator, and an input. Amplitude correction means for correcting the amplitude level of the in-phase component and the amplitude level of the quadrature component of the modulated wave signal so as to match each other; phase adjustment means for eliminating a phase error of the amplitude-corrected signal; In a demodulator based on a quasi-synchronous detection method having amplitude adjustment means for eliminating an amplitude error, the amplitude correction means is configured to operate independently of a frequency difference and a phase difference between a carrier wave of an input modulated wave signal and an oscillation signal from a local oscillator. A demodulator using a quasi-synchronous detection method, which adjusts an amplitude level of a signal input to the demodulator. 2. The method according to claim 1, wherein the amplitude correction unit determines whether a phase difference between the carrier of the input modulated wave signal and the oscillation signal from the local oscillator is a specific phase difference at which the amplitude correction unit malfunctions. 2. The demodulator according to claim 1, further comprising monitoring means. 3. The amplitude correction means according to claim 1, wherein when the rotation angle monitoring means detects a specific phase difference, the amplitude level of a signal input to the amplitude correction means is calculated by a multiplier just before the detection of the specific phase difference. 3. A demodulator based on a quasi-synchronous detection method according to claim 2, further comprising amplitude amplification means for amplifying the signal. 4. A rotation angle monitoring means, comprising: a comparison circuit for comparing whether or not the phase difference between the carrier of the input modulated wave signal and the oscillation signal of the local oscillator is a specific phase difference; and a specific circuit detected by the comparison circuit. 4. A demodulator according to claim 2, further comprising a counting circuit for counting a phase difference of the quasi-synchronous detection method. 5. The amplitude amplifying means includes a multiplier for adjusting the amplitude level of a signal input to the amplitude correction means immediately before the specific phase difference is detected when the rotation angle monitoring means detects the specific phase difference. 6. A multiplying means according to claim 3, further comprising: a multiplier holding means for holding a factor; and a multiplying means for adjusting an amplitude level of a signal input to the amplitude correcting means according to the multiplier held by the multiplier holding means. Demodulator based on synchronous detection.