JP2001189451A - Method for manufacturing semiconductor device - Google Patents

Abstract

[PROBLEMS] An amorphous or polysilicon film is deposited on a silicon semiconductor substrate and then is selectively grown without a high-temperature treatment on a single crystal layer only on an impurity diffusion region. And polycrystalline silicon are removed by etching. SOLUTION: A layer 7 of polysilicon or the like is deposited at a low temperature of about 600 ° C. on a semiconductor substrate 1 and on insulating films 4 and 5 for protecting gates. Subsequently, the silicon single crystal layer 8 is formed on the semiconductor substrate 1 by solid-phase growth by a heat treatment at about 600 ° C. After that, the insulating film 4, which has not been single-crystallized,
After the solid phase growth, the selective etching of polysilicon or the like on 5 is performed in the same reaction chamber for LP-CVD. The etching in the reaction chamber is performed in a reduced pressure atmosphere of about 10 Torr, in a gas obtained by diluting hydrochloric acid with hydrogen, in a temperature range of about 600 ° C. to 800 ° C. In this temperature region, only the layer of polysilicon or the like remaining on the insulating films 4 and 5 can be selectively etched without etching the silicon single crystal layer 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an elevated S / D (elevated source) for forming a silicon layer on an impurity diffusion region by selective epitaxial growth.
The present invention relates to a method for manufacturing a semiconductor device having a MOS transistor using e / Drain technology.

[0002]

2. Description of the Related Art Conventionally, MOS (Metal Oxide Semiconduct)
(or) Self-Aligned Silicide (IC) technology for depositing metals such as Co and Ti on a diffusion layer in a self-aligned manner to realize fine and high-speed devices.
de = SALICIDE) is known. On the other hand, in a semiconductor device, as the miniaturization progresses, it becomes necessary to form an impurity diffusion region shallower than ever. However, SALI as described above
When the CIDE technology is applied, the metal deposited when the silicidation reaction occurs between the metal and the silicon substrate is silicided while consuming the silicon substrate, so that it is difficult to form a shallow junction as a result.

[0003]

In order to solve this problem, a silicon single crystal layer is epitaxially grown on an impurity diffusion region formed on a silicon substrate, and a source / drain (S / D) region is formed on the original silicon substrate surface. A method has been conceived in which a metal is deposited and then a silicidation reaction is performed. According to this method, a shallow junction can be obtained at the same time as forming the low-resistance impurity diffusion region. A technique for epitaxially growing silicon on an impurity diffusion region formed on a silicon substrate is called an elevated (S / D) technique. However, the normally elevated S / D is LP (Low)
Pressure)-CVD (Chemical Vapor Deposition) using a high temperature heat treatment of 800 ° C. or more using a device, the impurity profile of the channel region and impurity diffusion region previously formed by ion implantation etc. changes, and MOS transistors Performance as designed cannot be achieved. Particularly, boron in the gate electrode diffuses into the channel region, so that the gate is depleted and the threshold voltage changes, which is a serious problem.

As described above, with the recent increase in the speed and miniaturization of transistors, it is necessary to form the impurity diffusion region of the MOSFET with a shallow and low resistance. In order to realize a shallow junction of the impurity diffusion region in a high-performance transistor, silicon is epitaxially grown on the impurity diffusion region, and impurities are ion-implanted from the silicon epitaxial layer to form a junction from the original silicon substrate surface to a shallow region. It can be formed.
Also in the above-mentioned SALICIDE technology, a margin between the pn junction and the bottom surface of the silicide can be ensured by depositing a metal after epitaxially growing silicon on the impurity diffusion region and siliciding the metal. This makes it possible to greatly reduce the joining leak. Usually UHV-CV for selective epitaxial growth
A D apparatus, an LP-CVD apparatus, or the like is used. Above all, from the viewpoints of production efficiency and process stability, it is desired to apply LP-CVD which has been widely used in the ULSI manufacturing process and has a proven track record. Typical selective epitaxial growth using LP-CVD is performed by a vapor phase growth method in a mixed atmosphere of a silicon material such as silane or dichlorosilane and an etching gas such as chlorine or hydrochloric acid.

On the other hand, in a future fine semiconductor device,
Since the thermal diffusion of the dopant is severely restricted, it is desirable that the thermal step of CVD can be performed at as low a temperature as possible. However, in order to obtain a practical deposited film thickness by, for example, a vapor phase growth method using LP-CVD, a high-temperature heat treatment of at least 800 ° C. or more is required. In addition, impurity diffusion from the gate to the channel cannot be ignored.
The present invention has been made under such circumstances,
After depositing an amorphous or polycrystalline silicon layer on the impurity diffusion region formed in the silicon semiconductor substrate, this layer is selectively grown into a single crystal layer only on the impurity diffusion region without high-temperature treatment. Provided is a method for manufacturing a semiconductor device in which amorphous silicon or polycrystalline silicon remaining after performing a step of etching is removed without performing a complicated step.

[0006]

According to the present invention, amorphous silicon or polycrystalline silicon is deposited on a semiconductor substrate at a low temperature of about 600.degree. C. and solid-phase grown by heat treatment at about 600.degree. Selective etching of polycrystalline silicon followed by solid phase growth of amorphous silicon or polycrystalline silicon followed by the same LP
-It is characterized in that it is performed in a reaction chamber where CVD is performed. Etching in LP-CVD equipment is 10 Torr
It is performed in a temperature range of about 600 ° C. to 800 ° C. in a gas obtained by diluting hydrochloric acid with hydrogen in a reduced pressure atmosphere of about r. In this temperature range, it is possible to selectively etch only the amorphous silicon or polycrystalline silicon remaining on the insulating film that covers and protects the gate without etching the silicon single crystal layer formed on the impurity diffusion region. Become.

According to a method of manufacturing a semiconductor device of the present invention, there is provided a step of forming a gate electrode covered with an insulating film on a semiconductor substrate via a gate oxide film, and forming the gate electrode and the gate electrode on the semiconductor substrate in a reaction chamber. Depositing an amorphous silicon film or a polycrystalline silicon film so as to cover the insulating film; and selectively growing the amorphous silicon film or the polycrystalline silicon film in the reaction chamber by solid phase growth on the semiconductor substrate. A step of monocrystallizing only a contacting portion and a step of etching and removing an amorphous silicon film or a polycrystalline silicon film remaining on the insulating film after being selectively monocrystallized in the reaction chamber. And Further, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode covered with an insulating film on a semiconductor substrate via a gate oxide film, and a step of forming a source region in the semiconductor substrate using the gate electrode as a mask. Forming a source region and a drain region, and forming an amorphous silicon film or a polycrystalline silicon film on the semiconductor substrate so as to cover the gate electrode and the insulating film in the reaction chamber after forming the source region and the drain region. Depositing the amorphous silicon film or the polycrystalline silicon film in the reaction chamber, and selectively crystallizing only a portion in contact with the source region and the drain region in the reaction chamber. Removing the amorphous silicon film or the polycrystalline silicon film remaining on the insulating film by etching. It is characterized by comprising the step of.

Further, a method of manufacturing a semiconductor device according to the present invention
Forming a gate electrode covered with an insulating film on a semiconductor substrate via a gate oxide film; and forming an amorphous silicon film or a multi-layer film on the semiconductor substrate so as to cover the gate electrode and the insulating film in the reaction chamber. Depositing a crystalline silicon film, selectively solid-phase growing the amorphous silicon film or polycrystalline silicon film in the reaction chamber, and monocrystallizing only a portion in contact with the semiconductor substrate; In the step of etching and removing the amorphous silicon film or the polycrystalline silicon film remaining on the insulating film, and after etching and removing the amorphous silicon film or the polycrystalline silicon film, using the gate electrode as a mask, Forming a source region and a drain region in a semiconductor substrate. It is characterized in. The deposition of the amorphous silicon film or the polycrystalline silicon film may be performed at 740 ° C. or lower, preferably 600 ° C. or lower in a low-pressure CVD apparatus. The solid-phase growth of the amorphous silicon film or the polycrystalline silicon film may be performed at 740 ° C. or lower, preferably 600 ° C. or lower in a low-pressure CVD apparatus.

Further, a method for manufacturing a semiconductor device according to the present invention
A step of forming a gate electrode having a portion other than an upper portion thereof covered with an insulating film via a gate oxide film on the semiconductor substrate, and forming an amorphous film in the reaction chamber so as to cover the gate electrode and the insulating film on the semiconductor substrate. Depositing a silicon film or a polycrystalline silicon film, and selectively solid-phase growing the amorphous silicon film or the polycrystalline silicon film in the reaction chamber to monocrystallize only a portion in contact with the semiconductor substrate. And selectively removing the amorphous silicon film or the polycrystalline silicon film remaining on the insulating film after selective single crystallization in the reaction chamber, wherein the temperature of the etching removal is from 600 ° C. to 740 ° C. ° C, and the total pressure in the reaction chamber where the etching is performed is from 10 Torr Is 00Torr, the etching atmosphere, the HCl diluted to between 1% and 50% H _2, and amorphous silicon film, polycrystalline silicon film and the single crystal silicon film is etched is etched away under a condition which is not etched It is characterized by:

Further, the method of manufacturing a semiconductor device according to the present invention comprises:
Forming a gate electrode covered with an insulating film via a gate oxide film on a semiconductor substrate; and forming an amorphous silicon film or a polycrystalline film on the semiconductor substrate so as to cover the gate electrode and the insulating film in the reaction chamber. Depositing a silicon film, and selectively solid-phase growing the amorphous silicon film or the polycrystalline silicon film in the reaction chamber to monocrystallize only a portion in contact with the semiconductor substrate; and Selectively removing the amorphous silicon film or the polycrystalline silicon film remaining on the insulating film after the single crystallization, wherein the temperature for the etching removal is 600.
C. to 740 ° C., and the total pressure in the reaction chamber in which the etching is performed is 10 Torr to 600 T
orr, the etching atmosphere is diluted with H ₂ to a range of 1% to 50% with H ₂ , and the amorphous silicon film is etched and removed under the condition that the polycrystalline silicon film and the single crystal silicon film are not etched. It is characterized by. The silicon single crystal layer formed by the single crystallization may have an end portion which is in contact with the insulating film covering the gate electrode and is equal or thicker than other portions.

Hereinafter, manufacturing steps along the process flow of the present invention will be described with reference to FIGS. 1 and 2 are process sectional views. Forming a gate oxide film 2 on a semiconductor substrate 1 such as silicon by thermal oxidation or the like;
A gate electrode 3 made of polysilicon is formed thereon. An insulating protective film 4 made of a silicon oxide film or the like is formed on the upper surface of the gate electrode 3, and a side wall insulating film 5 made of a silicon nitride film (SiN) is formed on the side surface of the gate electrode 3 (FIG. 1A). . An amorphous silicon film 7 is deposited at 740 ° C. or lower, preferably 600 ° C. or lower so as to include the gate electrode 3, the silicon nitride film 4, and the side wall insulating film 5 on the main surface of the semiconductor substrate 1 inside the LP-CVD apparatus. (FIG. 1 (b)). Next, in the LP-CVD apparatus, when heat treatment is performed in an H ₂ atmosphere, solid phase growth starts from a portion directly deposited on the main surface of the semiconductor substrate 1, and a single crystal grows in the film thickness direction. (Fig. 2
(A)). Thereafter, the amorphous silicon film 7 on the insulating film portion that was not single-crystallized in the same LP-CVD device.
Is selectively removed by etching with HCl gas diluted to about 10% with H ₂ . Thus, silicon single crystal layer 8 is formed on semiconductor substrate 1. Source / drain regions 9 are formed on the semiconductor substrate 1 including the silicon single crystal layer 8, and the gate oxide film 2, the gate electrode 3, and the source / drain regions 9 constitute a MOS transistor (FIG. 2B). . As described above, 800
The elevated S / D structure can be formed in the MOS transistor according to the present invention by the low-temperature heat treatment of not more than 100 ° C.
Application to FET becomes possible.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. First, referring to FIG. 3 to FIG.
An example will be described. 3 to 8 are process cross-sectional views illustrating the process of manufacturing the semiconductor device. An N-type impurity such as As (arsenic) is ion-implanted into a semiconductor substrate 101 such as silicon, and then thermal diffusion is performed to form an N-type impurity region (N-well) 102 having a depth of about 1 μm (FIG. 3).
(A)). Next, a silicon oxide film having a thickness of about 300 nm is buried in a predetermined region of the semiconductor substrate 101, and the silicon oxide film is formed into an element isolation region (STI: Shallow Trench Isolation) 10.
3 (FIG. 3B). Next, a protective oxide film 104 made of a silicon oxide film having a thickness of about 10 nm is formed on the semiconductor substrate 101, and ion implantation 105 for adjusting the threshold value of the formed MOS transistor is performed (FIG. 4).
(A)). After the protective oxide film 104 is peeled off, the gate oxide film 1 made of a silicon oxide film of about several nm is again formed.
06 is formed. As the gate oxide film, an oxynitride film containing about several% of nitrogen, TaO ₂ or the like can be used (FIG. 4B). Next, a polycrystalline silicon film 107 having a thickness of about 150 nm is deposited using a CVD method or the like, and RI is etched using a photoresist (not shown) as a mask.
Etching by E (Reactive Ion Etching) or the like is performed to form a gate electrode having a desired shape (FIG. 5A).

Thereafter, re-oxidation is performed to reduce RIE damage and electric field concentration at the gate end. next,
BF ₂ , 10 keV, ion implantation of about 5 × 10 ¹⁴ cm ⁻² is performed to form an LDD (Lightly Doped Drain) region 108 (FIG. 5B). This has the effect of relaxing the pn junction electric field and controlling the generation of hot electrons. Next, an SiO ₂ film having a thickness of about 10 nm is
A film is deposited, and this is combined with the above-described reoxidized film to form a liner layer 109. Next, a film thickness of 5
A silicon nitride film (SiN) 110 of about 0 nm is deposited on the liner layer 109 with good coverage (FIG. 6).
(A)). Subsequently, the entire surface is etched by RIE to leave SiN only on the gate side wall, and the gate side wall insulating film 110 is formed.
Is formed (FIG. 6B). The above-mentioned liner layer 109
Serves as an etching stopper when performing RIE etching of the silicon nitride film 110. Thereafter, silicon selective epitaxial growth is performed. Since the epitaxial layer needs to take over the crystallinity of the semiconductor substrate 101 for epitaxial growth, the SiO ₂ films 106 and 110 remaining on the source / drain regions need to be removed. There is. Therefore, before the epitaxial growth, for example, the SiO ₂ films 106 and 110 on the source / drain regions are removed in advance by etching with diluted hydrofluoric acid or the like.

As a result, the SiO ₂ films 106 and 110 become
It is formed below the gate electrode and on the side wall of the gate (FIG. 7A). Subsequently, an amorphous silicon film 111 having a thickness of about 50 nm is deposited on the entire surface of the semiconductor substrate 101 with good coverage using silane or the like by an LP-CVD apparatus. This may be a polycrystalline silicon film. The deposition temperature at this time is about 600 ° C. (FIG. 7)
(B)). When deposition of a desired film thickness is completed, supply of a source gas such as silane is stopped, and solid phase growth is performed in an H ₂ atmosphere. Since the solid phase growth occurs only in the portion of the amorphous silicon film 111 which is in contact with the semiconductor substrate 101, the amorphous silicon in the portion where the silicon is exposed on the semiconductor substrate 101 is monocrystallized by the solid phase growth to form silicon. The single-crystal layer 112 is formed, and the amorphous silicon on the insulating films 103, 109, and 110 such as the gate side wall and the element isolation remains without being single-crystallized. Subsequently, HC diluted to 10% with H _{2 in} the same reaction chamber of the LP-CVD apparatus.
Only amorphous silicon is etched away using 1 gas. In this method, the crystallized silicon single crystal layer 1
Selective etching without etching 12 is possible,
The selectivity is 10 or more.

Further, productivity can be greatly improved because deposition of amorphous silicon, solid phase growth, and selective etching can be continuously performed in the same reaction chamber. Thereafter, a P-type impurity is ion-implanted into the LDD region 108 of the semiconductor substrate 101 and diffused by heating to form a source / drain region 113 (FIG. 8). As described above, an elevated S / D structure can be realized by a low-temperature heat treatment at 800 ° C. or lower. Thereafter, the gate electrode peripheral structure is completed through a normal SALICIDE process. As described above, since silicon selective epitaxial growth using solid phase growth can be consistently performed in the same reaction chamber, productivity is dramatically improved. Further, since the process temperature can be reduced as compared with the conventional selective epitaxial growth method using vapor phase growth, a change in the impurity profile in the fine MOSFET is small and a process with a small thermal history can be constructed.

Next, a second embodiment will be described with reference to FIGS. 9 to 12 are cross-sectional views of a semiconductor substrate illustrating a manufacturing process of a semiconductor device. The steps up to the step of forming the gate oxide film 206 are the same as those in the first embodiment, and thus the description thereof is omitted. That is, the semiconductor substrate 201
, An element isolation region 203 is formed, and further, an N well region 202 is formed. Then, the semiconductor substrate 201
Main surface is a gate oxide film 2 made of a silicon oxide film or the like.
06 is formed. 150 nm using CVD method etc.
Is deposited, followed by ion implantation of BF _{2 at} 10 keV and about 5 × 10 ⁴ cm ⁻² for gate doping. Next, a silicon nitride film (SiN) 208 having a thickness of about 50 nm is deposited on the entire surface of the semiconductor substrate 201, and the silicon nitride film 208 is etched using the photoresist 209 as a mask (FIG. 9B). next,
Using this silicon nitride film 208 as a mask, RIE etching is performed on the polycrystalline silicon 207 into a gate electrode shape.
Thereafter, re-oxidation is performed to alleviate RIE damage and electric field concentration at the end of the gate electrode (FIG. 10A).

Next, BF ₂ , 10 keV, 5 × 10 ⁴ c
The LDD region 210 is formed by ion implantation of about m ⁻² . This has the effect of reducing the electric field at the PN junction and suppressing the generation of hot electrons. Next, an SiO ₂ film having a thickness of about 10 nm is deposited using an LP-CVD method or the like.
The re-oxidized layer and the above-described layer are combined to form a liner layer 211 (FIG. 10B). Next, a silicon nitride film (SiN) having a thickness of about 50 nm is deposited on the liner layer with good coverage by an LP-CVD method or the like, and the silicon nitride film is left only on the gate side wall by the RIE method or the like to form a gate sidewall insulating film. 212 (FIG. 11A). Liner layer 211
Serves as an etching stopper when the silicon nitride film is subjected to RIE processing. Thereafter, silicon selective epitaxial growth is performed. Since the epitaxial layer needs to inherit the crystallinity of the semiconductor substrate 201 for epitaxial growth, it is necessary to remove SiO ₂ remaining on the source / drain regions. Therefore, before the epitaxial growth, the SiO.sub.2 of the main surface of the semiconductor substrate 201 which is exposed in advance by, for example, etching with diluted hydrofluoric acid or the like.
₂ is removed (FIG. 11B).

Next, an amorphous silicon film 2 having a thickness of about 50 nm is formed using silane or the like by an LP-CVD apparatus.
13 is deposited on the entire surface of the semiconductor substrate 201 with good coverage.
The deposition temperature at this time is about 600 ° C. (FIG. 12)
(A)). When deposition of a desired film thickness is completed, supply of a source gas such as silane is stopped, and solid phase growth is performed in an H ₂ atmosphere. Since the solid phase growth occurs only in the portion of the amorphous silicon film 213 that is in contact with the semiconductor substrate 201, the amorphous silicon on the exposed main surface of the semiconductor substrate 201 is monocrystallized by the solid phase growth to form the silicon single crystal layer 214.
Is formed, and the amorphous silicon on the insulating film such as the silicon nitride film (sidewall insulating film) 212 surrounding the gate electrode 207 and the element isolation region 203 remains without being single-crystallized.
Subsequently, amorphous silicon is etched using HCl gas diluted to 10% with H ₂ in the same reaction chamber of the LP-CVD apparatus. This etching method is selective etching in which crystallized silicon is not etched, and a selectivity of 10 or more is obtained.

In this embodiment, since the upper portion of the gate electrode is covered with the silicon nitride film, even if the amorphous silicon film on the insulating film is polycrystallized, a selectivity can be obtained between polycrystalline silicon and single crystal silicon. The following conditions may be applied, and a high-rate etching can be performed under a slightly high temperature condition of about 700 ° C. to 800 ° C. In addition, productivity can be greatly improved because deposition of amorphous silicon, solid phase growth, and selective etching can be continuously performed in the same reaction chamber. After that, P
The source / drain regions 214 are formed by ion-implanting and diffusing the impurities by heating (FIG. 12B). As described above, an elevated S / D structure can be realized by low-temperature heat treatment at 800 ° C. or lower. Thereafter, through a normal SAICIDE process, a structure around the gate electrode is completed. As described above, since silicon selective epitaxial growth using solid phase growth can be consistently performed in the same reaction chamber, productivity is dramatically improved. Furthermore, since the process temperature can be reduced as compared with the conventional selective epitaxial growth method using vapor phase growth, an efficient process with small change in impurity profile in a small MOSFET and a small heat history can be obtained.

Next, a third embodiment will be described with reference to FIG. Silicon single crystal layer 8 formed in the first embodiment
As shown in FIG. 2B, a facet is formed on the gate side wall insulating film 5. The characteristic degradation and peeling of the silicon single crystal layer are likely to occur from this portion. In this embodiment, a method in which a facet is not formed will be described. FIG. 13 is a cross-sectional view illustrating a manufacturing process of the semiconductor device. A gate oxide film 302 is formed on a semiconductor substrate 301 of silicon or the like by a thermal oxidation process or the like, and a gate electrode 303 made of polysilicon is formed thereon. An insulating protective film 304 made of a silicon oxide film or the like is formed on the upper surface of the gate electrode 303, and a silicon nitride film (S
A sidewall insulating film 305 made of iN) or the like is formed. Then, inside the LP-CVD apparatus, an amorphous silicon film 307 is deposited at a temperature of 600 ° C. or less so as to include the gate electrode 303, the silicon nitride film 304, and the sidewall insulating film 305 on the main surface of the semiconductor substrate 301. (FIG. 13 (a)).

Next, in this LP-CVD apparatus,
When the heat treatment is performed in an H ₂ atmosphere, solid phase growth starts from a portion directly deposited on the main surface of the semiconductor substrate 301,
A single crystal 308 is formed along the silicon single crystal on the semiconductor substrate 301 by making it all single crystallized in the film thickness direction. Then, when the heat treatment is further continued, the amorphous silicon film 307 on the sidewall insulating film 305 continues to be single-crystallized, and the thickness increases from the end of the silicon single crystal 308 along the sidewall insulating film 305. become. This film thickness portion 308
a eliminates the facet portion (FIG. 13B). Amorphous silicon film 307 on the insulating film portion which has not been single-crystallized in the same LP-CVD device, the H ₂ 10
Etching is performed using HCl gas diluted to%. Thus, a silicon single crystal layer 308 is formed on semiconductor substrate 301. This silicon single crystal layer 3
A source / drain region 309 is formed on the semiconductor substrate 301 including the gate electrode 08, and the gate oxide film 302, the gate electrode 303, and the source / drain region 309 constitute a MOS transistor (FIG. 13C).

As described above, the ultra-fine MOSFE having a gate length of 0.1 μm or less is formed by the low-temperature heat treatment at 800 ° C. or less.
Application to T becomes possible. As described above, since silicon selective epitaxial growth using solid phase growth can be consistently performed in the same reaction chamber, productivity is dramatically improved.
Further, since the process temperature can be reduced as compared with the conventional selective epitaxial growth method using vapor phase growth, the fine M
An efficient process with a small change in the impurity profile of the OSFET and a small heat history can be obtained. In this embodiment, in particular, the silicon single crystal layer is formed uniformly without deterioration in characteristics.

FIG. 14 is a schematic cross-sectional view of a single-wafer CVD apparatus used for carrying out the method of manufacturing a semiconductor device according to the present invention. In addition, a batch type apparatus can also be used. In the figure, a reaction chamber (chamber) 41
Numeral 1 has a vacuum exhaust port 406 so that airtightness can be maintained. The upper lid of the upper part of the chamber 411 supports the upper electrode 404. Further, a magnet 405 for generating a magnetron discharge is provided on the side of the chamber. The upper electrode 404 has a disk-shaped shower nozzle having many small holes 403 penetrating from the upper surface to the lower surface. The upper electrode 404 is provided with a high frequency power supply 401 for applying a high frequency voltage. The lower electrode 408 is supported by a column 412, and the column is configured to be able to move up and down, so that the distance between the electrodes can be changed as appropriate. In addition, a cooling pipe and a heater 409 for circulating a coolant in order to keep the temperature constant are built in the lower electrode 408 provided above the support 412. Further, on the lower electrode 408, an electrostatic chuck mechanism (not shown) for chucking the processing target substrate 410 by electrostatic force is provided to maintain heat conduction between the processing target substrate 410 such as a silicon wafer and the substrate support. ing. The lower electrode 408 includes a high-frequency power supply 407 that applies a high-frequency voltage via the support 412. The upper electrode 404 is connected to a gas supply pipe 402, and a reaction gas supplied into the chamber 411 is jetted from the gas supply pipe 402 toward the substrate 410 through the minute holes 403 of the shower nozzle.

[0024]

According to the present invention, silicon selective epitaxial growth utilizing solid-phase growth can be consistently performed in the same reaction chamber by the above-described structure, so that productivity is dramatically improved. Further, since the process temperature can be reduced as compared with the conventional selective epitaxial growth method using vapor phase growth, a process with a small change in impurity profile and a small thermal history in a fine MOSFET can be obtained.

[Brief description of the drawings]

FIG. 1 shows an M having an elevated S / D structure according to the present invention.
FIG. 4 is a process cross-sectional view for forming an OS transistor.

FIG. 2 shows an M having an elevated S / D structure according to the present invention.
FIG. 4 is a process cross-sectional view for forming an OS transistor.

FIG. 3 is a process sectional view for explaining the first embodiment of the present invention.

FIG. 4 is a process sectional view for explaining the first embodiment of the present invention.

FIG. 5 is a process sectional view for explaining the first embodiment of the present invention.

FIG. 6 is a process sectional view for explaining the first embodiment of the present invention.

FIG. 7 is a process sectional view for explaining the first embodiment of the present invention.

FIG. 8 is a process sectional view for explaining the first embodiment of the present invention.

FIG. 9 is a process sectional view for explaining the second embodiment of the present invention.

FIG. 10 is a process sectional view for explaining the second embodiment of the present invention.

FIG. 11 is a process sectional view for explaining the second embodiment of the present invention.

FIG. 12 is a process sectional view for explaining the second embodiment of the present invention.

FIG. 13 is a process sectional view for explaining the third embodiment of the present invention.

FIG. 14 is a schematic cross-sectional view of a single-wafer CVD apparatus used for carrying out the method of manufacturing a semiconductor device according to the present invention.

[Explanation of symbols]

1, 101, 201, 301 ... semiconductor substrate, 2, 1
06, 206, 302 ... gate oxide film, 3, 10
7, 207, 303: gate electrode (polycrystalline silicon film), 4, 208, 304: silicon nitride film (Si
N), 5, 110, 212, 305 ... sidewall insulating film,
7, 111, 213, 307, amorphous silicon film, 8, 112, 214, 308, silicon single crystal layer, 9, 113, 214, 309, source / drain region, 102, 202, etc. N-well area, 10
3, 203... Element isolation region, 104, 204,.
Protection oxide film, 105, 205: ion implantation for threshold adjustment, 108, 210: LDD region,
109, 211: liner layer, 209: photoresist, 401, 407: high frequency power supply, 4
02: gas supply pipe, 403: minute hole,
404: upper electrode 405: magnet, 406
... Exhaust port, 408 ... Lower electrode, 409 ...
・ Heater, 410 ・ ・ ・ Wafer (substrate to be processed), 4
11 ... reaction chamber (chamber), 412 ... support.

Claims (8)

[Claims] A step of forming a gate electrode covered with an insulating film on a semiconductor substrate via a gate oxide film; and forming the gate electrode and the insulating film on the semiconductor substrate in a reaction chamber. A step of depositing an amorphous silicon film or a polycrystalline silicon film; and, in the reaction chamber, the amorphous silicon film or the polycrystalline silicon film is selectively solid-phase grown to monocrystallize only a portion in contact with the semiconductor substrate. And a step of etching and removing an amorphous silicon film or a polycrystalline silicon film remaining on the insulating film after being selectively single-crystallized in the reaction chamber. . 2. A step of forming a gate electrode covered with an insulating film on a semiconductor substrate via a gate oxide film, and a step of forming a source region and a drain region in the semiconductor substrate using the gate electrode as a mask. Forming the source region and the drain region, and then depositing an amorphous silicon film or a polycrystalline silicon film on the semiconductor substrate to cover the gate electrode and the insulating film in the reaction chamber; A step of selectively solid-phase growing the amorphous silicon film or the polycrystalline silicon film in the reaction chamber to monocrystallize only a portion in contact with the source region and the drain region; Etching the amorphous silicon film or the polycrystalline silicon film remaining on the substrate. The method of manufacturing a semiconductor device, characterized in that. A step of forming a gate electrode covered with an insulating film on a semiconductor substrate via a gate oxide film; and forming the gate electrode and the insulating film on the semiconductor substrate in a reaction chamber. A step of depositing an amorphous silicon film or a polycrystalline silicon film; and, in the reaction chamber, the amorphous silicon film or the polycrystalline silicon film is selectively solid-phase grown to monocrystallize only a portion in contact with the semiconductor substrate. Etching the amorphous silicon film or the polycrystalline silicon film remaining on the insulating film in the reaction chamber; and etching and removing the amorphous silicon film or the polycrystalline silicon film from the gate electrode. Is used as a mask to form a source region and a drain region in the semiconductor substrate. The method of manufacturing a semiconductor device characterized by comprising a step. 4. An amorphous silicon film or a polycrystalline silicon film is deposited at 600 ° C. in a low-pressure CVD apparatus.
4. The method of manufacturing a semiconductor device according to claim 1, wherein the method is performed as follows. 5. 5. The solid-phase growth of the amorphous silicon film or the polycrystalline silicon film is performed in a low-pressure CVD apparatus for 60 hours.
The method is performed at a temperature of 0 ° C. or less.
The method for manufacturing a semiconductor device according to any one of the above. 6. A step of forming a gate electrode having a portion other than an upper portion covered with an insulating film on a semiconductor substrate with a gate oxide film interposed therebetween, and forming the gate electrode and the insulating film on the semiconductor substrate in a reaction chamber. Depositing an amorphous silicon film or a polycrystalline silicon film so as to cover, and selectively solid-phase growing the amorphous silicon film or the polycrystalline silicon film in the reaction chamber and contacting only the portion in contact with the semiconductor substrate. A step of monocrystallizing; and a step of etching and removing an amorphous silicon film or a polycrystalline silicon film remaining on the insulating film after selective single crystallization in the reaction chamber. Range from 600 ° C. to 740 ° C., and the total pressure in the reaction chamber where the etching is performed is 10 a 600Torr from orr, wherein the etching atmosphere HCl diluted ranging from 1% to 50% in H _2, and amorphous silicon film is removed by etching conditions polycrystalline silicon film and the single crystal silicon film is etched is not etched A method of manufacturing a semiconductor device. 7. A step of forming a gate electrode covered with an insulating film on a semiconductor substrate via a gate oxide film; and forming a gate electrode and the insulating film on the semiconductor substrate in a reaction chamber. A step of depositing an amorphous silicon film or a polycrystalline silicon film; and, in the reaction chamber, the amorphous silicon film or the polycrystalline silicon film is selectively solid-phase grown to monocrystallize only a portion in contact with the semiconductor substrate. And a step of selectively removing the amorphous silicon film or the polycrystalline silicon film remaining on the insulating film after selective crystallization in the reaction chamber, wherein the temperature of the etching removal is from 600 ° C. 740 ° C., and the total pressure in the reaction chamber where the etching is performed is from 10 Torr Is 00Torr, wherein the etching atmosphere HCl diluted ranging from 1% to 50% in H _2, and amorphous silicon film, the polycrystalline silicon film and the single crystal silicon film is etched is etched away under a condition which is not etched A method for manufacturing a semiconductor device, comprising: 8. An end portion which is in contact with the insulating film covering the gate electrode with the silicon single crystal layer formed by the single crystallization and has the same thickness or is thicker than other portions. The method of manufacturing a semiconductor device according to claim 1.