JP2001183119A - Pattern inspecting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set arbitrary sensitivity by reducing the influence of a position shift of an inspection pattern on a pattern inspecting device, the contraction of a base material, etc. SOLUTION: A camera 3 reads in the inspection pattern of an iC package 1. The read image is held in an image memory 5 and binarized by a binarizing circuit 6. A feature extracting operator having a feature extraction pattern including a defect to be detected is held in advance and scanned to detect a defect image. The detected image which is defective is expanded by a specific number of pixels and further contracted to connect defects and erase an isolated defect. The number of the pixels of the image which is thus obtained is decided to detect a defect.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern inspection apparatus for precisely inspecting a pattern of an IC package, a printed circuit board or the like.

[0002]

2. Description of the Related Art In IC packages and printed circuit boards,
Various patterns are formed by a method such as print plating. These are becoming smaller year by year due to the miniaturization of electronic components,
The wiring has also been miniaturized. Since these patterns may be partially missing or partially bulged, pattern inspection is required. In the inspection at the time of pattern formation of an IC package, a short circuit or a disconnection of the inspection pattern is inspected by a continuity test called a continuity checker. Defects with large protrusions due to manufacturing defects and insufficient insulation spacing, and defects in which the wiring portion of the pattern is thinner than the design value and lacks strength cannot be inspected by the continuity inspection, but has a serious effect on quality Is a defect. Although there is no short circuit or disconnection, it is necessary to optically detect these defects. Due to the miniaturization of electronic components, such inspections have shifted from visual inspections to mechanical inspections using television cameras, and various inspection methods have been proposed.

The following inspection methods have been proposed as conventional inspection methods. First, there is an inspection method called a perfect comparison method in which an inspection pattern is read and its position and width are compared with a reference master pattern and detected.

A method called cluster comparison for checking the number of test patterns and the area and position of each test pattern has been proposed. In the cluster comparison, it is possible to increase the detection sensitivity of a short circuit or a disconnection of a long wiring.

Further, the detected inspection pattern is binarized,
A feature extraction method is known in which a binarized image is calculated using a feature extraction operator to calculate a defective area.
The operator for feature extraction is an image pattern of a predetermined size smaller than the detected image, and a pattern predetermined so that a predetermined pixel has a detection or non-detection level so as to have a defect feature. . This operator is scanned over the entire surface of the inspection pattern, and a chip in the width direction, a protrusion, or the like is detected depending on whether or not the operator matches the feature extraction operator. According to this method, a defect can be effectively detected even if there is a relative displacement due to a pattern displacement or a contraction of the base material forming the pattern.

[0006]

In the pattern inspection, the positional accuracy of the wiring and the accuracy of the line width may be poor, but
Even when the area is small, the chipping in the width direction or the protrusion or short-circuit when the space between the cutting patterns is at a narrow position becomes a serious defect.
Therefore, even if the inspection pattern is slightly thinner than the master pattern as a whole, matching is not good, but it should be handled as a good product. However, the conventional inspection method using the perfect comparison method has a drawback that it is difficult to effectively determine the quality of such a defect. Further, if the detection sensitivity is increased, a false report is likely to occur, and if the false detection is to be reduced, the sensitivity is lowered.

The above-described cluster comparison method has a drawback that it is difficult to detect a chip, a break, or a protrusion at an end of an inspection pattern.

Further, the method based on the feature extraction method has a disadvantage that there is no method for setting the detection sensitivity, and it is difficult to flexibly deal with the method. Further, even if a feature extraction operator with high detection sensitivity is prepared, there is a drawback that if the sensitivity is raised, false reports tend to occur, and if the false reports are reduced, the sensitivity is lowered.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems caused by the conventional pattern inspection, and reduces the influence of the positional deviation of the inspection pattern and the relative deviation due to shrinkage of the base material forming the inspection pattern. It is another object of the present invention to enable the sensitivity to be set freely and detect a defect with less false alarm.

[0010]

According to a first aspect of the present invention, there is provided an image pickup apparatus for picking up an inspection pattern, and a binarization for binarizing an image picked up by the image pickup apparatus into a pattern portion and other portions. A defect detection unit that scans a binarized image obtained by the binarization unit with a predetermined feature extraction pattern and detects a defective pixel by detecting a position of a matching image; An expanding portion for expanding the defective pixel by a first predetermined number of pixels, a reducing portion for reducing the image expanded by the expanding portion by the second number of pixels, and a pattern abnormality based on the size of the reduced defective image. And a discriminating unit for discriminating.

According to a second aspect of the present invention, in the pattern inspection apparatus of the first aspect, the defect detecting section scans only a predetermined inspection area in the binarized image taken and binarized to detect a defect. It is characterized by detecting pixels.

According to a third aspect of the present invention, there is provided an image pickup apparatus for picking up an inspection pattern, a binarizing section for binarizing an image picked up by the image pickup apparatus into a pattern portion and other portions,
A defect detection unit configured to scan a binarized image obtained by the binarization unit with a predetermined feature extraction pattern and detect a defective pixel by detecting a position of a coincident image; and Performing a labeling process on a defective pixel group reduced by the expansion unit that expands the image expanded by the expansion unit by the second pixel number by a first predetermined number of pixels, and a defective pixel group reduced by the reduction unit. And an aggregation processing unit for detecting a defect based on each area.

According to a fourth aspect of the present invention, in the pattern inspection apparatus according to any one of the first to third aspects, the defect detection unit sets an arbitrary image to be inspected for the binarized image. An area memory having a plurality of areas, and an inspection information memory configured to hold defect detection information including a different feature extraction pattern for each inspection position or area set in the area memory. In this case, the defective pixel is detected by scanning the feature extraction pattern set in (1).

[0014]

(First Embodiment) FIG. 1 is a block diagram showing a configuration of a pattern inspection apparatus according to a first embodiment of the present invention. In this figure, IC package 1
Is an inspection target, the inspection pattern is imaged by the camera 3 while being illuminated by the illumination 2. The camera 3 is a camera such as a two-dimensional CCD camera or a line drive type CCD camera that can capture image data at high resolution, and is, for example, 1024 × 1024 or 4000 × 4000.
Having the following resolution. The signal from the camera 3 is temporarily stored in the image memory 5 via the preprocessing circuit 4. The image memory 5 has a binarization circuit 6, a feature extraction circuit 7,
An expansion / contraction circuit 8 is connected in cascade. Image memory 5
Area line 10 and control CPU 11
Is connected.

The binarization circuit 6 binarizes the image data of the inspection pattern based on the luminance level of one screen held in the image memory 5. Image memory 5 for binarization
Are statistically processed, a threshold value is calculated and binarized. For example, if the frequency of the luminance level is different between the part with copper foil and the part without copper foil, by setting a threshold value in the middle, the optimal binarization according to the detection target and the lighting condition at that time Processing can be performed. The feature extraction circuit 7 extracts a defective portion of the inspection pattern from the binarized image data by using a feature extraction operator described later. The expansion / contraction circuit 8
It is assumed that the defective pixel obtained here is expanded by a predetermined number of pixels and then contracted thereafter. The expansion is performed by expanding, for example, three pixels in all directions with respect to the detected defective pixel. In this way, for example, for a defect of one pixel, a square defect image of seven pixels on both the X axis and the Y axis can be obtained. At the time of contraction, the expanded image is contracted inward by a predetermined number, for example, four pixels, of the defective image. In this way, when a plurality of defects are united due to expansion, the defects do not disappear even when contracted, so that a defective portion can be extracted. The number of reduced pixels may be greater than or equal to the number of expanded pixels, or less than or equal to the number of expanded pixels.

The area memory 10 is a memory for setting an inspection area to be inspected in the image memory 5 in advance. The determination circuit 9 determines the number of pixels remaining as defects in the inspection area set in the memory for each defect. Output.
Further, the control CPU 11 executes a CP for performing each of these processes.
U, and an operation unit 13 for performing necessary area setting and operation is connected.

If the feature extraction operator used in the feature extraction circuit 7 detects, for example, a terminal portion of a copper foil pattern of a wiring board of the IC package 1, the feature extraction pattern is a feature extraction pattern matched to a defect of the inspection pattern. . FIG.
(A) shows an example thereof, which is composed of 17 × 17 pixels, of which a copper foil pattern is detected at a predetermined pixel position indicated by a white circle and a copper foil pattern is not detected at a predetermined pixel position indicated by a black circle. , A pattern that matches a detection pixel indicated by a black triangle and for which no copper foil is detected is extracted. It is assumed that a desired number of such characteristic operators C1 are set in advance based on various patterns formed on the package 1. For example, for an IC package inspection pattern composed of only horizontal and vertical patterns, the pattern shown in FIG.
Only those rotated by 0 °, 180 °, and 270 ° are required.
For an image to be inspected including a pattern having an inclination of 45 ° and 22.5 °, a feature extraction pattern corresponding to the inclination is used. For example, for a pattern having an inclination of 22.5 °, a feature operator C2 of a feature extraction pattern as shown in FIG. 2B is used. Other patterns having an inclination of 45 ° are formed in the same manner. This pattern can be used as it is in an inverted or rotated state by 90 °.

Next, the operation of this embodiment will be described with reference to inspection patterns and flowcharts. FIG.
Is a flowchart showing this operation. First, in step 21, the IC package 1 is irradiated with the illumination 2,
The copper foil pattern of the IC package 1 is imaged using the camera 3. The captured image is pre-processed by the pre-processing circuit 4 and written into the image memory 5 (step 22). The binarization circuit 6 detects the frequency of the luminance as shown in FIG. 3B, and performs a binarization process by setting an intermediate value between two peak values of the frequency with respect to the luminance as a threshold Th (step 23). The binarized image is stored in the image memory 5 again. Next, in step 24, a feature extraction process is performed.

FIGS. 4A and 4B show a normal image of a bonding pad portion which is a part of the inspection pattern of the package 1 held in the image memory 5 and the IC package 1.
It shows an image detected from above. It is assumed that this area A is set in the area memory 10 as an inspection area. Since this image is a horizontal pattern, the feature extraction operator C1 having the pattern shown in FIG. If one of the 17 × 17 pixel feature extraction patterns is missing in the ▲ part, it is adjusted to one end of the inspection area A as shown in FIG. Then, the entire area of the necessary pixels is continuously scanned by shifting one pixel at a time in the X-axis direction and the Y-axis direction. Then, at a position where the inspection image matches the feature extraction pattern, an output indicating a matching pixel is obtained as shown in FIG. This is newly stored as an image of the inspection image.

Next, in an expansion processing step 25, the expansion and contraction circuit 8 expands this pixel by, for example, three pixels. The dilation is performed one pixel at a time in the vertical and horizontal directions.
Since a pixel is expanded, even a defect pattern of one pixel has a shape of 7 × 7 pixels at the end of expansion. 6
If there is a defective pixel in the vicinity of the pixel, the detected pixels are united by expansion. FIG. 4D shows an enlarged image, and the adjacent defect images are continuous images. Next, in step 26, the expanded defect image is contracted inward. Here, the contraction is performed for the expanded pixels or more. When the expansion is performed for three pixels, the contraction is performed for, for example, four pixels or five pixels. FIG. 4E shows an example of a contracted image. In this way, even if the detection points are originally one pixel, when the detection points are combined by expansion, the detection points remain even by contraction. On the other hand, if the defect is an isolated defect of only one pixel, even if the defect is once expanded by a predetermined number of pixels, the detected point disappears if it is not connected because it is contracted by more than the expanded pixel. . By eliminating isolated detection points in this way, false alarms can be prevented and only true defects can be detected.

Next, at step 27, the judgment circuit 9
And the area of the remaining defect is measured, and only a large defect having a predetermined number of pixels or more is detected. If the number of pixels is equal to or larger than this pixel, the extracted test pattern is output as having an abnormality.
If it is equal to or less than the predetermined number of pixels, it is determined that there is no abnormality. In this way, even if the wiring arrangement accuracy and the line width accuracy are poor, the defect can be detected without being affected by the relative displacement due to the displacement of the inspection pattern or the contraction of the base material. In addition, since the expansion ratio, the contraction ratio, and the number of pixels for quality determination can be arbitrarily selected, flexible detection sensitivity can be set according to the intended use.

In this embodiment, the area to be inspected is set in the area memory 10, but all the detected images are binarized without using the area memory 10 and a specific feature extraction operator is set. Needless to say, it can be used for inspection. In addition to the feature extraction patterns, not only the lack of patterns but also the feature extraction patterns corresponding to various defects such as protrusions, intervals between patterns, and pattern thickness are set in advance, and each of the feature extraction patterns is set in the inspection area. It goes without saying that the defect can be detected by applying the method.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIG. In FIG. 5, the same parts as those in the first embodiment described above are denoted by the same reference numerals, and the detailed description is omitted. In this embodiment, after the dilation processing and the erosion processing, the remaining images are totaled by the totalization processing circuit 14 and held in the totalization memory 15 to determine whether the defective pixel has a certain area or more. It is to determine. The tallying processing circuit 14 calculates the labeling process and the number of the detected images, and calculates the respective areas and positions, and writes the result in the tallying memory 15. The labeling process performed by the tallying processing circuit 14 is an operation for detecting an image group of continuous images, and is a prerequisite for area determination. When a defect image having a predetermined area or more is detected from the area data of each detected image group obtained in the counting memory 15 in this way, it is determined to be defective and output from the output unit 12. In this case, the determination process can be easily performed.

(Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG. In FIG. 6, the same parts as those in the above-described first embodiment are denoted by the same reference numerals, and detailed description is omitted. In this embodiment, an inspection information memory 16 is added to the second embodiment. Also, a plurality of feature extraction circuits 7A, 7B,... Having different inspection criteria such as feature extraction patterns even for the same search item are provided. The inspection information memory 16 changes an inspection condition and a feature extraction circuit to be used for each inspection region to be detected or for each pixel in the region among the detected binary images stored in the image memory 5. Things. As a result, the degree of the same inspection item can be changed in different areas. For example, regarding the detection of a chipped defect, the feature extraction pattern is changed so as to detect a shallow chipped defect in a certain area and a deep chipped defect in another area. .. Between the lines specified by the feature extraction circuits 7A, 7B,...
Detects patterns such as shorts. Further, the number of dilated pixels and reduced pixels may be arbitrarily selected. In this way, the rule serving as the inspection standard can be changed according to the location of the IC package to be detected.

In this case, as in the first embodiment,
A feature is extracted using the feature operator of each feature extraction circuit, and the expansion / contraction processing circuit 8 performs expansion / contraction processing. Then, as in the second embodiment, a labeling process is performed by the tallying processing circuit 14, the number, area, and position of the detected defective portions are calculated, written into the tallying memory 15, and the inspection result is determined from the data. Output. Further, the area value itself serving as a criterion for determining the quality of the inspection result may be changed. In this case, a threshold area value is written in the inspection information memory 16 for each inspection position or region. In this way, the defect can be detected flexibly according to the position of the pattern. In addition, when a heavy defect such as a short circuit is detected, the inspection condition can be set so that the defect is directly determined without performing the expansion / contraction processing. As a result, if a heavy defect is found, it can be determined as a defect without performing another inspection process, so that the process can be sped up.

[0026]

As described above in detail, according to the first to fourth aspects of the present invention, since the defect is detected by scanning the feature extraction pattern for the defect detection, the positional deviation of the inspection pattern is obtained. And the influence of relative displacement due to shrinkage of the substrate on which the pattern is formed can be eliminated. In addition, since the detected defects are expanded and contracted to connect the defects, isolated defect portions can be eliminated, and false reports can be reduced.

Further, according to the third aspect of the present invention, the labeling process is performed by the tallying unit, and the area of the defective pixel group is tallyed, so that the memory capacity can be reduced and the configuration can be further simplified. .

According to the fourth aspect of the present invention, since the inspection conditions are changed depending on the position of the pattern to be inspected, it is possible to set optimum conditions and sensitivity according to the position of the IC package or the like to be inspected. For this reason, it is possible to flexibly detect various defects such as disconnection, chipping, and projection of the pattern.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a pattern inspection apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a feature extraction operator used in the present embodiment.

FIG. 3 is a flowchart showing an operation of the pattern inspection apparatus according to the present embodiment.

FIG. 4 is a diagram showing a pattern showing an inspection process of the pattern inspection apparatus according to the present embodiment.

FIG. 5 is a block diagram showing a configuration of a pattern inspection device according to a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a pattern inspection apparatus according to a third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 IC package 2 Lighting 3 Camera 4 Preprocessing circuit 5 Image memory 6 Binarization circuit 7, 7A Feature extraction circuit 8 Expansion / contraction circuit 8 Judgment circuit 10 Area memory 11 Control CPU 12 Output unit 13 Operation unit 14 Aggregation processing circuit 15 Total memory 16 Test information memory

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2F065 AA49 AA56 AA58 BB02 CC01 CC25 DD06 DD07 FF42 FF61 HH12 HH14 JJ03 JJ09 JJ26 MM22 NN17 QQ03 QQ04 QQ08 QQ21 QQ23 QQ24 QQ31 QQ32 QQ36 QQ11 AE05 2A05 2A

Claims (4)

[Claims] 1. An imaging device for imaging an inspection pattern, a binarization unit for binarizing an image captured by the imaging device into a pattern part and another part, and a binary obtained from the binarization unit A defect detection unit that detects a defective pixel by scanning a predetermined feature extraction pattern on a converted image and detects a position of a matching image; and an expansion that expands the detected defective pixel by a first predetermined number of pixels. A reducing unit configured to reduce the image expanded by the expanding unit by the second number of pixels, and a determining unit configured to determine a pattern abnormality based on the size of the reduced defective image. Pattern inspection equipment. 2. The defect detection unit according to claim 1, wherein the defect detection unit detects only defective pixels by scanning only a predetermined inspection area in the binarized image captured and binarized. Pattern inspection equipment. 3. An image pickup device for picking up an inspection pattern, a binarizing unit for binarizing an image picked up by the image pickup device into a pattern part and another part, and a binary obtained from the binarizing unit. A defect detection unit that detects a defective pixel by scanning a predetermined feature extraction pattern on a converted image and detects a position of a matching image; and an expansion that expands the detected defective pixel by a first predetermined number of pixels. , A reducing unit for reducing the image expanded by the expansion unit by the second number of pixels, and performing a labeling process on the defective pixel group reduced by the reduction unit, and detecting a defect based on each area. A pattern inspection apparatus comprising: a totalization processing unit. 4. The defect detection section according to claim 1, wherein the area memory has a plurality of areas for setting an arbitrary image to be inspected with respect to the binarized image; An inspection information memory for holding defect detection information including the extracted feature extraction pattern, wherein a defective pixel is detected by scanning a feature extraction pattern set for each inspection area. The pattern inspection apparatus according to claim 1, wherein: