JP2001142089A - Electro-optical device - Google Patents

Abstract

(57) [Summary] In an electro-optical device such as a liquid crystal device, by reducing the alignment defect of a liquid crystal or the like due to a lateral electric field generated near the edge of a pixel electrode and reducing the resistance of a scanning line, a pixel is provided. And a high-quality image display with a high aperture ratio, high contrast, and high brightness. SOLUTION: A pixel electrode (9a) is provided on a TFT array substrate (10), and a counter electrode (2) is provided on a counter substrate (20).
1) is provided. The lower ground surface of the pixel electrode is a region opposed to a gap region between rows between adjacent pixel electrodes which are driven by driving potentials having opposite polarities at the time of 1H inversion driving, and includes a first conductive layer (81) and the like. It rises like a bank. The first conductive layer is made of the same film as the barrier layer (82) for relay connection between the pixel electrode and the TFT (30).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of electro-optical devices such as liquid crystal devices, and particularly employs a 1H inversion drive system in which a drive voltage polarity is periodically inverted for each pixel row along a scanning line. Thin Film Transisto
r: hereinafter appropriately referred to as TFT) belongs to the technical field of an electro-optical device such as an active matrix driving type liquid crystal device.

[0002]

2. Description of the Related Art Generally, in an electro-optical device such as a liquid crystal device, an electro-optical material such as a liquid crystal is sandwiched between a pair of substrates. It is defined by an alignment film formed on the material-side surface. Therefore, if there is a step on the surface of the pixel electrode under the alignment film or on the surface of the interlayer insulating film that is the ground below the pixel electrode, a step occurs on the surface of the alignment film, and depending on the degree of this step, the electro-optical material may Poor alignment (disclination) occurs. When such an orientation defect occurs, it is difficult to drive the electro-optical material satisfactorily in this portion, and the contrast ratio is reduced due to light leakage of the electro-optical device. However, in the case of a TFT active matrix driving type electro-optical device, various wirings such as scanning lines, data lines, capacitance lines, and TFTs for controlling switching of pixel electrodes are formed at various places on a TFT array substrate. Therefore, unless some kind of planarization treatment is performed, a step is inevitably generated on the surface of the alignment film depending on the existence of these wirings and elements.

Conventionally, a region on the substrate where such a step has occurred is made to correspond to a gap between adjacent pixel electrodes, and a light-shielding film provided on an opposing substrate or a TFT array substrate is used. By hiding the region where the pattern is generated, the electro-optical material portion which causes the alignment defect due to the step is not seen or does not contribute to the display light. Alternatively, conventionally, an interlayer insulating film beneath a pixel electrode is made of, for example, an organic SOG (Spin) so as to prevent a step itself due to the existence of such various wirings and TFTs.
A technology for flattening the ground below the pixel electrode by using a flattening film such as an On Glass film has also been developed.

On the other hand, generally, in this type of electro-optical device,
To prevent degradation of electro-optical material due to application of DC voltage, and to prevent crosstalk and flicker in displayed images,
An inversion driving method of inverting the voltage polarity applied to each pixel electrode according to a predetermined rule is adopted. During the display corresponding to the image signal of one frame or field, the pixel electrodes arranged in odd rows along the scanning lines are driven at a positive potential with reference to the potential of the counter electrode, and the scanning lines are driven. The pixel electrodes arranged in even rows along are driven with a negative potential with reference to the potential of the counter electrode, and during the subsequent display corresponding to the image signal of the next frame or field, the even The 1H inversion driving method in which the pixel electrodes arranged in rows are driven at a positive potential and the pixel electrodes arranged in odd rows are driven at a negative potential is relatively easy to control and provides high quality image display. Is used as an inversion driving method that makes it possible.

[0005]

However, according to the technique of covering the steps with a light-shielding film, the aperture area of the pixel becomes narrower in accordance with the area of the area having the steps. It is difficult to satisfy the basic requirement in the technical field of the electro-optical device that a brighter image display is performed by increasing the aperture ratio of the pixel in the display area. In particular, the number of wirings and the number of TFTs per unit area increase as the aperture ratio of fine pitch pixels for displaying high-definition images is increased.
This problem becomes more serious as electro-optical devices become more sophisticated because the ratio of areas having steps in the image display area becomes relatively high due to a certain limit in miniaturization of the image. Would.

On the other hand, according to the technique of flattening the interlayer insulating film below the pixel electrode, no particular problem arises when adjacent pixel electrodes on the TFT array substrate have the same polarity, When the voltages applied to the pixel electrodes adjacent to each other in the column direction along the data line have opposite polarities as in the 1H inversion driving method, the distance between the pixel electrode and the counter electrode is reduced by flattening the wiring or the like. In the vicinity of the edge of the pixel electrode located above the TFT, the width becomes wider than when the pixel electrode is not flattened. Therefore, a lateral electric field (that is, an electric field parallel to the substrate surface or a component parallel to the substrate surface) generated between adjacent pixel electrodes is reduced. (Inclined electric field) relatively increases. When such a horizontal electric field is applied to an electro-optical material in which it is assumed that a vertical electric field (that is, an electric field in a direction perpendicular to the substrate surface) between a pixel electrode and a counter electrode facing each other is applied. In addition, there arises a problem that poor alignment of the electro-optical material occurs, light leakage or the like occurs in this portion, and the contrast ratio decreases. In particular, as the distance between adjacent pixel electrodes is reduced due to the increase in aperture ratio of fine pitch pixels, such a transverse electric field is increased. It gets worse.

Further, by increasing the aperture ratio of such fine-pitch pixels, the line widths of the data lines and scanning lines themselves are also preferably reduced. It is necessary to allocate a lower resistance Al (aluminum) film or the like as a conductive film for formation, (ii) the scanning line has a portion that intersects with such a data line,
(iii) The scanning line is generally formed of a conductive polysilicon film because the scanning line is also used as a gate electrode of a thin film transistor. Therefore, when the scanning line width is reduced in accordance with the increase in the aperture ratio of the fine pitch pixels, or the driving frequency is increased in accordance with the increase in the definition, the size of the resistance or the time constant in the scanning line becomes a problem. It is becoming. That is, in this type of electro-optical device, since the scanning lines are formed from the conductive polysilicon film, it is not possible to cope with the high aperture ratio and the high definition of the fine pitch pixels,
There is also a problem that deterioration in image quality of a displayed image such as reduction in contrast ratio and occurrence of crosstalk and ghost due to the wiring resistance of the scanning line becomes apparent with an increase in the aperture ratio of fine pitch pixels.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is intended to reduce the poor orientation of an electro-optical material due to a lateral electric field generated near the edge of a pixel electrode, and at the same time to reduce the resistance of a scanning line. An object of the present invention is to provide an electro-optical device such as a liquid crystal device capable of displaying a high-quality image with a high aperture ratio, high contrast, and high brightness.

[0009]

In order to solve the above-mentioned problems, an electro-optical device according to the present invention comprises an electro-optical material sandwiched between a pair of first and second substrates.
A plurality of pixel electrodes, a plurality of intersecting data lines and a plurality of scanning lines, a plurality of thin film transistors respectively connected to the data lines and the scanning lines, and the scanning lines are overlapped with an interlayer insulating film; A plurality of first conductive lines formed along the scanning line for each of the pixel electrodes and connected to the scanning line via at least two contact holes separated along the scanning line, respectively; A counter electrode facing the pixel electrode on the second substrate, and a lower ground surface of the pixel electrode is raised in a convex shape in a region facing the first conductive layer.

According to the electro-optical device of the present invention, during operation, an image signal and a scanning signal are supplied to the thin film transistor via the data line and the scanning line, respectively, and each pixel electrode is driven. That is, the electro-optical device of the present invention is a TFT active matrix driving type electro-optical device. Here, in particular, as described below, the electro-optical device according to the present invention reduces the generation of a lateral electric field during the 1H inversion driving method in which the driving voltage polarity is inverted for each row of the pixel electrodes described above. It is configured to reduce malfunction of the substance.

That is, according to the electro-optical device of the present invention, the first conductive layers are respectively superposed on the scanning lines via the interlayer insulating film (that is, opposed to the scanning lines or below the scanning lines via the interlayer insulating film). Is arranged) and is divided for each pixel electrode along the scanning line, and in a region facing the first conductive layer,
The lower ground of the pixel electrode is raised in a convex shape according to the presence of the first conductive layer. Therefore, in a gap region between rows of pixel electrodes in a direction along a scanning line where a horizontal electric field is generated when driving is performed by the 1H inversion driving method, the lower ground of the pixel electrode is raised in a convex shape, and thus the substrate is raised. The gap between them is narrowed. Therefore, the vertical electric field generated between the edge portion of the pixel electrode and the counter electrode in the gap region between the rows of the pixel electrodes, which is substantially inversely proportional to the gap between the substrates, is relatively increased.
Conversely, the magnitude of the gap between the substrates and the lateral electric field generated between the edge portions of the pixel electrodes adjacent to each other via the gap region between the rows of the pixel electrodes have almost no relationship. The horizontal electric field is not strengthened even if it is narrowed in the gap region between the rows. As a result, the adverse effect of the horizontal electric field can be eliminated by locally strengthening the vertical electric field in the gap region between the pixel electrodes where the horizontal electric field is generated during the 1H inversion driving.

Further, according to the electro-optical device of the present invention, the first
Each of the conductive layers is formed so as to be divided for each pixel electrode along a scanning line. Here, since each first conductive layer is connected to the scanning line via at least two contact holes separated along the scanning line, each first conductive layer functions as a redundant wiring of the scanning line. It becomes possible. As a result, it is possible to reduce the resistance of the scanning line while reducing the scanning line width, particularly in accordance with the increase in the aperture ratio of the fine pitch pixels, thereby improving the contrast ratio and reducing the occurrence of crosstalk and ghost. It is possible to cope with high driving frequencies.

[0013] In addition, since the first conductive layer is divided for each pixel electrode, if a data line is formed in a gap region between columns of pixel electrodes, the data line and the first conductive layer overlap. Never. For this reason, in the gap region between the columns of the pixel electrodes, it is possible to avoid the situation where the base of the pixel electrode becomes thick due to the presence of the first conductive layer, and the presence of the first conductive layer hinders flattening near the data line. There is no. Further, in the gap region between the columns of the pixel electrodes, the first conductive layer and another conductive layer forming the data line or the thin film transistor may be in contact with each other (for example, the first conductive layer may be in contact with the first conductive layer in the gap region). The first conductive layer crosses another conductive layer made of the same film and having a function different from that of the redundant wiring of the scanning line, or the potential of the other conductive layer forming the thin film transistor is changed to the potential of the first conductive layer. A situation in which a ring or the like has an adverse effect) can also be avoided.

As a result, according to the electro-optical device of the present invention, it is possible to comprehensively reduce the poor orientation of the electro-optical material due to the transverse electric field and the poor orientation of the electro-optical material due to the step. Since the light-shielding film for concealing the defective alignment can be made smaller, the aperture ratio of each pixel can be increased without causing image defects such as light leakage, and at the same time, the resistance of the scanning line has been reduced. In addition, a bright, high-definition, high-quality image can be displayed with a high contrast ratio.

In one aspect of the electro-optical device according to the present invention, the thin film transistor and the pixel electrode are formed on the first substrate and are formed of the same film as the first conductive layer, and are stacked between the thin film transistor and the pixel electrode. The image display apparatus further includes a plurality of second conductive layers for relay connection with the pixel electrodes.

According to this aspect, as described above, the first conductive layer having the function of enhancing the vertical electric field in the region where the horizontal electric field is generated and the function of reducing the resistance of the scanning line, and the function of relay-connecting the thin film transistor and the pixel electrode Are made of the same film. For this reason, both having a plurality of functions can be simultaneously formed by the same process, which is very advantageous in a manufacturing process. Further, by using the second conductive layer in this way, even when the interlayer distance between the thin film transistor and the pixel electrode is long, the two can be connected with high reliability relatively easily and via a relatively small diameter contact hole. Become. Such a first conductive layer and a second conductive layer are made of at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). , Including a metal simple substance, an alloy, a metal silicide, and the like.

Alternatively, in another aspect of the electro-optical device according to the present invention, the first conductive layer is made of the same film as a conductive layer forming the data line.

According to this aspect, as described above, the first conductive layer having the function of increasing the vertical electric field in the region where the horizontal electric field is generated and the function of reducing the resistance of the scanning line, and the conductive layer forming the data line include: It consists of the same film. For this reason, both having a plurality of functions can be simultaneously formed by the same process, which is very advantageous in a manufacturing process. The first conductive layer and the conductive layer forming the data line are made of, for example, a metal such as Al. Since the first conductive layer is divided for each pixel electrode in the gap region between the rows of the pixel electrodes, if the data line is arranged in the gap region between the columns of the pixel electrodes, the data line and the first line are separated.
There is no overlap with the conductive layer.

Alternatively, in another aspect of the electro-optical device according to the present invention, the first conductive layer is formed of the same film as a conductive layer forming a part of the thin film transistor.

According to this aspect, as described above, the first conductive layer having the function of increasing the vertical electric field in the region where the horizontal electric field is generated and the function of reducing the resistance of the scanning line, and the conductive layer constituting a part of the thin film transistor Are formed from the same film, and therefore, both having a plurality of functions can be simultaneously formed by the same process, which is very advantageous in a manufacturing process. Such a first conductive layer and a conductive layer forming a part of the thin film transistor include:
For example, it is made of a polysilicon film or the like. Note that the first conductive layer is
Since a part of the thin film transistor is arranged in the gap region between the columns of the pixel electrodes, the conductive layer and the first conductive film constituting the part are separated from each other in the gap region between the pixel electrodes. The layers do not overlap.

Alternatively, in another aspect of the electro-optical device of the present invention, a conductive first light-shielding layer is further provided on the first substrate at a position covering at least a channel region of the thin film transistor as viewed from the first substrate side. The first conductive layer and the first light shielding layer are made of the same film.

According to this aspect, as described above, the first conductive layer having the function of increasing the vertical electric field in the region where the horizontal electric field is generated and the function of reducing the resistance of the scanning line, and the function of shielding the thin film transistor on the first substrate side Are formed of the same film. For this reason, both having a plurality of functions can be simultaneously formed by the same process, which is very advantageous in a manufacturing process. In addition, when the first light-shielding layer is used as described above, particularly in the case of a transmission-type electro-optical device, the characteristics of the thin film transistor are deteriorated due to a photoelectric effect in the back surface of the first substrate or a channel region based on return light from the projection optical system. Can be effectively prevented. The first conductive layer and the first light-shielding layer are made of, for example, a simple metal, an alloy, a metal silicide, or the like containing at least one of refractory metals such as Ti, Cr, W, Ta, and Mo. Note that the first conductive layer is divided for each pixel electrode in a gap region between rows of the pixel electrodes,
If the channel region of the thin film transistor and the first light-blocking layer are arranged in the gap region between the pixel electrode columns, the first light-blocking layer and the first conductive layer do not overlap.

In addition, by providing the same first conductive layer as the first light-shielding layer in the gap region between the rows of pixel electrodes, the first conductive layer allows the second conductive layer along the scanning line of the opening region of each pixel. An edge may be defined. On the other hand, the remaining two sides along the data line in the opening region of each pixel may be defined by a data line made of an Al film or the like. Accordingly, the light-shielding film for defining the opening area of each pixel may not be provided on the second substrate side, or the light-shielding film provided on the second substrate side may be used only for heat resistance to incident light in the electro-optical device. Alternatively, it may be a film that is set back a little from the opening region for improving the light resistance.

Alternatively, in another aspect of the electro-optical device according to the present invention, the first conductive layer is formed on the first substrate.
(i) the same film as a plurality of second conductive layers stacked between the thin film transistor and the pixel electrode and relay-connecting the thin film transistor and the pixel electrode, respectively; and (ii) a conductive layer forming the data line. The same film, (iii) the same film as the conductive layer constituting a part of the thin film transistor and (iv)
A conductive first electrode provided at a position covering at least a channel region of the thin film transistor as viewed from the first substrate side.
A layer composed of at least two films of the same film as the light-shielding layer is laminated.

According to this aspect, the same film as the above-described second conductive layer, the same film as the conductive layer forming the data line, the same film as the conductive layer constituting a part of the thin film transistor, the first conductive light-shielding layer Out of the same film, a first conductive layer having a three-dimensional structure in which a layer including at least two films is stacked. Accordingly, the redundant wiring structure above, below, or both above and below the scanning line makes it possible to more remarkably and surely lower the resistance of the scanning line. Further, by providing the first conductive layer composed of a plurality of layers in the gap region between the rows of the pixel electrodes as described above, the degree of freedom in the height and the shape when the lower ground of the pixel electrode is raised in a convex shape is advantageously increased. It is.

Alternatively, in another aspect of the electro-optical device of the present invention, the first conductive layer and the first conductive layer are formed on the first substrate.
(i) the same film as a plurality of second conductive layers stacked between the thin film transistor and the pixel electrode and relay-connecting the thin film transistor and the pixel electrode, respectively; and (ii) a conductive layer forming the data line. The same film, (iii) the same film as the conductive layer constituting a part of the thin film transistor and (iv)
A conductive first electrode provided at a position covering at least a channel region of the thin film transistor as viewed from the first substrate side.
By laminating a layer made of one or more films different from the first conductive layer in the same film as the light shielding layer, the lower ground of the pixel electrode is convex in a region opposed to the first conductive layer. It is lively.

According to this aspect, the same film as the above-mentioned second conductive layer, the same film as the conductive layer forming the data line, the same film as the conductive layer forming a part of the thin film transistor, the first conductive light-shielding layer And a layer made of one or more films different from the first conductive layer in the same film as the above, and the first conductive layer.
Therefore, in the gap region between the rows of the pixel electrodes, the degree of freedom in the height and shape of the raised portion when the lower ground of the pixel electrode is raised in a convex shape is advantageous.

In another aspect of the electro-optical device of the present invention, the at least two contact holes are provided at one end of the first conductive layer in a direction along the scanning line and at the other end. Including

According to this aspect, each of the first conductive layers is connected to the scanning line via the contact holes provided at both ends in the direction along the scanning line.
With the conductive layer, the resistance in the direction along the scanning line can be efficiently reduced.

In another aspect of the electro-optical device according to the present invention, the data line is at least partially embedded in a groove provided on the first substrate, and a lower ground of the pixel electrode is connected to the data line. The region facing the line is flattened.

According to this aspect, the data line is at least partially embedded in the groove provided on the first substrate, and the lower ground surface of the pixel electrode is flattened in a region facing the data line. I have. Therefore, if the data line is arranged in the gap region between the pixel electrodes where no horizontal electric field is generated during the 1H inversion driving, the step corresponding to the existence of the data line is reduced, and as a result, the electro-optic caused by the step in this region is reduced. Malfunction of the substance can be suppressed. That is, in a region where a lateral electric field is not generated, the gap between the substrates is locally narrowed to prevent the malfunction of the electro-optical material due to the lateral electric field, but the flattening of the electro-optical material due to the step is not performed. The malfunction is positively prevented.

When the groove is provided on the first substrate as described above, the groove may be dug in the upper surface of the first substrate, or may be formed in the interlayer insulating film below the data line on the first substrate. The trench may be dug, a trench may be formed in the interlayer insulating film by digging a trench on the upper surface of the first substrate and an interlayer insulating film having a constant thickness is formed thereon, or a combination of these trenches may be formed. Good.

The flattening by providing the grooves as described above can simplify the manufacturing process and improve the light resistance as compared with the case where the flattening is performed by a CMP process or the formation of an organic SOG film. This is advantageous in that no problems occur with respect to heat resistance.

In another aspect of the electro-optical device of the present invention, the thin film transistor is at least partially embedded in a groove provided on the first substrate, and a lower surface of the pixel electrode is connected to the thin film transistor. It is flattened in the facing region.

According to this aspect, the thin film transistor
The pixel electrode is at least partially buried in a groove provided on the first substrate, and a lower ground surface of the pixel electrode is flattened in a region facing the data line. Therefore, if the thin film transistor is arranged in the gap region between the pixel electrodes where no horizontal electric field is generated during the 1H inversion driving, the operation failure of the electro-optical material due to the step corresponding to the existence of the thin film transistor can be suppressed by the flattening. Can be.

When the groove is provided on the first substrate as described above, the groove may be formed in the upper surface of the first substrate, or may be formed in the interlayer insulating film below the thin film transistor on the first substrate. A groove may be formed in the interlayer insulating film by digging a groove on the upper surface of the first substrate and forming an interlayer insulating film having a constant film thickness thereon, or a combination of these grooves. .

In another aspect of the electro-optical device according to the present invention, the electro-optical device further includes a plurality of capacitance lines for providing storage capacitance to the plurality of pixel electrodes, respectively, on the first substrate, wherein the capacitance lines are at least provided. The pixel electrode is partially buried in a groove provided on the first substrate, and a lower ground surface of the pixel electrode is planarized in a region facing the capacitor line.

According to this aspect, by providing a storage capacitor to the pixel electrode by using the capacitor line, the voltage holding characteristic of the image signal at the pixel electrode is remarkably improved. Can be increased. And the capacitance line is at least partially
It is embedded in a groove provided on the substrate, and the lower ground of the pixel electrode is flattened in a region facing the capacitance line. Therefore, an operation failure of the electro-optical material due to a step corresponding to the presence of the capacitance line can be suppressed by the flattening.

When the groove is provided on the first substrate as described above, the groove may be dug in the upper surface of the first substrate, or the groove may be formed in the interlayer insulating film on the first substrate under the capacitor line. The trench may be dug, a trench may be formed in the interlayer insulating film by digging a trench on the upper surface of the first substrate and an interlayer insulating film having a constant thickness is formed thereon, or a combination of these trenches may be formed. Good.

In another aspect of the electro-optical device of the present invention, at least one of the first and second substrates is further provided with a second light-shielding film which overlaps a gap region between rows of the pixel electrodes when viewed in plan. .

According to this aspect, since the gap region between the rows of the pixel electrodes on which the scanning lines are formed is covered with the second light-shielding film, it is possible to prevent light leakage in this gap region and increase the contrast ratio. it can. Furthermore, the region where the electro-optical material is poorly aligned due to the lateral electric field and the step as described above can be hidden by the second light shielding film near the edge of the pixel electrode. Thus, the contrast ratio can be further increased. In particular, according to the present invention, as described above, the poor orientation of the electro-optical material due to the lateral electric field and the poor orientation of the electro-optical material due to the step are reduced in total. The ratio of the area to the entire image display area may be low. Therefore, the aperture ratio of each pixel is increased, and a bright and high-contrast image can be displayed.

In addition, for example, in the gap region between the rows of the pixel electrodes, the flattened capacitance line hardly causes poor alignment of the electro-optical material due to the step, so that the width is reduced by that much. It may be hidden by a narrow second light-shielding film. still,
For example, by providing a light-shielding film covering a thin film transistor formed in a gap region between columns of pixel electrodes, it is possible to prevent deterioration of transistor characteristics due to photocurrent generated in a semiconductor layer forming the thin film transistor due to incident light. (However, in order to prevent such deterioration of the characteristics of the transistor, at least the vicinity of the channel region of the thin film transistor is added to or instead of the second light-shielding film that defines the opening region of the pixel. It may be configured to provide a light shielding film that covers from the side). For example, in the case of a transmissive electro-optical device, a part or all of the second light-shielding film that defines the opening area of each pixel is formed on the first substrate by a pixel electrode, a thin film transistor, a scanning line, a data line, or the like. May be provided on a side closer to the first substrate than one of the conductive layers constituting the above. However, it is preferable that the light shielding for preventing the generation of the photocurrent of the thin film transistor be positively performed by the second light shielding film that defines the opening area of the pixel or by another light shielding film.

In the aspect having the second conductive layer, the at least two contact holes may be formed in the same step as a contact hole for connecting the second conductive layer and the thin film transistor.

With this structure, these contact holes can be formed in the same step, which is advantageous in manufacturing.

In another aspect of the electro-optical device according to the present invention, the first conductive layer comprises a light-shielding film.

According to this aspect, the first conductive layer formed of the light-shielding film can function as a built-in light-shielding film for defining an opening area of a pixel and for shielding a thin film transistor.

In this aspect, the first conductive layer and the data line may at least partially overlap.

According to this structure, the data line and the second line are formed at a position where the incident light easily enters the thin film transistor.
By at least partially overlapping the conductive layer, it is possible to more reliably prevent the incident light from entering the thin film transistor.

The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

[0050]

Embodiments of the present invention will be described below with reference to the drawings. In each of the following embodiments, the electro-optical device of the present invention is applied to a liquid crystal device.

(First Embodiment) The structure of an electro-optical device according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming an image display area of the electro-optical device. FIG. 2 is a plan view of a plurality of adjacent pixel groups on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed.
FIG. 4 is a plan view showing an excavated region of the groove on the TFT array substrate together with data lines and scanning lines.
5 is a cross-sectional view taken along the line BB 'in FIG. 2, FIG. 6 is a cross-sectional view taken along the line CC' in FIG.
FIG. 3 is a sectional view taken along line EE ′ of FIG. 2. FIG. 8 is a schematic plan view of a pixel electrode showing a potential polarity and a region where a lateral electric field is generated in each electrode in the 1H inversion driving method. FIG. FIG. 10 is a schematic cross-sectional view showing the state, and FIG. 10 is a schematic cross-sectional view showing the state of the alignment of liquid crystal molecules when a VA liquid crystal is used. In FIGS. 4 to 6, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawings.

In FIG. 1, a plurality of pixels formed in a matrix forming an image display area of the electro-optical device according to the present embodiment include a pixel electrode 9a and a TFT 30 for controlling the pixel electrode 9a in a matrix. A plurality of data lines 6a to which image signals are supplied are connected to the T
It is electrically connected to the source of FT30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. good. The scanning line 3a is connected to the gate of the TFT 30.
Are electrically connected to each other, and scan signals G1, G2,...
It is configured to apply in this order in a line-sequential manner. The pixel electrode 9a is electrically connected to the drain of the TFT 30. By closing the switch of the TFT 30, which is a switching element, for a certain period, the image signals S1, S2,... Write at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal as an example of the electro-optical material via the pixel electrode 9a are transmitted between the pixel electrode 9a and a counter electrode (described later) formed on a counter substrate (described later). For a certain period. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. In the normally white mode,
In accordance with the applied voltage, the incident light cannot pass through the liquid crystal portion. In the normally black mode, the incident light can pass through the liquid crystal portion in accordance with the applied voltage. Light having a contrast according to the image signal is emitted from the optical device. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode.

In this embodiment, driving is performed using the above-described 1H inversion driving method (see FIG. 8). This allows
It is possible to perform image display with reduced flicker occurring in a frame or field cycle and particularly reduced vertical crosstalk while avoiding deterioration of liquid crystal due to application of a DC voltage.

In FIG. 2, a plurality of transparent pixel electrodes 9 are arranged in a matrix on a TFT array substrate of the electro-optical device.
a (the outline is indicated by a dotted line portion 9a ′), and the data line 6a, the scanning line 3a, and the capacitor line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a. The data line 6a is electrically connected via a contact hole 5 to a source region described later in the semiconductor layer 1a made of, for example, a polysilicon film. The pixel electrode 9a is
By relaying a barrier layer 82 shown as an example of a conductive layer, which is indicated by a hatched area on the lower left in the figure, the semiconductor layer 1a is electrically connected to a drain region described later in the semiconductor layer 1a through contact holes 83 and 84. In addition, a channel region 1a ′ of the semiconductor layer 1a, which is indicated by a hatched region falling rightward in FIG.
The scanning line 3a is arranged so as to face the scanning line 3a, and the scanning line 3a functions as a gate electrode. As described above, pixel switching TFTs 30 in which the scanning lines 3a are opposed to each other as gate electrodes in the channel region 1a 'are provided at intersections of the scanning lines 3a and the data lines 6a.

The capacitance line 3b has a main line extending substantially linearly along the scanning line 3a, and a protruding portion protruding upward in the drawing along the data line 6a from a portion intersecting the data line 6a.

In the present embodiment, in particular, the first conductive layer 81 indicated by the hatched area on the lower left in the figure is formed so as to overlap the scanning line 3a and be divided along the scanning line 3a for each pixel electrode 9a. I have. As will be described later in detail, in a region facing the first conductive layer 81, the lower ground of the pixel electrode 9a is raised in a convex shape according to the presence of the first conductive layer 81. Each first conductive layer 81 is connected to the scanning line 3a via two contact holes 85 and 86 separated along the scanning line 3a, and each first conductive layer 81 serves as a redundant wiring for the scanning line 3a. Also works. Further, the first conductive layer 81 and the barrier layer 82 are made of the same film.

In FIG. 2, the TFT 30 is placed on the back side (TFT array substrate side) in each region along the scanning line 3b surrounded by a thick line.
The first light-shielding film 11a including a portion to be covered from is formed in a stripe shape along the main line portion of the scanning line 3a and the capacitance line 3b. The first light-shielding film 11a protrudes downward in the figure from a position facing the TFT 30 to a position covering the contact hole 5, and reliably shields the TFT 30 from return light.

As shown in FIG. 3, in addition to the configuration shown in FIG. 2, in the present embodiment, in particular, a region along each data line 6a including the data line 6a and each data line 6a including each TFT 30 and a capacitance line on the TFT array substrate. A mesh-like groove 201 is provided in a hatched region in the figure along 3b. As a result, a flattening process is performed on a part of the data line 6a, the TFT 30, and the capacitor line 3b. That is, in FIG. 2, each barrier layer 82, each data line 6a, and each TFT 3 excluding a rectangular area where the first conductive layer 81 is formed along each scanning line 3a.
A flattening process is performed on 0 and a part of the capacitance line 3b.

Next, as shown in the cross-sectional view of FIG. 4, the electro-optical device includes a transparent TFT array substrate 10 and a transparent opposing substrate 20 arranged to face the TFT array substrate. The TFT array substrate 10 is made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate. The pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrode 9a. The pixel electrode 9a is made of, for example, ITO (Indium Tin Oxid).
e) It consists of a transparent conductive thin film such as a film. Also, the alignment film 16
Is composed of an organic thin film such as a polyimide thin film.

On the other hand, a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode 21. I have. The counter electrode 21 is made of, for example, a transparent conductive thin film such as an ITO film. The alignment film 22 is made of an organic thin film such as a polyimide thin film.

Each pixel electrode 9 is provided on the TFT array substrate 10.
A pixel switching TFT 30 that controls switching of each pixel electrode 9a is provided at a position adjacent to the pixel electrode 9a.

As shown in FIG. 4, the opposing substrate 20 is further provided with a second light-shielding film 23 in a non-opening region of each pixel. Therefore, the incident light does not enter the channel region 1a ', the low-concentration source region 1b, and the low-concentration drain region 1c of the semiconductor layer 1a of the pixel switching TFT 30 from the counter substrate 20 side. Further, the second light shielding film 23
Has functions of improving contrast, preventing color mixture of color materials when a color filter is formed, and the like. In this embodiment, the light-shielding data line 6a made of Al or the like is used.
Thus, by shading the portion along the data line 6a in the non-opening region of each pixel, a contour portion along the data line 6a in the opening region of each pixel may be defined. May be configured such that the second light-shielding film 23 provided on the counter substrate 20 shields light from the non-opening region along the line redundantly or independently.

The space between the TFT array substrate 10 and the opposing substrate 20 having the above-described structure, in which the pixel electrode 9a and the opposing electrode 21 face each other, is provided in a space surrounded by a sealing material described later. Liquid crystal, which is an example of an optical material, is sealed, and a liquid crystal layer 50 is formed. The liquid crystal layer 50 has the alignment film 16 in a state where no electric field is applied from the pixel electrode 9a.
A predetermined orientation state is obtained by means of and. The liquid crystal layer 50
For example, it is composed of a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. The sealing material is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the TFT array substrate 10 and the opposing substrate 20 around them,
A gap material, such as glass fiber or glass beads, for adjusting the distance between the two substrates to a predetermined value is mixed.

In this embodiment, in particular, the TFT array substrate 10
The first light-shielding film 11a is formed thereon. The first light-shielding film 11a shields the return light from the back surface of the TFT array substrate 10 or the projection optical system, and the channel region 1 based on the light.
The photoelectric effect in a ′ effectively prevents the characteristics of the TFT 30 from deteriorating. Such a first light shielding film 11a
Is made of a simple metal, an alloy, a metal silicide, or the like containing at least one of high melting point metals such as Ti, Cr, W, Ta, and Mo. In particular, when a plurality of electro-optical devices are combined via a prism or the like to form a single optical system for a multi-plate type color projector application or the like, the projection light portion penetrating the prism or the like from another electro-optical device is used. Since the returning light is strong, the TFT
It is very effective to provide the first light shielding film 11a below 30.

Further, a base insulating film 12 is provided between the first light shielding film 11a and the pixel switching TFT 30. The base insulating film 12 is formed on the entire surface of the TFT array substrate 10 so that the T
It has a function of preventing contamination of the FT 30 and preventing deterioration of the characteristics of the pixel switching TFT 30 due to roughness at the time of polishing the surface of the TFT array substrate 10 or contamination remaining after washing. The base insulating film 12 is made of, for example, NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG
(Boron phosphorus silicate glass) or the like, or a silicon oxide film, a silicon nitride film, or the like.

In this embodiment, the semiconductor layer 1a extends from the high-concentration drain region 1e to form a first storage capacitor electrode 1f, and a part of the capacitor line 3b opposed to the first storage capacitor electrode 1f serves as a second storage capacitor electrode. The insulating thin film 2 including the film is connected to the scanning line 3a
The storage capacitor 70 is formed by extending from a position facing the first dielectric film and forming a first dielectric film sandwiched between these electrodes.

In FIG. 4, the pixel switching TFT
Reference numeral 30 denotes an LDD (Lightly Doped Drain) structure, and includes a scanning line 3a and a channel region 1 of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a.
a ', an insulating thin film 2 including a gate insulating film for insulating the scanning line 3a from the semiconductor layer 1a, a data line 6a, a low-concentration source region 1b and a low-concentration drain region 1c of the semiconductor layer 1a, and a high-concentration source of the semiconductor layer 1a. A region 1d and a high-concentration drain region 1e are provided. A corresponding one of the plurality of pixel electrodes 9a is relay-connected to the high-concentration drain region 1e by a barrier layer 82 via contact holes 83 and 84. Further, the scanning line 3a and the capacitance line 3b
A first interlayer insulating film 91 in which a contact hole 5 leading to the high-concentration source region 1d and a contact hole 83 leading to the high-concentration drain region 1e are respectively formed.

On the first interlayer insulating film 91, a barrier layer 82 for relay connection between the TFT 30 and the pixel electrode 9a via contact holes 83 and 84 is formed. As described above, since the high-concentration drain region 1e and the pixel electrode 9a are electrically connected to each other through the barrier layers 80a through the contact holes 83 and 84, one contact hole is opened from the pixel electrode 9a to the drain region. As compared with the case, the diameters of the contact holes 8a and 8b can be reduced. The barrier layer 82 is made of, for example, T
It is made of a simple metal, an alloy, a metal silicide, or the like containing at least one of high-melting metals such as i, Cr, W, Ta, and Mo. Thereby, good electrical connection can be established between the barrier layer 82 and the pixel electrode 9a via the contact hole 84. The thickness of the barrier layer 82 is preferably, for example, about 50 nm or more. If the thickness is about 50 nm, the possibility of penetration when the contact hole 84 is opened in the manufacturing process is reduced. The planar shape of each contact hole in the present embodiment may be a circle, a square, or another polygon, but the circle is particularly useful for preventing cracks in the interlayer insulating film and the like around the contact hole. Then, in order to obtain a good electrical connection, it is preferable that wet etching is performed after dry etching to slightly taper each of these contact holes.

On the barrier layer 82, the high-concentration source region 1
A second interlayer insulating film 4 in which a contact hole 5 leading to d and a contact hole 84 leading to a barrier layer 82 are formed, respectively.

The data lines 6 a are formed on the second interlayer insulating film 4, and a third interlayer insulating film 7 having a contact hole 84 to the barrier layer 82 formed thereon is formed thereon.
Are formed. The above-described pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 configured as described above.

As shown in FIG. 5, a data line 6a is provided in a non-opening region of each pixel located in a gap region between columns of pixel electrodes 9a adjacent to each other on the left and right in FIG. 6a, the data line 6 in the contour of the opening area of each pixel
The portion along the line a is defined, and light leakage in the non-opening region is prevented by the data line 6a.
A storage capacitor 70 is formed below the data line 6a by using a portion of the capacitor line 3b protruding below the data line 6a from a main line portion of the capacitor line 3b. Have been.

As shown in FIGS. 4 and 5, in the present embodiment, in particular, each data line 6a is formed on the TFT array substrate 10.
A groove 201 is provided in a plane area (see FIG. 3) facing each data line 6a including each TFT 30. Thereby, the data line 6a and the TFT 30 are subjected to the flattening process.

As shown in FIG. 6, a scanning line 3a and a capacitor line 3b are provided in a non-opening region of each pixel located in a gap region between rows of pixel electrodes 9a vertically adjacent to each other in FIG. First light-shielding film 1 provided on TFT array substrate 10
The portion along the scanning line 3a in the contour of the opening area of each pixel is defined by the first light-shielding film 23 provided on the counter substrate 20 and 1a, and light leakage in the non-opening area is prevented. .

As shown in FIGS. 4 and 6, in the present embodiment, the groove 201 is formed in a plane area (see FIG. 3) facing the scanning line 3a except for the gate electrode portion of the TFT 30 on the TFT array substrate 10. Not provided. On the other hand,
The groove 201 is provided in a plane region facing a part of the capacitance line 3b (main line portion along the edge near the scanning line 3a). That is, the flattening process is not performed on the scanning line 3a, and the ground below the pixel electrode 9a (in this embodiment, the surface of the third interlayer insulating film 7) is formed by the scanning line 3a and the first conductive layer 8
In the gap region between the rows of the pixel electrodes 9a in which 1 and the like are stacked and not flattened, the protrusions are raised like a bank, and a bank-shaped portion 301 is formed. Here, in particular, the first conductive layer 81 is formed on the scanning line 3a, and the barrier layer 82 is formed on the unflattened portion of the capacitor line 3b. 301
Is positively excited. in addition,
The first light-shielding film 11a is also formed in the gap region between the rows of the pixel electrodes 9a, and contributes to the bulging of the bank-shaped portion 301. The edge of the pixel electrode 9a is formed on the bank 301.

As shown in FIG. 7, in the present embodiment, in particular, the island-shaped first conductive layers 81 arranged along the scanning lines 3a are:
It is connected to the scanning line 3a via the contact holes 85 and 86, and functions as a redundant wiring for the scanning line 3a.
In addition to lowering the resistance of the scanning line 3a, it is also possible to prevent charge leakage due to generation of stray capacitance by fixing the first conductive layer 81 to the potential of the scanning line 3a.

These contact holes 85 and 86 are preferably formed in the same step as contact hole 83 (see FIG. 4) for connecting second conductive layer 82 and TFT 30. Further, in the present embodiment, the first conductive layer 81
Is composed of a light-shielding film, and is used for defining an opening area of a pixel or TF.
It functions as a built-in light shielding film for light shielding of T30. Also the first
The end of the conductive layer 81 and the edge of the data line 6a are slightly overlapped in a plan view, so that the entrance of the incident light to the TFT 30 can be more reliably prevented.

Referring now to FIG. 8, adjacent pixel electrodes 9 in the 1H inversion driving method employed in this embodiment.
The relationship between the voltage polarity a and the region where the lateral electric field is generated will be described.

That is, as shown in FIG. 8A, during the period of displaying the image signal of the n-th field or frame (where n is a natural number), the liquid crystal indicated by + or-for each pixel electrode 9a. The polarity of the driving potential is not inverted, and the pixel electrodes 9a are driven with the same polarity for each row. Thereafter, as shown in FIG. 8B, when displaying the image signal of the (n + 1) th field or one frame, the polarity of the liquid crystal driving potential in each pixel electrode 9a is inverted, and the image of the (n + 1) th field or one frame is displayed. During the signal display period, the polarity of the liquid crystal drive potential indicated by + or-is not inverted for each pixel electrode 9a, and the pixel electrodes 9a are driven with the same polarity for each row. Then, the states shown in FIGS. 8A and 8B are repeated at a cycle of one field or one frame, and the driving by the 1H inversion driving method in the present embodiment is performed. As a result, according to the present embodiment, image display with reduced crosstalk and flicker can be performed while avoiding deterioration of the liquid crystal due to the application of the DC voltage. The 1H inversion driving method is advantageous in that there is almost no vertical crosstalk as compared with the 1S inversion driving method. In the 1H inversion driving method according to the present invention, the polarity of the driving potential may be inverted for each row, or may be inverted for every two adjacent rows or for a plurality of rows.

As can be seen from FIGS. 8A and 8B, in the 1H inversion driving method, the horizontal electric field generation region C1 is always in the vicinity of the gap region between the rows of the pixel electrodes 9a adjacent to each other in the Y direction. Become.

In this embodiment, as shown in FIGS. 4 and 6, a bank-shaped portion 301 is formed.
The vertical electric field in the vicinity of the edge of the pixel electrode 9a disposed on the pixel 01 is strengthened. More specifically, as shown in FIG.
Narrow by the step. On the other hand, as shown in FIG.
The data line 6a has been subjected to a flattening process.
The distance d2 between the vicinity of the edge of the pixel electrode 9a and the counter electrode 21
Forms a groove 201 so as to be substantially equal to the distance D between the pixel electrode 9a and the counter electrode 21 in the central region occupying most of the pixel electrode. Here, the distance d between the vicinity of the edge of the pixel electrode 9a and the counter electrode 21 in the flattened portion
2 is d2 + between the liquid crystal layer thickness D in the light transmission region.
The relation of 300 nm ≧ D is established. That is, in a region where a lateral electric field is not generated, if a step of 300 nm or more is generated between the region and the layer thickness D of the liquid crystal, light leakage may occur.

Therefore, the horizontal electric field generation region C shown in FIG.
In 1, the vertical electric field between the pixel electrode 9a and the counter electrode 21 can be strengthened. And FIG.
In this case, even when the distance d1 is narrow, the gap W1 between the adjacent pixel electrodes 9a is constant, and thus the magnitude of the transverse electric field that increases as the gap W1 is narrowed is also constant. Therefore, the vertical electric field with respect to the horizontal electric field can be locally strengthened in the horizontal electric field generation area C1 shown in FIG. 8, and as a result, the vertical electric field becomes more dominant. In this case, poor alignment of the liquid crystal due to the lateral electric field can be prevented.

As shown in FIG. 5, since the data line 6a has been subjected to the flattening process, the liquid crystal alignment caused by the step due to the presence and absence of the data line 6a and the like in this portion. The occurrence of defects can be reduced. Here, since the flattening process is performed, the vertical electric field is not strengthened by reducing the distance d2 between the pixel electrode 9a and the counter electrode 21, but in this portion, as shown in FIG. No horizontal electric field is generated between the pixel electrodes 9a adjacent to each other. Therefore, in this portion, the alignment state of the liquid crystal can be extremely improved by the flattening treatment without taking measures against the lateral electric field.

As a result, according to the present embodiment, focusing on the characteristics of the lateral electric field generated in the 1H inversion driving method,
In the horizontal electric field generation region C1, by arranging the edge of the pixel electrode 9a on the bank-shaped portion 301, the vertical electric field is strengthened to reduce the adverse effect of the horizontal electric field, and at the same time, in the region where no horizontal electric field is generated, flattening is performed. By doing so, the pixel electrode 9a
Reduces adverse effects due to surface steps. As described above, by comprehensively reducing the alignment defect of the liquid crystal due to the lateral electric field and the alignment defect of the liquid crystal due to the step, the second light-shielding film 23 for hiding the defective alignment of the liquid crystal can be small (however, the bank-shaped portion). It is desirable to set the width of the second light-shielding film 23 to be slightly larger than the width of the bank-like portion 301 in order to cover a portion of the liquid crystal alignment defect caused by a step in the portion 301). Therefore, it is possible to increase the aperture ratio of each pixel without causing image defects such as light leakage, and finally, it is possible to display a bright, high-quality image with a high contrast ratio.

According to the study of the present inventor, the thickness of the liquid crystal layer 50 maintains the light resistance at a certain level, does not make the injection process of the liquid crystal 50 difficult, and the liquid crystal molecules are formed by the application of an electric field during operation. In order to work well,
A certain layer thickness (for example, about 3 μm according to the current technology) is required. On the other hand, the gap W1 between adjacent pixel electrodes 9a (see FIG. 6) is
a and shorter than the distance d1 between the counter electrode 21 (ie, W
It has been found that when 1 <d1), the adverse effect due to the lateral electric field starts to appear. Therefore, if the layer thickness D (see FIGS. 5 and 6) of the liquid crystal layer 50 is simply reduced as a whole in order to increase the aperture ratio of the fine pitch pixels, it becomes difficult to control the cell gap and to improve the light resistance. This causes a drop, a difficulty in an injection process, a malfunction of liquid crystal molecules, and the like. Conversely, in order to increase the aperture ratio of fine pitch pixels, the liquid crystal layer 5
If the gap W1 between the pixel electrodes 9a adjacent to each other is simply narrowed without reducing the value of 0, the horizontal electric field becomes larger than the vertical electric field, and thus the poor alignment of the liquid crystal due to the horizontal electric field becomes apparent. Considering the characteristics of such a liquid crystal device, the layer thickness d1 of the liquid crystal layer 50 (for example, 1.
The thickness D of the liquid crystal layer 50 in the light transmission region of the liquid crystal layer 50 is sufficiently reduced (for example, 3 μm) by reducing the thickness D of the liquid crystal layer 50 in the other region occupying most of the pixel electrode 9a while reducing the thickness to approximately 5 μm. The gap W1 between the pixel electrodes 9a adjacent to each other can be narrowed while ensuring a sufficient level of the horizontal electric field, while increasing the aperture ratio of the fine-pitch pixels and increasing the definition of the display image. It is very effective in planning.

In this embodiment, in particular, in FIG. 6, the pixel electrodes 9a are preferably arranged in a plane so as to satisfy the relationship of 0.5D <W1, and further satisfy the relationship of d1 + 300 nm (nanometer) .ltoreq.D. A bank 301 is formed. In other words, the distance between the pixel electrodes 9a is set so as not to be too close, and
If the height is raised to not less than nm, the vertical electric field in this region can be increased with respect to the horizontal electric field to such an extent that the adverse effect due to the horizontal electric field does not actually surface. Further, in order to increase the aperture ratio of the pixels with fine pitch and to increase the definition of the display image, it is effective to make the gap W1 and the gap W2 as small as possible. However, in order to prevent the adverse effect of the lateral electric field from becoming apparent. ,
This gap W1 cannot be reduced unnecessarily. Here, setting the gap W1 small until W1 ≒ d1 is most effective for increasing the aperture ratio of pixels with fine pitch without deteriorating image quality.

Further, in this embodiment, the pixel electrode 9 is formed on the edge of the bank-shaped portion 301 extending in the width direction on the upper surface extending in the longitudinal direction.
It is preferable that the edge of a is located. With this configuration, the distance d1 between the pixel electrode 9a and the counter electrode 21 at the edge can be shortened by making maximum use of the height of the bank-shaped portion 301. At the same time, the width W1 between adjacent pixel electrodes 9a where a horizontal electric field is generated can be reduced by making the most of the width of the upper surface of the bank-shaped portion 301. Thus, the vertical electric field can be strengthened in the horizontal electric field generation region C1 with respect to the horizontal electric field by utilizing the shape of the bank-like portion 301 very efficiently.

The above-described bank-shaped portion 301 is formed by using a scanning line 3a, a capacitor line 3b, a first conductive layer 81, a barrier layer 82, a second light-shielding film 23, a conductive film for forming the TFT 30, and an interlayer insulating film. Forming, but during the lamination process TF
A film for forming a bank is additionally formed locally between the T array substrate 10 and the pixel electrode 9a, or the surface of the TFT array substrate 10 is formed in a bank shape by etching or the like.
It is formed by forming the surface of an interlayer insulating film or the like interposed between the surface of the TFT array substrate 10 and the pixel electrode 9a into a bank shape by etching or the like. The cross-sectional shape of the bank-shaped portion 301 cut perpendicular to its longitudinal axis is, for example, trapezoidal, triangular, semi-circular, semi-elliptical, semi-circular or semi-elliptical in which the vicinity of the top is flat, or inclination of the side. Various shapes such as a quadratic curve, a cubic curve, a substantially trapezoidal shape, and a substantially triangular shape that gradually increase toward the top can be considered. Further, it is also possible to apply a flattening process only partially to the main line portions of the scanning lines 3a and the capacitance lines 3b shown in FIG. For example, these wirings are connected to the TFT array substrate 1
Alternatively, a bank-shaped portion having a desired height may be formed in a desired region by partially burying the groove in a groove formed in the interlayer insulating film. Therefore, in practice, it is desirable to appropriately adopt a cross-sectional shape that can reduce the alignment defect of the liquid crystal caused by the step according to the properties of the liquid crystal. At the same time, with respect to each film thickness that defines the height of the bank-like portion 301 such as the film thickness of the first conductive layer 81 and the film thickness of the first light-shielding film 11a, the bank-like portion 301 having a desired height is formed. It is desirable to set to.

On the other hand, as shown in FIGS. 2 and 6, according to the present embodiment, each of the first conductive layers 81 formed along the scanning line 3a and divided into the pixel electrodes 9a into a longitudinal shape is formed. Since it is connected to the scanning line 3a via the contact holes 85 and 86 which are spaced apart along the scanning line 3a when viewed in a plan view, it functions as a redundant wiring for the scanning line 3a, and particularly has a high aperture of a fine pitch pixel. It is possible to reduce the resistance of the scanning line 3a while reducing the width of the scanning line 3a as the efficiency increases. As a result, the contrast ratio can be improved, the occurrence of crosstalk and ghost can be reduced, and a high driving frequency can be handled. In particular, the two contact holes 85 and 8
6 is the scanning line 3 in each first conductive layer 81 when viewed in plan.
a is provided at both ends in the direction along
Due to the conductive layer 81, the scanning line 3a
Can be efficiently reduced in the direction along.
Note that three or more contact holes may be formed in each first conductive layer 81 along the direction of the scanning line.

In addition, the first conductive layer 81 is formed on the pixel electrode 9a.
Since the first conductive layer 81 is separated from each other, the data line 6a formed in the gap region between the columns of the pixel electrodes 9a does not overlap with the first conductive layer 81. For this reason, in the gap region between the columns of the pixel electrodes 9a, it is possible to avoid a situation where the ground below the pixel electrodes 9a (that is, the surface of the third interlayer insulating film 7) becomes thick due to the presence of the first conductive layer 81. Due to the presence of the conductive layer 81, the data line 6a
There is no hindrance to flattening in the vicinity (see FIG. 5). Further, in the gap region between the columns of the pixel electrodes 9a,
The first conductive layer 81 and the semiconductor layer 1a constituting the data line 6a and the TFT 30 do not adversely affect each other due to capacitive coupling or the like.

Here, as shown in FIG. 9B, in this embodiment, preferably, the liquid crystal layer 50 is formed of a TN (Twisted Nemati).
c) It is composed of liquid crystal, and the side surface of the bank portion 301 is tapered. In addition, the inclination direction of the pretilt angle θ and the inclination direction of the taper of the TN liquid crystal on the TFT array substrate 10 are matched. Here, “the tilt direction is adjusted” means that the liquid crystal layer thickness D
It is said that the inclination directions of these two coincide with each other to the extent that a very good liquid crystal alignment state can be obtained when the constant is constant, and the allowable range is appropriately determined experimentally, empirically, and theoretically. Determined.

That is, as shown in FIG. 9A, the liquid crystal molecules 50a of the TN liquid crystal have the respective liquid crystal molecules 5a when no voltage is applied.
The liquid crystal molecules 50a are oriented so as to be gradually twisted from the TFT array substrate 10 toward the opposing substrate 20 in a state where the liquid crystal molecules 50a are basically parallel to the substrate surface. It is oriented so as to stand vertically from the substrate surface. For this reason, as shown in FIG.
If the side surface of the bank-like portion 301 is tapered, and if the inclination direction of the pretilt angle θ of the TN liquid crystal and the inclination direction of the taper are matched, the gap between the bank-like portion 301 and the counter substrate 20 Even if the layer thickness d1 of the liquid crystal in FIG. 6 gradually decreases along the side surface, a favorable liquid crystal alignment state close to the case where the layer thickness D of the liquid crystal is constant can be obtained. That is, defective liquid crystal alignment caused by a step caused by the presence of the bank-shaped portion 301 for reducing defective liquid crystal alignment caused by the lateral electric field can be suppressed as much as possible. Assuming that FIG.
If the inclination direction of the pretilt angle θ of the TN liquid crystal and the inclination direction of the taper do not match as shown in (c), between the bank-like portion 301 and the counter substrate 20, there is no difference between the other liquid crystal molecules 50 a. Liquid crystal molecules 50 rising in the opposite direction
b is generated in the vicinity of the bank-shaped portion 301, and this causes a liquid crystal alignment defect in which the alignment state is discontinuous.
Therefore, such a region is preferably hidden by forming a light shielding film on the opposing substrate 20 or the TFT array substrate 10.

Alternatively, as shown in FIG. 10B, in the present embodiment, the liquid crystal layer 50 'is formed of a VA (Vertically Aligned).
d) A bank-shaped portion 301 'made of liquid crystal and not tapered may be provided.

That is, as shown in FIG. 10A, the VA liquid crystal is oriented so that each liquid crystal molecule 50a 'is basically in a state substantially perpendicular to the substrate surface when no voltage is applied.
In a region where the side surface of the bank-like portion exists in a plan view, the liquid crystal alignment must be disturbed.
If the side face of 01 ′ is not tapered, the liquid crystal portion where the orientation is disturbed on the side face can be minimized. Therefore, the portion of the pixel electrode 9a at a substantially flat location near the top of the bank-like portion 301 'and the bank-like portion 301'
10B, a good liquid crystal alignment state close to the case where the layer thickness D of the liquid crystal is constant in FIG. It is obtained as follows.

In the above-described embodiment, the flattening process is performed by digging the groove 201 in the TFT array substrate 10 and embedding the data line 6a.
Grooves may be dug in the first interlayer insulating film 91 and the second interlayer insulating film 4, or a step on the upper surface of the third interlayer insulating film 7 located above the data line 6 a or the like may be formed by CMP (Chemical Mechanical Polishing).
The flattening process may be performed by flattening by a shinging process or the like, or by flattening using an organic SOG.

In the embodiment described above, the pixel switching TFT 30 preferably has an LDD structure as shown in FIG. 4, but implants impurity ions into the low-concentration source region 1b and the low-concentration drain region 1c. A self-aligned TFT which has a high offset concentration and has a high concentration of source and drain regions formed in a self-aligned manner by implanting impurity ions at a high concentration using a gate electrode comprising a part of the scanning line 3a as a mask. You may. In this embodiment, the pixel switching TFT 3
Although only one gate electrode is disposed between the high-concentration source region 1d and the high-concentration drain region 1e, two or more gate electrodes may be disposed between them. When a TFT is formed with a dual gate or a triple gate or more as described above, a leak current at a junction between a channel and a source / drain region can be prevented, and a current in an off state can be reduced.

(Manufacturing Process of First Embodiment) Next, a manufacturing process of the TFT array substrate constituting the electro-optical device according to the first embodiment having the above-described configuration will be described with reference to FIG. . FIG. 11 is a process diagram showing each layer on the TFT array substrate side in each process corresponding to the BB ′ cross section of FIG. 2 and the CC ′ cross section of FIG. 2 as in FIGS. 5 and 6. .

First, as shown in step (a) of FIG. 11, a TF such as a quartz substrate, a hard glass substrate, a silicon substrate or the like is used.
A T-array substrate 10 is prepared, and a groove 201 is formed in a region where a data line 6a or the like is to be formed as shown in FIG. Subsequently, on the entire surface of the TFT array substrate 10, Ti, Cr, W,
A light-shielding film is formed from a high-melting point metal such as Ta or Mo by a sputtering process or a vapor deposition process, and then the first light-shielding film 11a having a plane pattern as shown in FIG. Form inside and outside of.

Next, as shown in step (b) of FIG. 11, the scanning lines 3a, the capacitance lines 3b, and the data lines 6a are formed on the TFT array substrate 10 by using a thin film forming technique.
In parallel with this, the TFT 30 and the storage capacitor 70 as shown in FIG. 4 are formed.

More specifically, a TEOS (Tetra.
Ethyl ortho silicate) gas, TEB
Ethyl boat rate) gas, TMOP (tetramethyl oxyfoslate) gas, etc.
Silicate glass films such as PSG, BSG, and BPSG;
A base insulating film 12 made of a silicon nitride film, a silicon oxide film, or the like and having a thickness of about 500 to 2000 nm is formed. Next, an amorphous silicon film is formed on the base insulating film 12 by low-pressure CVD or the like, and an annealing process is performed to grow a polysilicon film in a solid phase. Alternatively, a polysilicon film is directly formed by a low pressure CVD method or the like without passing through the amorphous silicon film. Next, a semiconductor layer 1a having a predetermined pattern including the first storage capacitor electrode 1f as shown in FIG. 2 is formed by subjecting the polysilicon film to a photolithography step, an etching step and the like. Next, the TF shown in FIG.
An insulating thin film 2 including a first dielectric film for forming a storage capacitor is formed together with the gate insulating film of T30. As a result, the thickness of the semiconductor layer 1a is about 30 to 150 nm, preferably about 35 to 50 nm, and the thickness of the insulating thin film 2 is
About 20-150 nm thickness, preferably about 30-100
nm in thickness. Next, a polysilicon film is deposited to a thickness of about 100 to 500 nm by a low pressure CVD method or the like, and P (phosphorus) is thermally diffused to make the polysilicon film conductive. Thus, the scanning lines 3a and the capacitance lines 3b having a predetermined pattern as shown in FIG. 2 are formed. Note that the scanning line 3a and the capacitance line 3b
May be formed of a metal alloy film such as a refractory metal or a metal silicide, or may be a multilayer wiring in combination with a polysilicon film or the like. Next, by doping impurity ions in two steps of low concentration and high concentration, the low concentration source region 1b, the low concentration drain region 1c, and the high concentration source region 1c are doped.
The pixel switching TFT 30 having the LDD structure, including d and the high-concentration drain region 1e, is formed.

Note that, in parallel with the step (b) in FIG.
Peripheral circuits such as a data line driving circuit and a scanning line driving circuit composed of T may be formed in a peripheral portion on the TFT array substrate 10.

Next, as shown in step (c) of FIG. 11, a first interlayer insulating film 91 made of a high-temperature silicon oxide film (HTO film) or a silicon nitride film is formed on the entire surface by a low pressure CVD method, a plasma CVD method or the like. accumulate. At this time, in order to construct an additional storage capacitor between the barrier layer 82 and the storage capacitor electrode 1f, the first interlayer insulating film 91 functioning as a dielectric between the two is formed by a relatively thin film having a thickness of about 200 nm or less. May be deposited. Alternatively, if such an additional storage capacitor is unnecessary, the first interlayer insulating film 91 may be deposited to a thickness of about 200 to 1000 nm. However, the first interlayer insulating film 91
May be formed of a multilayer film, or the first interlayer insulating film 91 can be formed by various known techniques generally used for forming a gate insulating film of a TFT.

The first interlayer insulating film 91 thus formed
A contact hole 82 for electrically connecting the barrier layer 82 and the high-concentration drain region 1e of the semiconductor layer as shown in FIGS. At the same time, the scanning line 3a
And contact holes 85 and 86 for electrically connecting the first conductive layer 81 to the first conductive layer 81. After opening these contact holes, the first conductive layer 81 and the barrier layer 82 having a predetermined thickness are formed from the same film so that the height of the bank-like portion 301 becomes a desired height as described above. . For example, as in the case of the first light shielding film 11a, Ti, Cr, W, T
A conductive film is formed from a high melting point metal such as a or Mo by a sputtering process or a vapor deposition process, and then the first conductive layer 81 and the barrier layer 82 as shown in FIG. It is formed at a predetermined position inside and outside of.

Then, NSG, PSG, etc. are applied using a normal pressure or reduced pressure CVD method, a TEOS gas, or the like, so as to cover the stacked body including the first conductive layer 81, the barrier layer 82, and the first interlayer insulating film 91. , A second interlayer insulating film 4 made of a silicate glass film such as BSG or BPSG, a silicon nitride film, a silicon oxide film, or the like. The second interlayer insulating film 4
For example, the thickness is about 1000 to 2000 nm.
Note that, in parallel with or before or after this thermal baking, an annealing process at about 1000 ° C. may be performed to activate the semiconductor layer 1a. Then, a contact hole 5 for electrically connecting the data line 6a shown in FIG. 4 to the high concentration source region 1d of the semiconductor layer 1a is formed in the second interlayer insulating film 4 and the insulating thin film 2. At the same time, a contact hole 84 for electrically connecting the barrier layer 82 and the pixel electrode 9a as shown in FIGS. 2 and 4 may be partially formed. Further, a contact hole for connecting the scanning line 3a or the capacitance line 3b to a wiring (not shown) in the peripheral region of the substrate can be formed in the same process as the contact holes 5 and 84.

Next, as shown in step (d) of FIG. 11, the second interlayer insulating film 4 is formed on the second interlayer insulating film 4 by sputtering or the like.
A low resistance metal film such as Al or a metal silicide film
After being deposited to a thickness of 500 nm, a data line 6a having a plane pattern as shown in FIG. 2 is formed by a photolithography process, an etching process, and the like.

Subsequently, a third interlayer insulating film 7 is formed on data line 6a. Further, as shown in FIG. 4, a contact hole 83 for electrically connecting the pixel electrode 9a and the barrier layer 82 is formed by dry etching such as reactive ion etching, reactive ion beam etching, or wet etching. I do. Subsequently, a transparent conductive thin film such as an ITO film is deposited on the third interlayer insulating film 7 to a thickness of about 50 to 200 nm by a sputtering process or the like, and further, a pixel is formed by a photolithography process and an etching process. An electrode 9a is formed. When the electro-optical device is used as a reflection type, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al. Finally, the entire surface including the pixel electrode 9a is formed from an organic thin film such as a polyimide thin film by spin coating or the like, and then subjected to a predetermined rubbing treatment.

As described above, according to the manufacturing method of the present embodiment, the trench 201 is dug in the TFT array substrate 10 to perform the flattening process on the data line 6a, and to provide a part of the scanning line 3a and the capacitor line 3b. On the other hand, since no flattening process is performed, the liquid crystal alignment defect due to the step is reduced in the region where the horizontal electric field does not occur, and the bank-like portion 30 is formed in the region where the horizontal electric field is generated.
1, the liquid crystal device of the first embodiment that reduces the liquid crystal alignment failure due to the lateral electric field can be manufactured relatively easily. In this case, in particular, the first conductive layer 81 having a function of strengthening the vertical electric field in the region where the horizontal electric field is generated and a function of lowering the resistance of the scanning line 3a;
Since the barrier layer 82 having a function of relay connection between the FT 30 and the pixel electrode 9a is formed of the same film, both can be formed simultaneously by the same process.

(Second Embodiment) Next, a second embodiment of the electro-optical device of the present invention will be described with reference to FIG. Here, FIG. 12 is a sectional view taken along the line CC ′ of FIG. 2 shown in FIG.
FIG. 10 is a cross-sectional view of the electro-optical device according to the second embodiment at a location corresponding to a cross-section. In FIG. 12, the same components as those in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted.

As shown in FIG. 12, in the second embodiment,
Instead of the first conductive layer 81 and the barrier layer 82 made of a refractory metal film laminated between the first interlayer insulating film 91 and the second interlayer insulating film 4 in the first embodiment, the second interlayer insulating film 4 and the second The point that the first conductive layer 81 ′ and the barrier layer 82 ′ which are laminated between the three interlayer insulating films 7 and are made of the same Al film as the data line 6 a are provided, and the first interlayer insulating film 91 is omitted. The points are different from those of the first embodiment, and the other configurations are the same as those of the first embodiment.

Therefore, as in the first embodiment, the first conductive layer 81 'having the function of increasing the vertical electric field in the horizontal electric field generation region and the function of lowering the resistance of the scanning line 3a, and the TFT 3
Since the barrier layer 82 'having the function of relaying connection between the pixel electrode 9a and the data line 6a is formed of the same film, these three layers can be formed simultaneously by the same process. This is very advantageous in the manufacturing process. Since the first conductive layer 81 'is divided for each pixel electrode 9a in the gap region between the rows of the pixel electrodes 9a, the first conductive layer 81' is connected to the data line 6a disposed in the gap region between the columns of the pixel electrodes 9a and the first conductive layer 81 '. Layer 8
1 'does not overlap.

In the first embodiment described above, the first conductive layer 81 and the barrier layer 82 are formed of the same layer. In the second embodiment, the first conductive layer 81 ′, the barrier layer 82 ′, and the data line 6a are Are formed of the same film, but the first conductive layer 81 may be formed of the same film as the other conductive layers. Further, the laminated structure for defining the height of the bank-like portion 301 also
Other than those shown in the first and second embodiments may be used. For example, the first line which is connected to the scanning line 3 a by a contact hole to reduce the resistance and constitute the bank-like portion 301.
The conductive layer is formed by laminating a plurality of films out of a barrier layer, a data line, a conductive layer forming part of a TFT, and the first light-shielding film, and the plurality of films are electrically connected to each other by contact holes. You may comprise so that it may be. With this configuration, it is also possible to further reduce the resistance of the scanning line. At the same time, with this configuration, the pixel electrode 9
The degree of freedom regarding the height and shape when the lower ground a is raised in a convex shape is also increased. Or barrier layer, data line, TFT
Of the conductive layer and the first light-blocking layer that constitute a part of the first conductive layer, one or more films different from the first conductive layer (that is, not connected to the first conductive layer through the contact hole) and the first conductive layer The lower ground of the pixel electrode 9a is
You may comprise so that it may be raised in the convex shape in the area | region facing a conductive layer. Even with such a configuration, the degree of freedom in height and shape when the lower ground of the pixel electrode 9a is raised in a convex shape also increases.

(Overall Configuration of Electro-Optical Device) The overall configuration of the electro-optical device in each embodiment configured as described above will be described with reference to FIGS. Note that FIG.
FIG. 14 is a plan view of the TFT array substrate 10 together with the components formed thereon viewed from the counter substrate 20 side, and FIG. 14 is a cross-sectional view taken along the line HH ′ of FIG.

In FIG. 13, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and is made of, for example, the same or different material as the second light shielding film 23 in parallel with the inside thereof. A third light-shielding film 53 is provided as a frame defining the periphery of the image display area. A data line driving circuit 101 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing and an external circuit connection terminal 1 are provided in a region outside the sealing material 52.
02 is provided along one side of the TFT array substrate 10, and supplies a scanning signal to the scanning line 3a at a predetermined timing to drive the scanning line 3a.
4 are provided along two sides adjacent to this one side. If the delay of the scanning signal supplied to the scanning line 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. In addition, the data line driving circuit 10
1 may be arranged on both sides along the side of the image display area.
For example, the odd-numbered data lines supply image signals from a data line driving circuit disposed along one side of the image display area, and the even-numbered data lines extend along the opposite side of the image display area. The image signal may be supplied from the data line driving circuit provided. By driving the data lines 6a in a comb-tooth shape in this manner, the area occupied by the data line driving circuit 101 can be expanded, so that a complicated circuit can be configured. Further, on the remaining one side of the TFT array substrate 10, a plurality of wirings 105 for connecting between the scanning line driving circuits 104 provided on both sides of the image display area are provided. In at least one corner of the counter substrate 20, a conductive material 10 for electrically connecting the TFT array substrate 10 and the counter substrate 20 is provided.
6 are provided. Then, as shown in FIG. 14, the counter substrate 20 having substantially the same contour as the sealing material 52 shown in FIG.
It is stuck to.

Note that, on the TFT array substrate 10, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, a sampling circuit for applying an image signal to the plurality of data lines 6a at a predetermined timing, a plurality of Data line 6a
A precharge circuit for supplying a precharge signal of a predetermined voltage level prior to the image signal, an inspection circuit for inspecting the quality, defects, and the like of the electro-optical device during manufacturing or shipping. Good.

In each of the embodiments described above with reference to FIGS. 1 to 14, instead of providing the data line drive circuit 101 and the scan line drive circuit 104 on the TFT array substrate 10, for example, TAB (Tape Automated Bonding) The driving LSI mounted on the substrate may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. For example, the TN mode, V
A-mode, PDLC (Polymer Dispersed Liquid Crysta
l) A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as a mode or a normally white mode / normally black mode.

Since the electro-optical device in each of the embodiments described above is applied to a projector which is a projection type display device, three electro-optical devices are used as RGB light valves, and each light valve has The light of each color separated via the dichroic mirror for RGB color separation is respectively incident as projection light. Therefore, in each embodiment, the opposing substrate 20 is not provided with a color filter. However, in a predetermined region facing the pixel electrode 9a where the second light shielding film 23 is not formed, the R
The counter substrate 2 is provided with a GB color filter together with its protective film.
It may be formed on zero. In this way, the electro-optical device in each embodiment can be applied to a direct-view or reflective color electro-optical device other than the liquid crystal projector. Further, a micro lens may be formed on the counter substrate 20 so as to correspond to one pixel. Alternatively, the TFT array substrate 10
It is also possible to form a color filter layer with a color resist or the like below the pixel electrode 9a facing the upper RGB. By doing so, by improving the light collection efficiency of the incident light,
A bright electro-optical device can be realized. Furthermore, a dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with the dichroic filter, a brighter color electro-optical device can be realized.

(Configuration of Electronic Apparatus) An electronic apparatus using the electro-optical device of the above-described embodiment includes a display information output source 1000, a display information processing circuit 1002, a display drive circuit 1004, and an electro-optical device shown in FIG. The device includes a device 100, a clock generation circuit 1008, and a power supply circuit 1010. The display information output source 1000 includes a memory such as a ROM or a RAM, a tuning circuit for tuning and outputting a television signal, and the like, and outputs display information such as a video signal based on a clock from a clock generation circuit 1008. I do. The display information processing circuit 1002 includes a clock generation circuit 1
The display information is processed and output based on the clock from 008. The display information processing circuit 1002 can include, for example, an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, a clamp circuit, and the like. The display driving circuit 1004 includes a scanning side driving circuit and a data side driving circuit, and drives the liquid crystal panel 1006 for display. The power supply circuit 1010 supplies power to each of the above circuits.

As an electronic apparatus having such a configuration, FIG.
And a personal computer (PC) and an engineering workstation (EWS) compatible with multimedia shown in FIG.

FIG. 16 is a schematic configuration diagram showing a main part of the projection display device. In the figure, 1102 is a light source, 1108 is a dichroic mirror, 1106 is a reflection mirror, 1122
Is an entrance lens, 1123 is a relay lens, 1124 is an exit lens, 100R, 100G, and 100B are liquid crystal light modulators, which are the electro-optical devices described in the above embodiments, 1112 is a cross dichroic prism, 111
Reference numeral 4 denotes a projection lens. The light source 1102 includes a lamp such as a metal halide and a reflector that reflects light from the lamp. Dichroic mirror 110 that reflects blue light and green light
Reference numeral 8 transmits red light of the light flux from the light source 1102 and reflects blue light and green light. The transmitted red light is reflected by the reflection mirror 1106 and is incident on the liquid crystal light modulator for red light 100R. On the other hand, the green light among the color lights reflected by the dichroic mirror 1108 is reflected by the green light reflecting dichroic mirror 1108 and is incident on the liquid crystal light modulator for green light 100G.
On the other hand, the blue light also passes through the second dichroic mirror 1108. For blue light, an incident lens 1122 and a relay lens 112 are used to prevent light loss due to a long optical path.
3. A light guiding means 1121 composed of a relay lens system including an emission lens 1124 is provided, through which blue light is incident on the liquid crystal light modulation device 100B for blue light. The three color lights modulated by the respective light modulators enter the cross dichroic prism 1112. This prism is formed by bonding four right-angle prisms, and a dielectric multilayer film that reflects red light and a dielectric multilayer film that reflects blue light are formed in a cross shape on the inner surface. With these dielectric multilayer films, 3
The two color lights are combined to form light representing a color image. The combined light is transmitted through a projection lens 11 as a projection optical system.
The image is projected on a screen 1120 by 14 and the image is enlarged and displayed.

The personal computer 12 shown in FIG.
00 is a main body 1204 having a keyboard 1202
And a liquid crystal display screen 1206 using the electro-optical device described in the above embodiment.

As described in detail above, according to the present embodiment, it is possible to reduce the resistance of the wiring such as the scanning line 3a without increasing the number of special manufacturing steps, and it is possible to form various light-shielding films on the TFT array substrate 10. It is also possible to incorporate it on the side,
An image with a high contrast ratio can be displayed.

The present invention is not limited to the above-described embodiments, but can be appropriately modified without departing from the spirit and spirit of the invention which can be read from the claims and the entire specification. Such an electro-optical device is also included in the technical scope of the present invention.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements, wiring, and the like provided in a plurality of pixels in a matrix forming an image display area in an electro-optical device according to a first embodiment of the present invention.

FIG. 2 is a plan view of a plurality of adjacent pixel groups of a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the electro-optical device according to the first embodiment.

FIG. 3 is a plan view showing an excavated region of a groove on a TFT array substrate together with a data line and a scanning line in the electro-optical device according to the first embodiment.

FIG. 4 is a sectional view taken along line A-A 'of FIG.

FIG. 5 is a sectional view taken along line B-B 'of FIG.

FIG. 6 is a sectional view taken along line C-C 'of FIG.

FIG. 7 is a sectional view taken along line E-E 'of FIG.

FIG. 8 is a schematic plan view of a pixel electrode showing a voltage polarity and a region where a lateral electric field is generated in each electrode in the 1H inversion driving method used in the first embodiment.

FIG. 9 is a schematic cross-sectional view illustrating a state of alignment of liquid crystal molecules when a TN liquid crystal is used in the first embodiment.

FIG. 10 is a schematic cross-sectional view showing a state of alignment of liquid crystal molecules when a VA liquid crystal is used in the first embodiment.

FIG. 11 is a process diagram sequentially illustrating a manufacturing process of the electro-optical device according to the first embodiment.

FIG. 12 is a plan view of a plurality of adjacent pixel groups on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in an electro-optical device according to a second embodiment of the present invention.

FIG. 13 is a plan view of a TFT array substrate in the electro-optical device according to each embodiment, together with components formed thereon, viewed from a counter substrate side.

FIG. 14 is a sectional view taken along line H-H ′ of FIG.

FIG. 15 illustrates an example of an electronic apparatus including the electro-optical device according to the embodiment.

FIG. 16 illustrates a projection display device as an example of an electronic apparatus.

FIG. 17 illustrates a personal computer as an example of an electronic apparatus.

[Explanation of symbols]

 1a Semiconductor layer 1a 'Channel region 1b Low-concentration source region 1c Low-concentration drain region 1d High-concentration source region 1e High-concentration drain region 1f First storage capacitor electrode 2 Insulating thin film 3a Scanning line 3b Capacitance line 4 Second interlayer insulating film 5 Contact hole 6a Data line 7 Third interlayer insulating film 8 Contact hole 9a Pixel electrode 10 TFT array substrate 12 Base insulating film 16 Alignment film 20 Counter substrate DESCRIPTION OF SYMBOLS 21 ... Counter electrode 22 ... Orientation film 23 ... Second light-shielding film 30 ... Pixel switching TFT 50 ... Liquid crystal layer 50a ... Liquid crystal molecules 70 ... Storage capacitance 81 ... First conductive layer 82 ... Barrier layers 83, 84, 85, 86 ... Contact hole 201 ... groove 301 ... bank-shaped part

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) H01L 29/786 H01L 29/78 612C 21/336 619B 627A F term (reference) 2H090 HA04 HB03X HB06X HC03 HC05 HC09 HC10 HD03 HD07 JA03 JC03 LA01 2H092 JA25 JA46 JB04 JB23 JB24 JB32 JB33 JB58 JB64 JB66 KA04 KA07 KB22 KB25 MA05 MA07 MA13 MA18 NA04 NA28 PA01 PA02 PA09 5C094 AA06 AA10 BA03 BA43 CA19 DA13 EA03 EA04 EA07 FA02 DD05 DD05 EE04 EE05 EE09 EE14 EE45 FF02 FF23 GG02 GG13 GG25 GG47 HJ01 HJ15 HJ23 HL03 HL04 HL05 HL06 HL14 HL23 HM15 NN03 NN04 NN22 NN23 NN24 NN25 NN26 NN35 NN40 QNN NN46 NN45 NN46

Claims (15)

[Claims] An electro-optical material is sandwiched between a pair of first and second substrates, and a plurality of pixel electrodes, a plurality of intersecting data lines and a plurality of scanning lines are provided on the first substrate. A plurality of thin film transistors respectively connected to the data line and the scanning line; and a plurality of thin film transistors which are overlapped on the scanning line via an interlayer insulating film and are formed separately for each of the pixel electrodes along the scanning line. And a plurality of first conductive layers respectively connected to the scanning lines via at least two contact holes separated along the scanning lines, and opposing the pixel electrodes on the second substrate. And an electrode, wherein a lower ground of the pixel electrode is raised in a convex shape in a region facing the first conductive layer. 2. A plurality of films comprising the same film as the first conductive layer on the first substrate, each of which is laminated between the thin film transistor and the pixel electrode, and which relay-connects the thin film transistor and the pixel electrode, respectively. The electro-optical device according to claim 1, further comprising a second conductive layer. 3. The semiconductor device according to claim 1, wherein the first conductive layer is formed of the same film as a conductive layer forming the data line.
An electro-optical device according to claim 1. 4. The electro-optical device according to claim 1, wherein the first conductive layer is formed of the same film as a conductive layer forming a part of the thin film transistor. 5. A method according to claim 1, further comprising a conductive first light shielding layer on the first substrate at a position covering at least a channel region of the thin film transistor as viewed from the first substrate side. The electro-optical device according to claim 1, wherein the light-shielding layer is made of the same film. 6. The first conductive layer (i) formed on the first substrate, being stacked between the thin film transistor and the pixel electrode, and relaying the thin film transistor and the pixel electrode respectively. (Ii) the same film as the conductive layer forming the data line, (ii) the same film as the second conductive layer
i) the same film as the conductive layer forming a part of the thin film transistor, and (iv) the same film as the conductive first light shielding layer provided at a position covering at least the channel region of the thin film transistor as viewed from the first substrate side. 2. The device according to claim 1, wherein at least two layers are laminated.
An electro-optical device according to claim 1. 7. The first conductive layer, and a plurality of (i) stacked on the first substrate, which are stacked between the thin film transistor and the pixel electrode, and which relay-connect the thin film transistor and the pixel electrode, respectively. (Ii) the same film as the conductive layer forming the data line, (ii) the same film as the second conductive layer
i) the same film as the conductive layer forming a part of the thin film transistor, and (iv) the same film as the conductive first light shielding layer provided at a position covering at least the channel region of the thin film transistor as viewed from the first substrate side. Wherein a layer made of one or more films different from the first conductive layer is stacked, so that the lower ground of the pixel electrode is raised in a convex shape in a region facing the first conductive layer. The electro-optical device according to claim 1, wherein: 8. The method according to claim 1, wherein the at least two contact holes include one provided at one end of the first conductive layer in a direction along the scanning line and one provided at the other end. The electro-optical device according to claim 1. 9. The data line is at least partially embedded in a groove provided on the first substrate, and a lower ground surface of the pixel electrode is flattened in a region facing the data line. The electro-optical device according to any one of claims 1 to 8, wherein: 10. The thin film transistor is at least partially buried in a groove provided on the first substrate, and a lower ground surface of the pixel electrode is planarized in a region facing the thin film transistor. The electro-optical device according to claim 1, wherein: 11. The semiconductor device further comprising a plurality of capacitance lines for providing storage capacitance to the plurality of pixel electrodes, respectively, on the first substrate, wherein the capacitance lines are provided at least partially on the first substrate. 11. The electro-optical device according to claim 1, wherein the lower surface of the pixel electrode is buried in a groove, and a lower surface of the pixel electrode is flattened in a region facing the capacitance line. 12. apparatus. 12. The apparatus according to claim 1, further comprising a second light shielding film on at least one of the first and second substrates, the second light shielding film overlapping a gap region between rows of the pixel electrodes when viewed in plan. The electro-optical device according to any one of claims 11 to 11. 13. The electro-optical device according to claim 2, wherein the at least two contact holes are formed in the same step as a contact hole for connecting the second conductive layer and the thin film transistor. apparatus. 14. The electro-optical device according to claim 1, wherein the first conductive layer is made of a light-shielding film. 15. The first conductive layer and the data line,
The electro-optical device according to claim 14, wherein the electro-optical device is at least partially overlapped.