JP2002182238A - Electro-optical device and method of manufacturing the same, substrate device and method of manufacturing the same - Google Patents

Abstract

Abstract: PROBLEM TO BE SOLVED: To hardly generate unevenness in an upper layer of a laminated structure at a connection point and its periphery between a wiring, an electrode, an element, and the like which have a laminated structure on a substrate and are insulated from each other. Connect to each other. An electro-optical device includes a TFT array substrate (1).
0), a pixel electrode (9a) and a TF connected to the pixel electrode (9a).
T (30) and a data line (6a) connected thereto. A convex portion (501) is formed on the substrate and TF
T interlayer insulating film (41, 4) between the source region and the data line.
2) is removed at a position facing the convex portion,
An electrical connection is established between the two.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor (hereinafter, appropriately referred to as a TFT (Thin Film Transistor)), a thin film diode (hereinafter, referred to as appropriate) on a substrate, such as data lines, scanning lines, and capacitance lines. TFD (Thin Film
Diode), and various types of pixel switching elements, such as pixel electrodes, capacitance electrodes, etc., and are formed in the technical field of electro-optical devices such as liquid crystal devices of an active matrix drive system and the manufacturing method thereof. Specifically, the present invention belongs to the technical field of a substrate device of an electro-optical device in which various wirings, various electronic elements, various electrodes, and the like are formed on a substrate, and a manufacturing method thereof.

[0002]

2. Description of the Related Art In this type of electro-optical device, various wirings such as data lines, scanning lines, and capacitance lines, TFTs, TFDs, and the like are provided on a substrate.
Various kinds of electronic elements such as a pixel electrode and the like are laminated with an interlayer insulating film interposed therebetween. Therefore, due to the presence of these wirings and elements, irregularities occur on the underlying surface of the pixel electrode located above them via the interlayer insulating film. As a result, operation irregularities such as defective orientation of the liquid crystal facing the pixel electrode occur due to such irregularities, and lead to image defects such as a decrease in contrast ratio due to light leakage. For this reason, it is common to provide a stripe-shaped or lattice-shaped light-shielding film so as to cover various wirings and various elements when the TFT array substrate and the counter substrate are viewed in plan.
However, in order to meet the basic requirement in the technical field of the electro-optical device for brightening a display image, it is important to make the area hidden by the light-shielding film as small as possible.

[0003]

However, in the above-described electro-optical device, for example, the electrical connection between the source side of the TFT and the data line and the electrical connection between the drain side of the TFT and the pixel electrode are respectively: It is made through one contact hole opened in the interlayer insulating film, or through a plurality of contact holes by relaying the relay layer. For this reason, even if the flattening process is performed, irregularities are generated on the underlying surface of the pixel electrode around the area where the contact hole is opened, which leads to an image defect such as a decrease in contrast ratio as described above. There is.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a laminated structure on a substrate, between wirings, electrodes, elements, and the like, which are mutually insulated from one another, at a connection point and at the periphery thereof. It is an object of the present invention to provide an electro-optical device, a method of manufacturing the same, and a substrate device and a method of manufacturing the same, which are connected to each other so as to cause almost no irregularities in the upper layer and can be manufactured relatively easily.

[0005]

In order to solve the above-mentioned problems, an electro-optical device according to the present invention comprises an electro-optical material sandwiched between a pair of first and second substrates.
A pixel electrode, a switching element connected to the pixel electrode, a wiring connected to the switching element, the pixel electrode, an interlayer insulating film formed between the switching element and the wiring, the pixel electrode, And a connection portion electrically connected between the switching element and the wiring, wherein a protrusion is formed in at least one region of the connection portion of the first substrate, and the connection is formed by the protrusion. The lower connection portion of the portion is raised, and the interlayer insulating film on the lower connection portion is removed to be electrically connected to the upper connection portion.

According to the electro-optical device of the present invention, the switching of pixel electrodes is controlled by switching elements such as TFTs and TFDs provided on a substrate and connected to wirings such as data lines and scanning lines. Active matrix driving can be performed. The interlayer insulating film is provided between the pixel electrode and the switching element, and between the wiring and the switching element. In particular, the interlayer insulating film is removed at a portion facing the convex portion formed on the first substrate, and the pixel electrode and the switching element, and the wiring and the switching element are electrically connected. .

Therefore, if the interlayer insulating film is removed by flattening at the portion facing the convex portion, the connecting portion between the pixel electrode and the switching element and its periphery, and between the wiring and the switching element, The underlying surface of the pixel electrode at the connection location and its periphery is flattened. Alternatively, if the interlayer insulating film is removed by forming a contact hole at a position facing the convex portion, the depth of the contact hole may be small in accordance with the height of the convex portion. As compared with the case where no portion exists, the unevenness generated on the base surface of the pixel electrode at the connection point and the periphery thereof is reduced. Moreover, such an effect according to the present invention can be obtained by forming a convex portion on the first substrate, and can be implemented relatively easily.

As a result, it is possible to reduce operation defects such as defective alignment of liquid crystal due to unevenness on the underlying surface of the pixel electrode, and finally, it is possible to reduce image defects such as a decrease in contrast ratio.

In one aspect of the electro-optical device according to the present invention, the interlayer edge film is removed by a CMP process at a portion facing the convex portion.

According to this aspect, the interlayer insulating film is formed by CMP.
Since the substrate is removed by being flattened by the treatment, the underlying surface of the pixel electrode at the connection point and the periphery thereof can be extremely flattened.

Alternatively, in another aspect of the electro-optical device according to the present invention, the interlayer insulating film is removed by forming a contact hole at a position facing the projection.

According to this aspect, since the interlayer insulating film is removed by forming the contact hole, the interlayer insulating film is formed on the contact hole and the underlying surface of the pixel electrode in the vicinity thereof in accordance with the height of the projection. Unevenness can be reduced.

In another aspect of the electro-optical device according to the present invention, the pixel electrode and the switching element are electrically connected to each other via a relay layer, and the interlayer insulating film faces the projection. At least one portion is electrically connected between the pixel electrode and the relay layer and between the switching element and the relay layer.

According to this aspect, the pixel electrode and the switching element are electrically connected via the relay layer. For this reason, even when the interlayer distance between the pixel electrode and the switching element is long, the two can be connected while avoiding the technical difficulty of connecting them with one contact hole. In particular, the interlayer insulating film is removed at a position facing the convex portion, and the pixel electrode and the relay layer and the switching element and the relay layer are electrically connected. Therefore, irregularities generated on the base surface of the pixel electrode at and around the connection point between the pixel electrode and the relay layer and the connection point between the switching element and the relay layer and the periphery thereof can be reduced.

It is needless to say that the pixel electrode and the switching element may be directly connected without using the relay layer. In addition, instead of or in addition to between the pixel electrode and the switching element, the wiring such as a data line and the switching element may be configured to be electrically connected via a relay layer.

In another aspect of the electro-optical device of the present invention, the height of the protrusion is substantially equal to the thickness of the interlayer insulating film.

According to this structure, when the interlayer insulating film is removed by planarization by the CMP process, the portion of the interlayer insulating film which is raised according to the protrusion is polished and removed, so that the connection of the switching element can be achieved. The portion can be exposed from the interlayer insulating film. Alternatively, in the case where the interlayer insulating film is removed by forming a contact hole, the contact hole may be formed up to the level of the surface of the portion of the interlayer insulating film which is not raised around the protrusion, so that the switching element can be connected. The portion can be exposed from the interlayer insulating film. Therefore, the irregularities on the underlying surface of the pixel electrode can be greatly reduced in a simple manner, and the reliability at the connection point can be improved.

In another aspect of the electro-optical device according to the present invention, the protrusion is formed as a part of the first substrate.

According to this aspect, the convex portion formed as a part of the first substrate makes it possible to flatten the connection portion thereabove and the underlying surface of the pixel electrode in the vicinity thereof. In particular, such a configuration can be relatively easily realized by photolithography, etching, and the like for the first substrate.

In this aspect, the first substrate has a trench in which the wiring and the switching element are at least partially buried via the interlayer insulating film, and the convex portion has a trench. It may be formed by not being performed.

According to this structure, the wiring and the switching element are buried in the groove, so that the underlying surface of the pixel electrode located above the wiring and the switching element can be flattened. Can be further reduced.
Moreover, since the protrusions are formed by not digging such grooves, the grooves and the protrusions can be collectively formed by, for example, photolithography, etching, or the like on the first substrate. This is very advantageous in simplifying the laminated structure and manufacturing process of the optical device. In this case, for example, the projection is formed in an island-like region surrounded by a groove when viewed in plan.

Alternatively, in another aspect of the electro-optical device according to the present invention, the protrusion is formed from an island-shaped member provided on the first substrate.

According to this aspect, the convex portion formed from the island-shaped member can flatten the connection portion above and the underlying surface of the pixel electrode in the vicinity thereof. Such an island-shaped member is made of, for example, an island-shaped film piece having a predetermined thickness, and may use the same film as another light-shielding film, a dielectric film, a semiconductor layer, a conductive film for wiring, or the like. Alternatively, it may be additionally formed from a dedicated film.

In another aspect of the electro-optical device according to the present invention, the protrusion has a taper.

According to this aspect, since the convex portion has a taper, it is attached to the side wall of the convex portion such as the conductive film, the relay layer, or the like which forms the connection portion of the switching element formed above the convex portion. The circumference improves. For this reason, a connection failure is less likely to occur, and the device reliability can be improved.

In another aspect of the electro-optical device according to the present invention, the electro-optical device further includes a base insulating film laminated below the switching element, wherein the protrusions are provided instead of or in addition to the substrate. Is formed.

According to this aspect, instead of or in addition to the substrate, the convex portion formed on the underlying insulating film on the substrate can flatten the underlying portion of the pixel electrode in the connection portion thereabove and in the vicinity thereof. .

In order to solve the above-mentioned problems, an electro-optical device manufacturing method according to the present invention is a method for manufacturing the above-described electro-optical device (including various aspects thereof) according to the present invention. Forming the projection on the first substrate; forming the switching element such that a lower connection portion of the switching element is located above the projection; and forming the interlayer insulating layer above the switching element. A step of forming a film, a step of removing the interlayer insulating film at a position facing the convex portion to expose the lower connection portion, and a step of forming the wiring or the pixel electrode on the exposed lower connection portion. Forming the wiring or the pixel electrode on the interlayer insulating film such that the upper connection portion is located.

According to the method of manufacturing the electro-optical device of the present invention, the electro-optical device of the present invention (including various aspects thereof) in which the irregularities generated on the underlying surface of the pixel electrode at the connection point and the periphery thereof are reduced as described above. Can be manufactured using a relatively simple process of first forming a convex portion on the first substrate and then removing the raised portion of the interlayer insulating film accordingly.

In one aspect of the method of manufacturing an electro-optical device according to the present invention, the exposing step includes exposing the lower connection portion by planarizing the interlayer insulating film by a CMP (chemical mechanical polishing) process. Let it.

According to this aspect, the electro-optical device according to the present invention, in which the underlying surface of the pixel electrode at the connection point and the periphery thereof is extremely flattened as described above, is first formed with a convex portion on the first substrate. Thereafter, it can be manufactured using a relatively simple process of flattening the raised interlayer insulating film portion by the CMP process.

In another aspect of the method of manufacturing an electro-optical device according to the present invention, in the step of forming the convex portion, the first substrate is etched so as to leave the convex portion, and the wiring and the switching element are formed by the etching. An etching step of forming a groove which is at least partially buried via an interlayer insulating film;

According to this aspect, it is possible to manufacture the electro-optical device according to the present invention in which not only the connection portion and its periphery, but also the underlying surface of the pixel electrode above the wiring and the switching element are satisfactorily planarized. Moreover, since these grooves and projections can be formed collectively by etching the first substrate, it is very advantageous in simplifying the manufacturing process. For example, although no convex portion is formed on the substrate as in the present invention, the number of steps does not need to be increased as compared with a manufacturing method including a step of digging a groove for embedding a wiring or a switching element for planarization.

In order to solve the above problems, the substrate device of the present invention has a first conductive film having a first planar pattern on the substrate, an interlayer insulating film laminated on the first conductive film, A second conductive film having a second planar pattern formed on the interlayer insulating film, wherein a convex portion is formed on the substrate, and the interlayer insulating film is flat at a position facing the convex portion. Thus, the first conductive film and the second conductive film are electrically connected to each other.

According to the substrate device of the present invention, the first substrate having the first plane pattern insulated from each other on the substrate is provided.
From the conductive film and the second conductive film having the second planar pattern,
Various electronic elements, wirings, connection parts, and the like are formed, and a substrate device such as an element array substrate device related to a semiconductor circuit device or an electro-optical device is constructed. Here, in particular, the interlayer insulating film is removed by being flattened at a portion facing the convex portion, so that the first conductive film and the second conductive film which form a laminated structure and are interlayer-insulated from each other are electrically connected. Connected. Therefore, the upper layer of the stacked structure at the connection between the first conductive film and the second conductive film and at the periphery thereof is flattened. Moreover, such an effect according to the present invention can be obtained by forming a projection on the substrate, and can be implemented relatively easily.

As a result, the present invention is suitably applied to a substrate device such as a semiconductor circuit device and an element array substrate device in which flattening in the upper layer of the laminated structure on the substrate provides some benefit.

In order to solve the above-mentioned problems, a method for manufacturing a substrate device according to the present invention is a method for manufacturing a substrate device for manufacturing the above-described substrate device according to the present invention, comprising the steps of: Forming the first conductive film so that the lower connection portion of the first conductive film is located above the protrusion, and forming the interlayer insulating film above the first conductive film. Removing the interlayer insulating film by flattening the portion facing the convex portion to expose the lower connection portion; and forming the upper portion of the second conductive film on the exposed lower connection portion. Forming the second conductive film on the interlayer insulating film so that the side connection portion is located.

According to the method of manufacturing a substrate device of the present invention, the substrate device of the present invention, in which the unevenness generated in the upper layer of the laminated structure at the connection point and its periphery is reduced as described above, is first provided with a projection on the first substrate. It can be manufactured using a relatively simple process of forming and then removing the raised interlayer insulating film by planarization.

The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

[0040]

Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the electro-optical device according to the invention is applied to a liquid crystal device.

(Electro-optical Device of First Embodiment) First, an electro-optical device of a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming an image display area of the electro-optical device. FIG.
FIG. 3 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed. FIG.
FIG. 4 is a sectional view taken along line AA ′ of FIG. 2, and FIG.
5 is a cross-sectional view taken along the line CC ′ of FIG. 2. In FIGS. 3 to 5, the scale of each layer and each member is different for each layer and each member in order to make the size recognizable in the drawings.

In FIG. 1, each of a plurality of pixels formed in a matrix forming an image display area of the electro-optical device according to this embodiment has a pixel electrode 9a and a TFT 30 for controlling the switching of the pixel electrode 9a. Are formed, and the data line 6a to which the image signal is supplied is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. good. The scanning line 3 is connected to the gate of the TFT 30.
a is electrically connected to the scanning line 3a at predetermined timings in a pulsed manner with the scanning signals G1, G2,.
Are applied in this order in a line-sequential manner.
The pixel electrode 9a is electrically connected to the drain of the TFT 30, and by closing the switch of the TFT 30 as a switching element for a certain period, the data line 6 is turned off.
The image signals S1, S2,..., Sn supplied from a are written at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal as an example of the electro-optical material via the pixel electrode 9a are connected to a counter electrode (described later) formed on a counter substrate (described later). For a fixed period of time. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. In the normally white mode, the transmittance for the incident light decreases according to the voltage applied in each pixel unit. In the normally black mode, the light enters according to the voltage applied in each pixel unit. Light transmittance is increased, and light having a contrast corresponding to an image signal is emitted from the electro-optical device as a whole. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with a liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. Storage capacity 70
Are formed via a dielectric film between a pixel potential side capacitance electrode extending from the drain of the TFT 30 and a fixed potential side capacitance electrode formed of a part of the capacitance line 300.

In FIG. 2, a plurality of transparent pixel electrodes 9 are arranged in a matrix on a TFT array substrate of the electro-optical device.
a (the outline is indicated by a dotted line portion 9a '), and the data line 6a and the scanning line 3a are provided along the vertical and horizontal boundaries of the pixel electrode 9a, respectively.

A scanning line 3a is arranged so as to face a channel region 1a 'indicated by a hatched region in the semiconductor layer 1a which rises to the right in the figure, and the scanning line 3a functions as a gate electrode. Thus, the scanning line 3a and the data line 6
Pixel switching TFTs 30 each having a scanning line 3a opposed to each other as a gate electrode in a channel region 1a 'are provided at intersections with the pixel region a.

As shown in FIG. 2 to FIG.
May have a function as a light shielding layer for shielding the TFT 30 from incident light on the upper side of the TFT 30 in addition to the function as the fixed potential side capacitance electrode of the storage capacitor 70. Thereby, since the built-in light shielding on the TFT array substrate 10 can be realized, the light shielding film on the counter substrate 20 can be omitted.
Further, even if the displacement of the bonding between the TFT array substrate 10 and the counter substrate 20 occurs, the region through which the light is transmitted does not change, so that a liquid crystal device without variation in transmittance can be realized.

On the other hand, the dielectric film 7
The relay layer 71 opposed to the pixel electrode 5 through the pixel electrode 9a
And a high-concentration drain region 1e of the TFT 30. The storage capacitor 70 also has a function as a pixel potential side capacitor electrode of the storage capacitor 70.

In this embodiment, the storage capacitor 70 is a TFT
The relay layer 71 as a pixel potential side capacitance electrode connected to the high-concentration drain region 1e and the pixel electrode 9a of 30 and a part of the capacitance line 300 as a fixed potential side capacitance electrode are connected via a dielectric film 75. It is formed by being arranged facing.

As shown in FIG. 2, the capacitance line 300 includes a main line portion extending in a stripe shape along the scanning line 3a as viewed in plan, and a portion overlapping the TFT 30 projects vertically from the main line portion. The TFT 30 on the TFT array substrate 10 is provided in a region where the data line 6a extending in the vertical direction and the capacitance line 300 extending in the horizontal direction intersect.
Is arranged. The data lines 6a and the capacitor lines 300 which intersect each other form a lattice-shaped light-shielding layer in plan view, and define an opening area of each pixel.

On the other hand, T on the TFT array substrate 10
On the lower side of the FT 30, the lower light-shielding film 1 shown by a thick line in FIG.
1a are provided in a lattice shape.

The capacitance line 3 constituting one example of these light-shielding layers
00 and the lower light-shielding film 11a are each at least one of high-melting metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum), and Pb (lead). Including one metal simple substance, alloy,
It is made of a metal silicide, a polysilicide, or a material obtained by laminating them. Here, particularly for the capacitance line 300,
It may be configured to have a multilayer structure in which a first film made of a conductive polysilicon film or the like and a second film made of a metal silicide film containing a high melting point metal are stacked. In this case, T
The first film on the FT 30 side has a function as a light absorbing layer,
Internal reflected light and multiple reflected light generated in the electro-optical device can be absorbed and removed.

In FIGS. 4 and 5, the dielectric film 75 disposed between the relay layer 71 as a capacitor electrode and the capacitor line 300 is, for example, a thin HTO having a thickness of 200 nm or less.
A silicon oxide film such as a film, an LTO film, a nitrided oxide film, a silicon nitride film, or the like. From the viewpoint of increasing the storage capacitance 70, the thinner the dielectric film 75 is, the better the reliability of the film can be obtained.

As shown in FIGS. 3 to 5, the electro-optical device includes a transparent TFT array substrate 10 and a transparent opposing substrate 20 arranged to face the TFT array substrate. The TFT array substrate 10 is made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate.

In the TFT array substrate 10, a lattice-shaped groove 10cv is dug in a hatched area in the lower right of FIG. Wirings and elements such as the scanning lines 3a, the data lines 6a, and the TFTs 30 are buried in the grooves 10cv. As a result, the step between the region where the wiring, the element, and the like are present and the region where the wiring, the element, and the like are not present is reduced, and ultimately, image defects such as defective alignment of the liquid crystal due to the step can be reduced.

In FIG. 5, the pixel switching TFT
Reference numeral 30 denotes an LDD (Lightly Doped Drain) structure, and includes a scanning line 3a and a channel region 1 of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a.
a ', a gate insulating film 2 for insulating the scanning line 3a from the semiconductor layer 1a, a low-concentration source region 1b and a low-concentration drain region 1c of the semiconductor layer 1a, a high-concentration source region 1d and a high-concentration drain region 1e of the semiconductor layer 1a. It has.

On the scanning line 3a, a high concentration source region 1d
A first interlayer insulating film 41 is formed in which a contact hole 601 leading to the contact hole 603 and a contact hole 603 leading to the high concentration drain region 1e are respectively formed.

As shown in FIG. 4, a storage capacitor 7 composed of a relay layer 71 and a capacitor line 300 is provided on the first interlayer insulating film 41.
0 are formed, and a second interlayer insulating film 42 in which a contact hole 602 leading to the relay layer 71 is opened is formed thereon.

In this embodiment, the first interlayer insulating film 41 is used.
By sintering at 1000 ° C., the ions implanted into the polysilicon film forming the semiconductor layer 1a and the scanning line 3a may be activated. On the other hand, by not performing such sintering on the second interlayer insulating film 42, stress generated near the interface of the capacitance line 300 may be reduced.

The data lines 6 a are formed on the second interlayer insulating film 42, and a third contact hole 602 leading to the relay layer 71 is formed on the data lines 6 a.
3 are formed. The pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 43 configured as described above. In particular, the surface of the third interlayer insulating film 43 near the opening regions of the contact holes 601 and 602 is reduced by the presence of the convex portions 501 and 502 as described later.

As shown in FIGS. 2 and 3, the semiconductor layer 1a
In the opening region of the contact hole 601 connecting the high-concentration source region 1d and the data line 6a, the island-shaped convex portion 501 is formed on the surface of the substrate 10 by not locally forming the groove 10cv. I have. Due to the presence of the protrusion 501, the lower light-shielding film 11a, the underlying insulating film 12, and the semiconductor layer 1a stacked thereon are raised. Then, the high-concentration source region 1d of the semiconductor layer 1a thus raised is exposed at the bottom of the contact hole 601.
The exposed upper surface of the high-concentration source region 1d is configured to be in contact with the lower surface of the data line 6a in this region (see FIG. 3). That is, contact hole 6
Reference numeral 01 denotes openings in the second interlayer insulating film 42, the dielectric film 75, the first interlayer insulating film 41, and the gate insulating film 2.

Accordingly, the depth of the contact hole 601 can be reduced in accordance with the height of the projection 501, so that the pixel electrode 9a at the connection point and the periphery thereof can be compared with the case where such a projection 501 does not exist. (See FIG. 3). Moreover, such a protrusion 501 can be easily formed by not locally forming the groove 10cv in the TFT array substrate 10.

As shown in FIGS. 2 and 4, a contact hole 60 connecting the relay layer 71 and the pixel electrode 9a is formed.
By not locally forming the groove 10cv in the opening area of the second hole 2, the island-shaped convex portion 5 is formed on the surface of the TFT array substrate 10.
02 is formed. Due to the presence of the projection 502,
The lower light-shielding film 11a and the underlying insulating film 1 laminated thereon
2. The first interlayer insulating film 41 and the relay layer 71 are raised. Then, the relay layer 71 raised in this way.
Are exposed at the bottom of the contact hole 602, and the exposed upper surface of the relay layer 71 is in contact with the lower surface of the pixel electrode 9a in this region (see FIG. 4).
That is, the contact hole 602 is formed in the third interlayer insulating film 4.
3, openings are formed in the second interlayer insulating film 42 and the dielectric film 75.

Therefore, the depth of the contact hole 602 can be reduced according to the height of the projection 502, and the pixel electrode 9a at the connection point and its surroundings can be compared with the case where such a projection 502 does not exist. (See FIG. 4). Moreover, such a protrusion 502 can be easily formed by not locally forming the groove 10cv in the TFT array substrate 10.

Further, in the present embodiment, the convex portions 501 and 502 are each formed with a taper, and the contact holes 601 and 602 are accordingly tapered (see FIGS. 3 and 4). Therefore, the rotation of the data line 6a on the side wall of the contact hole 601 or the side wall of the pixel electrode 9a on the side wall of the contact hole 602 is improved, and good electrical connection can be realized.

The contact holes 601 and 602
Even when the high-concentration source region 1d and the relay layer 71 of the semiconductor layer 1a are removed at the time of formation of the semiconductor layer 1a, conduction is established between the removed high-concentration source region 1d and the relay layer 71 and the data line 6a and the pixel electrode 9a. I hope I can do it.

As shown in FIGS. 2 and 5, the semiconductor layer 1a
In the contact hole 603 connecting the high-concentration drain region 1e and the relay layer 71, no projection is formed on the substrate 10 in the opening region. This is because the depth of the contact hole 603 is substantially equal to the thickness of only the first interlayer insulating film 41, and the contact holes 601 and 60
This is because the connection by the contact hole can be relatively easily formed without forming a projection because the depth is shallower than that of No. 2. However, the contact hole 603 is formed on the substrate 1 like the contact hole 601 or 602 described above.
It is possible to open a hole on the projection formed at zero.

By using the relay layer 71 in this way, even if the interlayer distance between the high-concentration drain region 1e and the pixel electrode 9a is long, for example, about 2000 nm, it is technically difficult to connect them with one contact hole. In addition, two or more contact holes 603 and 602 having relatively small diameters can be connected well in series while avoiding the problem, the pixel aperture ratio can be increased, and the penetration of etching when the contact holes are opened can be prevented. Useful.

In FIG. 2, the capacitance line 300 is the scanning line 3
a, the pixel electrode 9a extends from the image display area where the pixel electrode 9a is arranged along the periphery thereof, and is electrically connected to a constant potential source.
The potential is fixed. As such a constant potential source, a TFT 30
A scanning line driving circuit (to be described later) for supplying a scanning signal for driving the
A constant potential source such as a positive power supply or a negative power supply supplied to a data line driving circuit (described later) for controlling a sampling circuit for supplying the signal to a, or a constant potential supplied to the counter electrode 21 of the counter substrate 20 may be used. . Further, the lower light-shielding film 11a also extends from the image display area to the periphery thereof and is connected to a constant potential source, similarly to the capacitor line 300, in order to prevent the potential fluctuation from adversely affecting the TFT 30. Good to do.

As shown in FIGS. 3 to 5, a pixel electrode 9a is provided on the TFT array substrate 10, and a predetermined orientation such as rubbing treatment or the like is provided above the pixel electrode 9a via a third interlayer insulating film 43. The processed alignment film 16 is provided. The pixel electrode 9a is made of, for example, ITO (Indium Tin Oxid).
e) It is made of a transparent conductive film such as a film. The alignment film 16 is made of, for example, an organic film such as a polyimide film.

On the other hand, a counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode 21. I have. The counter electrode 21 is made of, for example, a transparent conductive film such as an ITO film. The alignment film 22 is made of an organic film such as a polyimide film.

The opposing substrate 20 may be provided with a lattice-shaped or stripe-shaped light-shielding film. By adopting such a configuration, as described above, the capacitance line 30 constituting the light shielding layer
0 and the light-shielding film on the opposing substrate 20 together with the data lines 6a, the incident light from the opposing substrate 20 side is
a ′, the lightly doped source region 1b and the lightly doped drain region 1
c can be more reliably prevented from entering. Further, such a light-shielding film on the counter substrate 20 has a function of preventing a temperature rise of the electro-optical device by forming at least a surface irradiated with incident light with a highly reflective film. Note that the light-shielding film on the counter substrate 20 is preferably formed so as to be located inside the light-shielding layer including the capacitor lines 300 and the data lines 6a in plan view. As a result, the light-shielding film on the counter substrate 20 can provide such effects of light-shielding and temperature rise prevention without lowering the aperture ratio of each pixel.

The space between the TFT array substrate 10 and the opposing substrate 20 having the pixel electrode 9a and the opposing electrode 21 arranged in such a manner as to face each other is provided in a space surrounded by a sealing material described later. Liquid crystal, which is an example of an electro-optical material, is sealed, and a liquid crystal layer 50 is formed. The liquid crystal layer 50 holds the alignment film 1 in a state where no electric field is applied from the pixel electrode 9a.
A predetermined orientation state is taken by 6 and 22. Liquid crystal layer 50
Is composed of, for example, a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. The sealing material is used for bonding the TFT array substrate 10 and the opposing substrate 20 around them.
For example, it is an adhesive made of a photo-curing resin or a thermosetting resin, and a gap material such as glass fiber or glass beads for mixing the two substrates at a predetermined distance is mixed.

Further, under the pixel switching TFT 30, a base insulating film 12 is provided. Base insulating film 1
2 has a function of interlayer insulating the TFT 30 from the lower light-shielding film 11a, and is formed on the entire surface of the TFT array substrate 10 so that the surface of the TFT array substrate 10 can be roughened during polishing or stains remaining after cleaning. T for pixel switching
It has a function of preventing the characteristics of the FT 30 from changing.

According to the present embodiment configured as described above, the channel region 1 of the TFT 30 from the counter substrate 20 side
When the incident light attempts to enter a ′ and its vicinity, the light is shielded by the data line 6a and the capacitance line 300 as an example of the built-in light shielding film. On the other hand, from the TFT array substrate 10 side, the TFT 3
When return light attempts to enter the 0 channel region 1a 'and its vicinity, the lower light shielding film 11a blocks light. In particular,
When a single optical system is configured by combining a plurality of electro-optical devices via a prism or the like in a multi-plate type color display projector or the like, the projection light that passes through the prism or the like from another electro-optical device is strong. Therefore, it is effective. As a result, the characteristics of the TFT 30 hardly change due to light leakage, and in the electro-optical device,
Very high lightfastness is obtained.

According to the present embodiment, in particular, the data line 6a, the scanning line 3a, the capacitor line 300 and the TFT 30
0cv, the third interlayer insulating film 4
The surface of the third interlayer insulating film 43 in the vicinity of the contact holes 601 and 602 according to the heights of the projections 501 and 502 as well as the unevenness of the surface of the third electrode 3 (that is, the underlying surface of the pixel electrode 9a) is reduced. Are reduced.
Therefore, alignment defects of the liquid crystal due to irregularities on the surface of the pixel electrode 9a can be greatly reduced, and finally, high-contrast, high-quality images with little light leakage can be displayed. Moreover, the protrusions 501 and 601 that enable such a configuration can be obtained relatively easily by not locally forming the groove 10cv in the substrate 10. Further, since the height of the protrusion 501 is substantially equal to the thickness of the second interlayer insulating film 42, the contact hole 6
By opening 01, high-concentration source region 1 d can be relatively easily exposed in contact hole 601. Similarly, since the height of the protrusion 502 is substantially equal to the thickness of the third interlayer insulating film 43, the relay layer 71 can be relatively easily exposed in the contact hole 602 by opening the contact hole 602. it can. In addition, in the present embodiment, in particular, the convex portions 501 and 502 are each formed with a taper, and the sidewalls of the contact holes 601 and 602 can easily turn around the data line 6a and the pixel electrode 9a. An electro-optical device with high device reliability can be realized.

In the embodiment described above, the storage capacity 70
Although the configuration in which the capacitance line 300 including the fixed potential side electrode is used as the built-in light-shielding film is adopted, the pixel potential side electrode of the storage capacitor 70 may be formed as the built-in light-shielding film, or the pixel electrode 9a It is also possible to configure a relay layer for relay connection between the TFT and the TFT 30 as a built-in light shielding film. In any case, the pixel potential side capacitor electrode or the relay layer may be formed from a conductive light shielding film such as a high melting point metal film.

In the embodiment described above, FIGS.
By stacking a large number of conductive layers as shown in FIG. 3, the data lines 6a and the scanning lines 3a on the ground below the pixel electrodes 9a are formed.
Is formed in the area along the TFT array substrate 1
The groove 10cv is formed in the base insulating film 12, the first interlayer insulating film 41, the second interlayer insulating film 42, and the third interlayer insulating film 43 instead of or in addition to the groove 10cv. May be formed, and a flattening process may be performed by embedding the wiring such as the data line 6a or the TFT 30 or the like, or the step on the upper surface of the third interlayer insulating film 43 or the second interlayer insulating film 42 may be formed by CMP.
The flattening process may be performed by polishing using a (Chemical Mechanical Polishing) process or the like, or by forming flat using organic SOG (Spin On Glass).

In addition, in the present embodiment, as shown in FIG. 2, the data line 6a, the scanning line 3a, the capacitor line 300 and the TFT
The grooves 10cv are formed in a grid pattern so as to embed the grooves 30. However, by not forming the grooves 10cv at least partially in the plane area along the data lines 6a, the banks extending along the scanning lines 3a can be removed from the pixel electrodes. 9a may be formed on the base surface. That is, according to this configuration, when the scanning line inversion driving method of inverting the voltage applied to the liquid crystal for each pixel group along the scanning line 3a for each field or every frame of the image signal is employed, The adverse effect caused by the horizontal electric field generated between the pixel electrodes 9a adjacent to each other in the direction 6a can be reduced. More specifically, as the distance between the edge of the pixel electrode on the bank and the counter electrode is shortened, the vertical electric field can be strengthened in the region where the horizontal electric field is generated, and the alignment defect of the liquid crystal due to the horizontal electric field is reduced. it can. As a result, it is possible to prevent light emission due to poor alignment of the liquid crystal due to the horizontal electric field, and to improve the contrast ratio. Adopting the scanning line inversion driving method in this manner is useful for preventing deterioration of liquid crystal due to application of a DC voltage and preventing flicker in a displayed image.

(Manufacturing Method of First Embodiment) Next, regarding the manufacturing method of the electro-optical device of the first embodiment having the above-described configuration, particularly on the side of the TFT array substrate 10, the steps related to the contact holes 601 and 602 will be described. The description will be made mainly with reference to FIGS. 6 to 9. Here, FIGS. 6 and 7 are process diagrams showing each layer on the TFT array substrate 10 side in each process of the manufacturing process of the first embodiment, corresponding to the AA ′ section of FIG. is there. On the other hand, FIGS. 8 and 9 are process diagrams corresponding to the BB ′ cross section of FIG. 2 similarly to FIG.

First, as shown in step (2) of FIG. 6 and FIG. 8, TFT such as quartz substrate, hard glass, silicon substrate, etc.
An array substrate 10 is prepared, and has a plane pattern shown in FIG. 2 by photolithography and dry etching and wet etching.
A groove 10cv having a depth of about 1000 nm, preferably about 800 nm is formed. Such a depth may be set individually and specifically according to the flatness required near the contact holes 601 and 602 and the thickness of the interlayer insulating film according to the actual device specifications. As a result, a protrusion 501 (see FIG. 6) and a protrusion 502 (see FIG. 8) are formed. Here, heat treatment is preferably performed in an inert gas atmosphere such as N ₂ (nitrogen) and at a high temperature of about 900 to 1300 ° C., and pre-processing is performed so that distortion generated in the TFT array substrate 10 in a high-temperature process performed later is reduced. Keep it.

Subsequently, the lower light-shielding film 11a having the planar pattern as shown in FIG. 2 and the semiconductor layer are formed on the substrate 10 having the grooves 10cv formed thereon by sputtering, vapor deposition, photolithography, etching or the like. 1a, the scanning line 3a, the relay layer 71, the capacitor line 300, and the like are sequentially formed, and the base insulating film 12, the gate insulating film 2, the first interlayer insulating film, and the dielectric film 75 are sequentially formed therebetween.

More specifically, the lower light-shielding film 11a is sputtered with, for example, Ti, Cr, W, Ta, Mo, Pb or the like, and has a thickness of about 100 to 500 nm.
Preferably, after forming a light-shielding film having a thickness of about 200 nm,
Perform patterning.

On the other hand, for the base insulating film 12, for example,
TEOS (tetra-ethyl-ortho-silicate) gas, TEB (tetra-ethyl-borate) gas, TMOP (tetra-methyl
NSG, PS using oxyfoslate) gas
G, BSG, BPSG, or the like is formed from a laminated or single-layer silicate glass film, a silicon nitride film, a silicon oxide film, or the like. The film thickness of the base insulating film 12 is, for example, about 500 to
It is about 2000 nm.

The same applies to the first interlayer insulating film 41.

The semiconductor layer 1a is, for example, about 450
The amorphous silicon film is formed in a relatively low-temperature environment of about 550 ° C., preferably about 500 ° C. by low-pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa) using a monosilane gas, a disilane gas, or the like at a flow rate of about 400 to 600 cc / min. At about 600 to 700 ° C. in a nitrogen atmosphere.
Heat treatment for about 1 to 10 hours, preferably for 4 to 6 hours, to form a polysilicon film of about 50 to 200 n.
After solid-phase growth to a particle size of m, preferably about 100 nm, patterning is performed.

For the gate insulating film 2 of the TFT 30, for example, the lower layer gate insulating film is formed by thermally oxidizing the semiconductor layer 1a at a temperature of about 900 to 1300 ° C., preferably at a temperature of about 1000 ° C. The upper gate insulating film is formed by, for example, or by performing both of them continuously. Thereby, a multilayer high-temperature silicon oxide film (H
A gate insulating film 2 made of a TO film) or a silicon nitride film is formed. As a result, the thickness of the semiconductor layer 1a is about 30 to 1
The thickness is 50 nm, preferably about 35 to 50 nm, and the thickness of the gate insulating film 2 is about 20 to 150 nm, preferably about 30 to 100 nm.

For the scanning line 3a, for example,
After a polysilicon film is deposited by a method or the like, and the polysilicon film is made conductive by, for example, thermally diffusing phosphorus (P), the polysilicon film is patterned. The thickness of the scanning line 3a is about 1
It has a thickness of 00 to 500 nm, preferably about 350 nm.

Further, the scanning line 3 is applied to the semiconductor layer 1a.
After the formation of a, the low-concentration source region 1b and the low-concentration drain region 1c and the high-concentration source region 1d and the high-concentration drain region 1e are selectively doped with P ions or the like by a predetermined amount according to the specification of the TFT 30.

For the relay layer 71, for example, low pressure CVD
A polysilicon film is deposited by a method or the like, and is made conductive by thermal diffusion of phosphorus (P), and then patterned. The thickness of the relay layer 71 is about 100 to 500 nm, preferably about 150 nm.

For the dielectric film 75, for example,
A dielectric film 75 made of a high-temperature silicon oxide film (HTO film) or a silicon nitride film is deposited to a relatively small thickness of about 50 nm by a method D, a plasma CVD method, or the like. Alternatively, it may be formed in the same manner as the gate insulating film 2 described above.

For the capacitance line 300, for example, Ti, C
Sputtering r, W, Ta, Mo, Pb, etc.,
After forming a metal film having a thickness of about 100 to 500 nm,
Perform patterning.

After the first interlayer insulating film 41 is formed, contact holes 603 extending from the relay layer 71 to the high-concentration drain region 1e are formed by dry etching such as reactive ion etching and reactive ion beam etching.
(See FIGS. 2 and 5).

Next, in the step (2) shown in FIGS. 6 and 8, for example, normal pressure or reduced pressure CVD, TEOS gas or the like is used.
A second interlayer insulating film made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The film thickness of the first interlayer insulating film 42 is, for example, about 500 to 1500 nm.

Next, in step (3) of FIG. 6, reactive ion etching, reactive ion beam etching, or the like is performed on the second interlayer insulating film 42, the dielectric film 75, the first interlayer insulating film 41, and the gate insulating film 2. A contact hole 601 is formed at a plane position shown in FIG. 2 by dry etching, wet etching or a combination thereof. At this time, it is preferable to use wet etching at least partially so that the contact hole 601 has a taper. As a result, the high-concentration source region 1 is formed on the bottom of the contact hole 601 above the protrusion 501.
Part of d is exposed.

Next, in step (4) of FIG. 6, a low-resistance metal such as Al or a metal silicide, such as light-shielding Al, is formed on the entire surface of the second interlayer insulating film 42 in which the contact hole 601 is formed by sputtering or the like. About 100 to 5
Deposit to a thickness of 00 nm, preferably about 300 nm.
Then, a data line 6a having a predetermined pattern as shown in FIG. 2 is formed by photolithography and etching. Thereby, at the bottom of the contact hole 601,
Electrical connection between data line 6a and high concentration source region 1d can be established.

Next, as shown in step (5) of FIG. 7 and FIG. 9, NSG, PS, or the like is formed by using normal pressure or low pressure CVD, TEOS gas, or the like so as to cover the data line 6a.
A third interlayer insulating film 43 made of a silicate glass film such as G, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed. The thickness of the third interlayer insulating film 43 is, for example, about 500 to 1500 nm.

Next, as shown in step (6) of FIG.
Interlayer insulating film 43, second interlayer insulating film 42, and dielectric film 75
A contact hole 602 is formed at a plane position shown in FIG. 2 by dry etching such as reactive ion etching, reactive ion beam etching, or wet etching, or a combination thereof. At this time, it is preferable to use wet etching at least partially so that the contact hole 602 has a taper. As a result, a part of the relay layer 71 is exposed at the bottom of the contact hole 602 above the protrusion 502.

As shown in step (7) of FIGS. 7 and 9,
Third interlayer insulating film 4 having contact holes 602 formed therein
3, a transparent conductive film such as an ITO film is deposited to a thickness of about 50 to 200 nm by sputtering or the like. Then, the pixel electrode 9a having the planar pattern shown in FIG. 2 is formed by photolithography and etching.
Accordingly, electrical connection between the pixel electrode 9a and the relay layer 71 can be established at the bottom of the contact hole 602. When the liquid crystal device is used for a reflection type liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

Subsequently, after applying a coating liquid for a polyimide-based alignment film on the pixel electrode 9a, a rubbing process is performed so as to have a predetermined pretilt angle and in a predetermined direction. 3 to FIG. 5).

As a result, the TFT array substrate 10 side of the electro-optical device according to the first embodiment is manufactured.

According to the present embodiment, in particular, in the step (1) of FIG. 6, first, the groove 10cv is formed, and at the same time, the convex portion 501 is formed on the substrate 10, and then the steps (3) and (3) of FIG. In (4), the data line 6a can be electrically connected to the high-concentration source region 1d of the semiconductor layer 1a by using a relatively simple process of removing the portion of the interlayer insulating film that has been raised according to the protrusion 501. . This allows
The pixel electrode 9a can be manufactured so that the underlying surface is flat near the contact hole 601.

Similarly, in step (1) of FIG. 9, first, the groove 10cv is formed, and at the same time, the projection 502 is
Then, in a step (6) and a step (7) in FIG. 9, the pixel electrode 9a and the pixel electrode 9a are formed by using a relatively simple process of removing an interlayer insulating film portion raised according to the protrusion 502, respectively. The relay layer 71 can be electrically connected. Accordingly, the pixel electrode 9a can be manufactured such that the underlying surface becomes flat near the contact hole 602.

As described above, the manufacturing method of this embodiment is very advantageous in simplifying the manufacturing steps. For example, as compared with the manufacturing method including the step of forming the groove 10cv for burying the data line 6a or the like for flattening although the protrusions 501 and 502 are not formed on the substrate 10 as in the present embodiment,
It is sufficient to slightly change the etching pattern when forming the groove 10cv, and it is not necessary to increase the number of steps.

(Electro-optical Device of Second Embodiment) Next, FIG.
The second embodiment of the electro-optical device according to the present invention will be described with reference to FIG. Since the second embodiment relates to the connection between the pixel electrode 9a and the relay layer 71 in the first embodiment, only the configuration of this connection will be described. Other configurations are the same as those in the first embodiment. Here, FIG.
It is sectional drawing which shows the connection part of 2nd Embodiment in the cross section corresponding to B 'cross section. In FIG. 10, the same components as those of the first embodiment shown in FIG. 4 are denoted by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 10, in the second embodiment, the protrusion 502 'is formed on the TFT array substrate 10, and the relay layer 71 is raised at the connection 71e. In particular, above the connection portion 71e, the third interlayer insulating film 43, the second interlayer insulating film 42, and the dielectric film 75 are flattened by a CMP process in a portion raised by the convex portion 502 '. Has been removed. As a result, the connection portion 71e is exposed at the same level as the surface of the third interlayer insulating film 43 above the convex portion 502 ', and is configured to come into surface contact with the pixel electrode 9a here. .

Therefore, according to the second embodiment, the protrusion 50
Above 2 ', the third interlayer insulating film 43 and the second interlayer insulating film 42
In addition, since the dielectric film 75 is flattened by the CMP process, the underlying surface of the pixel electrode 9a in the connection portion 71e and the periphery thereof can be extremely flattened.

In particular, in this embodiment, the height of the projection 502 'is substantially equal to the total thickness of the third interlayer insulating film 43, the second interlayer insulating film 42, and the dielectric film 75. By polishing and removing the raised portion of the interlayer insulating film,
The connection portion 71e of the relay layer 71 can be exposed from the third interlayer insulating film 43.

(Manufacturing Method of Second Embodiment) Next, in the manufacturing method of the electro-optical device according to the second embodiment having the above-described configuration, particularly on the TFT array substrate 10 side, the connection portion 71e of the relay layer 71 and the pixel The process related to the connection with the electrode 9a will be mainly described with reference to FIG. Here, FIG. 11 is a process diagram showing each layer on the TFT array substrate 10 side in each step of the manufacturing process of the second embodiment corresponding to the BB ′ section of FIG. 2 as in FIG. still,
The description of the same steps as in the first embodiment shown in FIGS. 8 and 9 will be omitted.

First, steps (1) to (5) of FIG. 8 are performed in substantially the same manner as in the first embodiment. However, compared to the first embodiment, the height of the convex portion 502 'is increased (that is, the groove 10c is formed).
v is formed deeply).
Etching of the array substrate 10 is performed. As a result, a laminated structure as shown in the step (5 ′) in FIG. 11 is obtained.

Next, in the step (6a) of FIG. 8, the third interlayer insulating film 43, the second interlayer insulating film 42 and the dielectric film 75 are polished and removed by the CMP process up to the horizontal line Lc. Specifically, for example, by flowing a liquid slurry (chemical polishing liquid) containing silica particles on a polishing pad fixed on a polishing plate, the substrate surface fixed on the spindle is brought into rotational contact with the polishing pad. The surface of the third interlayer insulating film 43 is polished, polishing is continued even after the second interlayer insulating film 42 is exposed above the convex portion 502 ', and further after the dielectric film 75 is exposed above the convex portion 502'. Continue polishing.

Next, in the step (6b) of FIG. 8, when the polishing up to the horizontal line Lc is completed, the CMP process is stopped. For example, the CMP process is stopped by time management.
Alternatively, the CMP process is stopped by forming an appropriate stopper layer having the same laminated structure as that shown in the step (6b) of FIG. 8 at a predetermined position on the TFT array substrate 10, for example. The detection of the surface of the stopper layer includes, for example, a friction detection method that detects a change in the coefficient of friction when the stopper layer is exposed, a vibration detection method that detects vibration that occurs when the stopper layer is exposed, and an exposure of the stopper layer. What is necessary is just to carry out by the optical system which detects the change of the reflected light quantity at the time of this.

As described above, according to the second embodiment, the electro-optical device according to the second embodiment is first provided on the substrate 10 with the convex portions 502 ′.
Is formed, and then the portion of the raised interlayer insulating film is flattened by a CMP process in accordance with the process, thereby making it possible to manufacture using a relatively simple process.

(Modifications) Next, various modifications of the electro-optical device according to the present invention will be described.

In one modification, in the configuration of the first embodiment, the protrusions 501 and 502 are formed of island-shaped members arranged on the TFT array substrate 10 independently of forming the grooves 10cv. Alternatively, in the configuration of the second embodiment,
Independently from the fact that the convex portion 502 'forms the groove 10cv, TF
It is made of an island-shaped member arranged on the T-array substrate 10. As the island-shaped member, the same film as another light-shielding film, a dielectric film, a semiconductor layer, a conductive film for wiring, and the like, which are not illustrated in the first embodiment, may be used. It may be additionally formed. Even when the convex portion is configured in this manner, the underlying surface of the pixel electrode 9a near the contact holes 601 and 602 or the connection portion 71e above the convex portion can be flattened.

In another modification, in the configuration of the first embodiment, in addition to or instead of forming the groove 10cv in the substrate 10, a groove is formed in the base insulating film 12, so that the protrusions 501 and 502 is formed. Or,
In the configuration of the second embodiment, in addition to or instead of forming the groove 10cv in the substrate 10, a groove is formed in the base insulating film 12, whereby the convex portion 502 'is formed. Even when the convex portion is configured in this manner, the underlying surface of the pixel electrode 9a near the contact holes 601 and 602 or the connection portion 71e above the convex portion can be flattened.

(Overall Configuration of Electro-Optical Device) FIGS. 12 and 13 show the overall configuration of the electro-optical device configured as described above.
This will be described with reference to FIG. FIG. 12 shows the TFT substrate 10 together with the components formed thereon and the counter substrate 2.
FIG. 13 is a plan view as viewed from the side of FIG.
It is H 'sectional drawing.

In FIG. 12, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof, and in parallel with the sealing material 52, a light shielding as a frame defining the periphery of the image display area 10a is provided. A film 53 is provided. In a region outside the sealing material 52, a data line driving circuit 101 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10. A scanning line driving circuit 1 for driving a scanning line 3a by supplying a scanning signal to the scanning line 3a at a predetermined timing.
04 are provided along two sides adjacent to this one side. If the delay of the scanning signal supplied to the scanning line 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. In addition, the data line driving circuit 10
1 may be arranged on both sides along the side of the image display area 10a. Further, on one remaining side of the TFT array substrate 10, the scanning line driving circuits 10 provided on both sides of the image display area 10a are provided.
A plurality of wirings 105 are provided to connect the four wirings. In at least one of the corners of the counter substrate 20, a conductive material 106 for electrically connecting the TFT array substrate 10 and the counter substrate 20 is provided. Then, as shown in FIG. 13, the opposite substrate 20 having substantially the same contour as the sealing material 52 shown in FIG. 12 is fixed to the TFT array substrate 10 by the sealing material 52.

Note that, on the TFT array substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104, etc., a sampling circuit for applying an image signal to a plurality of data lines 6a at a predetermined timing, a plurality of Data line 6a
A precharge circuit for supplying a precharge signal of a predetermined voltage level prior to the image signal, an inspection circuit for inspecting the quality, defects, and the like of the electro-optical device during manufacturing or shipping. Good.

In the electro-optical device described above with reference to FIGS. 1 to 13, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, TAB (Tape Automated Bonding) The driving LSI mounted on the substrate may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. Also, the side of the opposite substrate 20 on which the projected light is incident and the TFT array substrate 10
For example, the TN mode,
VA (Vertically Aligned) mode, PDLC (Polymer
Operation modes such as (Dispersed Liquid Crystal) mode,
A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to the normally white mode / normally black mode.

Since the above-described electro-optical device is applied to a projector, three electro-optical devices are used as light valves for RGB, and each light valve is provided with a dichroic mirror for RGB color separation. The light of each color decomposed is then incident as projection light. Therefore, in each embodiment, the opposing substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the opposing substrate 20 in a predetermined area facing the pixel electrode 9a together with its protective film.
In this way, the electro-optical device in each embodiment can be applied to a direct-view or reflective color electro-optical device other than the projector. Further, a micro lens may be formed on the counter substrate 20 so as to correspond to one pixel. Alternatively, it is also possible to form a color filter layer with a color resist or the like under the pixel electrode 9a facing the RGB on the TFT array substrate 10. If you do this,
By improving the efficiency of collecting incident light, a bright electro-optical device can be realized. Furthermore, a dichroic filter that produces RGB colors using light interference may be formed by depositing many layers of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with the dichroic filter, a brighter color electro-optical device can be realized.

In addition, according to the present invention, the interlayer insulating film above the projection formed on the substrate is removed by flattening or a contact hole is formed in the interlayer insulating film above the same. The configuration for electrically connecting the upper and lower portions of the film is not limited to the application to the electro-optical device described above, but is applicable to general substrate devices such as semiconductor circuit devices. In particular, the present invention is very effective for applications in which flattening the surface of an interlayer insulating film near a contact hole is useful in some sense.

The present invention is not limited to the above-described embodiment, but can be appropriately modified without departing from the spirit or spirit of the invention which can be read from the claims and the entire specification. The electro-optical device and its manufacturing method, and the substrate device and its manufacturing method are also included in the technical scope of the present invention.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements, wiring, and the like provided in a plurality of pixels in a matrix forming an image display area in an electro-optical device according to an embodiment of the present invention.

FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the electro-optical device of FIG.

FIG. 3 is a sectional view taken along line A-A 'of FIG.

FIG. 4 is a sectional view taken along line B-B 'of FIG.

FIG. 5 is a sectional view taken along the line C-C 'of FIG.

FIG. 6 shows T in each step of the manufacturing process of the present embodiment.
Each of the layers on the FT array substrate side is the same as that of FIG.
It is a process drawing (the 1) shown corresponding to A 'section.

FIG. 7 shows T in each step of the manufacturing process of the present embodiment.
Each of the layers on the FT array substrate side is the same as that of FIG.
It is a process drawing (the 2) shown corresponding to A 'section.

FIG. 8 shows T in each step of the manufacturing process of the present embodiment.
Each of the layers on the FT array substrate side is the same as that of FIG.
It is a process drawing (the 1) shown corresponding to B 'section.

FIG. 9 shows T in each step of the manufacturing process of the present embodiment.
Each of the layers on the FT array substrate side is the same as that of FIG.
FIG. 9 is a process diagram (part 2) shown corresponding to the B ′ cross section;

FIG. 10 is a cross-sectional view showing a connection portion of the second embodiment in a cross section corresponding to the BB ′ cross section shown in FIG. 4;

FIG. 11 is a process chart of the second embodiment corresponding to the process chart shown in FIG. 9;

FIG. 12 is a plan view of a TFT array substrate in an electro-optical device according to an embodiment of the present invention, together with components formed thereon, viewed from a counter substrate side.

13 is a sectional view taken along the line H-H 'of FIG.

[Explanation of symbols]

 1a ... semiconductor layer 1a '... channel region 1b ... low concentration source region 1c ... low concentration drain region 1d ... high concentration source region 1e ... high concentration drain region 2 ... gate insulating film 3a ... scanning line 6a ... data line 9a ... pixel electrode DESCRIPTION OF SYMBOLS 10 ... TFT array substrate 10cv ... Groove 11a ... Lower light-shielding film 12 ... Base insulating film 16 ... Alignment film 20 ... Counter substrate 21 ... Counter electrode 22 ... Alignment film 30 ... TFT 50 ... Liquid crystal layer 70 ... Storage capacitor 71 ... Relay layer 71e Connection part 75 Dielectric film 300 Capacitance line 501, 502, 502 'Protrusion 601, 602, 603 Contact hole

Continued on the front page F term (reference) 2H092 GA48 GA51 GA59 HA25 JA25 JA33 JA35 JA36 JA39 JA43 JB07 JB27 JB54 JB58 JB69 KA04 KA10 KA12 KB02 KB04 KB13 KB25 MA05 MA07 MA08 MA17 MA25 MA29 MA37 NA04 NA07 NA19 NA27 PA02 PA03 Q09 PA10 RA05 5C094 AA10 AA42 AA43 BA03 BA43 CA19 DA15 EA04 EA07 FB15 5F110 AA16 CC02 DD02 DD03 DD05 DD12 DD13 DD14 DD21 EE09 EE45 FF02 FF09 FF23 FF32 GG02 GG13 GG16 GG25 GG47 HL03 NN17 NN05 NN05 NN05 NN17 NN05 NN17 NN05 NN17 NN05 NN05 NN05 NN05 NN05 NN15 NN05 NN73 PP02 PP10 QQ04 QQ05 QQ19

Claims (15)

[Claims] An electro-optical material is sandwiched between a pair of first and second substrates. A pixel electrode, a switching element connected to the pixel electrode, and a switching element connected to the first substrate. A connected wiring, an interlayer insulating film formed between the pixel electrode, the switching element, and the wiring, and a connection portion electrically connected between the pixel electrode, the switching element, and the wiring. A protrusion is formed in at least one region of the connection portion of the first substrate, a lower connection portion of the connection portion is raised by the protrusion, and the interlayer on the lower connection portion is An electro-optical device, wherein the insulating film is removed and is electrically connected to the upper connection portion. 2. The electro-optical device according to claim 1, wherein the interlayer insulating film is removed by a CMP (Chemical Mechanical Polishing) process at a position facing the convex portion. 3. The electro-optical device according to claim 1, wherein the interlayer insulating film is removed by forming a contact hole at a position facing the projection. 4. The pixel electrode and the switching element are electrically connected to each other by relaying a relay layer, and the interlayer insulating film is removed at a position facing the projection, and 4. The electro-optical device according to claim 1, wherein at least one of between the relay layer and between the switching element and the relay layer is electrically connected. 5. . 5. The electro-optical device according to claim 1, wherein a height of the protrusion is substantially equal to a thickness of the interlayer insulating film. 6. The electro-optical device according to claim 1, wherein the protrusion is formed as a part of the first substrate. 7. The first substrate has a groove in which the wiring and the switching element are at least partially buried via the interlayer insulating film, and the protrusion does not have the groove. The electro-optical device according to claim 6, wherein the electro-optical device is formed by: 8. The electro-optical device according to claim 1, wherein the protrusion is formed from an island-shaped member provided on the first substrate. 9. The electro-optical device according to claim 1, wherein the projection has a taper. 10. The semiconductor device according to claim 1, further comprising a base insulating film laminated below the switching element, wherein the protrusion is formed on the base insulating film instead of or in addition to the substrate. The electro-optical device according to claim 1. 11. A method for manufacturing an electro-optical device according to claim 1, wherein the step of forming the convex portion on the first substrate includes the steps of: Forming the switching element such that the lower connection portion of the switching element is located above the portion; forming the interlayer insulating film above the switching element; and opposing the protrusion. Removing the interlayer insulating film to expose the lower connecting portion; and forming the interlayer insulating film such that the upper connecting portion of the wiring or the pixel electrode is located on the exposed lower connecting portion. Forming the wiring or the pixel electrode thereon. 12. The method according to claim 11, wherein, in the exposing step, the lower connection portion is exposed by flattening the interlayer insulating film by a chemical mechanical polishing (CMP) process. A method for manufacturing an electro-optical device. 13. The method according to claim 13, wherein the step of forming the protrusion is performed by the first step.
13. The method according to claim 11, further comprising etching the substrate so as to leave the convex portion, and forming a groove in which the wiring and the switching element are at least partially embedded via the interlayer insulating film. 3. The method for manufacturing an electro-optical device according to claim 1. 14. A first conductive film having a first plane pattern on the substrate, an interlayer insulating film laminated on the first conductive film, and a second plane formed on the interlayer insulating film. A second conductive film having a pattern, wherein a protrusion is formed on the substrate, and the interlayer insulating film is removed by being flattened at a portion facing the protrusion, and the first conductive film is removed. A substrate device, wherein a conductive film is electrically connected to the second conductive film. 15. A method for manufacturing a substrate device for manufacturing the substrate device according to claim 14, wherein: the step of forming the convex portion on the substrate; and the lower portion of the first conductive film above the convex portion. Forming the first conductive film so that the side connection portion is located; forming the interlayer insulating film above the first conductive film; and forming the interlayer insulating film at a position facing the convex portion. Removing the lower connection portion by planarization to expose the lower connection portion; and forming the upper connection portion of the second conductive film on the exposed lower connection portion on the interlayer insulating film. The second
Forming a conductive film.