JP2001028715A - CCD type solid-state imaging device - Google Patents

Abstract

(57) [Abstract] [Problem] Low power consumption, easy to drive and easy to use C
As one method for realizing a CD-type solid-state imaging device, reduction of a power supply voltage of a CCD output circuit has been considered.
In this case, CC for extracting the signal charge from the photoelectric conversion element group
A drop in the D read pulse voltage also occurs at the same time, which causes a problem of malfunction of the CCD, and a problem is to reduce the power supply voltage related to the solid-state imaging device substrate and to realize an element that maintains stable operation of the CCD. Was. In the two-dimensional CCD solid-state imaging device, the voltage of a vertical CCD readout pulse generation circuit is reduced together with the power supply voltage of an output circuit section, and the output of the pulse generation circuit is time-integrated via a capacitor. The result is added to the output of the pulse generation circuit, and the voltage required by the CCD is realized by the result of the synthesis.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD type image pickup device, and more particularly to a two-dimensional CCD type image pickup device which can be easily driven with low power consumption and has an output circuit with low power consumption and low noise.

[0002]

2. Description of the Related Art Conventionally, a CCD type solid-state imaging device has been widely used as a solid-state imaging device used in a home video camera or the like. Such a conventional CCD type solid-state imaging device has an element configuration called an inter-line type shown in FIG. 15, is driven under the driving conditions shown in Table 1, and is used in a camera system by the configuration shown in FIG. .

In FIG. 15, 1 is a photodiode for performing photoelectric conversion, 2 and 3 are a vertical CCD and a horizontal CCD for transferring signal charges photoelectrically converted by the photodiode,
4 is an output gate for separating the horizontal CCD 3 and the output circuit.
And 5, a reset transistor for resetting the floating diffusion layer to which the signal charge is sent from the horizontal CCD 3 every transfer cycle of the horizontal CCD, and 6 and 8, respectively, a driver transistor and a load transistor constituting a first stage source follower. , 9, and 10 are a driver transistor and a load transistor, respectively, which constitute the next-stage source follower. A partition in the vertical CCD 2 indicates one transfer stage composed of one polysilicon electrode, and a partition in the horizontal CCD indicates one transfer stage composed of first-layer polysilicon and second-layer polysilicon electrode. Boron ions are implanted below the horizontal CCD 3 and the second-layer polysilicon electrode forming the output gate to lower the channel voltage. The reset transistor 5 is a depression type transistor similar to the one below the first layer polysilicon electrode constituting the horizontal CCD. v1, v2, v3, v4 are vertical C
Input terminal of a four-phase pulse for driving CD2, h
1 and h2 are input terminals of a two-phase pulse for driving the horizontal CCD 3, og is a DC bias voltage input terminal of the output gate, RG is a reset pulse input terminal, rd is a reset voltage input terminal of the floating diffusion layer, vg is the gate voltage input terminal of the load transistor, od is the power supply voltage input terminal of the output circuit, sub is the substrate voltage input terminal, well is the well voltage input terminal, vss is the well voltage input terminal of the protection circuit, and out is the signal output. Terminal.

The signal charge photoelectrically converted by the photodiode 1 is applied with a high voltage to the terminal v1 or v3 and is sent to the vertical CCD 2 collectively. Then, the voltage levels of the medium voltage and the low voltage are applied to the terminals v1 to v4. Are applied and transferred to the horizontal CCD 3 line by line.
Two-phase pulses are applied to the terminals and are sequentially transferred in the horizontal CCD 3. A potential change due to the signal charge transferred from the horizontal CCD 3 to the floating diffusion layer is detected by a first-stage source follower including transistors 6 and 8, and transistors 9 and 9
The signal is output to an out terminal by a next-stage source follower composed of 10. Next, a reset pulse is applied to the rg terminal, the reset transistor 5 is turned on, and the floating diffusion layer
It is applied to the d terminal and reset to the reset voltage. The above operation is repeated, and signals are sequentially output. Also, s
Normally, a predetermined DC voltage is applied to the ub terminal to discharge excess charges generated by the photodiode, and a high voltage is applied during scanning to realize an electronic shutter for improving dynamic resolution and preventing flicker. Is done.

The CCD type solid-state imaging device having such a configuration and operation is generally driven under the driving conditions shown in Table 1. Table 1 shows an example of a pulse applied to each terminal shown in FIG. 15 and a DC bias voltage. Using the well terminal voltage as a reference voltage, negative voltage vertical CCD scanning at the v1 to v4 terminals, in which the lowest voltage is set to be equal to or less than the voltage at which the p-type inversion layer is formed on the surface of the vertical CCD n layer (hereinafter, pinning voltage) to reduce dark current When a pulse is applied and a signal charge is transferred from the photodiode to the vertical CCD, a high voltage is applied to the v1 and v3 terminals. The output voltage of the timing generator shown in FIG. 16 is directly applied to the terminals h1 and h2. This is to prevent unnecessary power consumption due to the provision of the driver, and to reduce the power consumption of the camera system. Further, in order to transfer the charge from the horizontal CCD to the output diffusion layer without interruption, a voltage equal to the high voltage of the horizontal CCD transfer pulse applied to the h1 and h2 terminals is applied to the og terminal, and the output gate is applied to the rd terminal. A voltage that is sufficiently higher than the channel voltage below is applied. rg
The low voltage at the terminal is equal to the low voltage of the horizontal CCD transfer pulse to prevent leakage of signal charges from the floating diffusion layer, and the high voltage is sufficiently higher than the high voltage of the horizontal CCD transfer pulse to achieve a sufficiently low on-resistance. Apply voltage. Also, o
The same voltage as that of the rd terminal is applied to the d terminal so as not to increase the number of voltage values. On the other hand, the DC voltage for discharging excess charges applied to the sub terminal varies for each element, so that adjustment is made for each element, and the high voltage for the electronic shutter pulse is set to the upper limit of the variation of the elements.

[0006]

[Table 1] The CCD type solid-state imaging device described above is used in a camera with the configuration shown in FIG. In the figure, reference numeral 161 denotes the CCD solid-state imaging device shown in FIG. 15; 162, a timing generator for driving the CCD solid-state imaging device 161; 163, a driver for setting the voltage value of each pulse to a predetermined value; 16
Reference numeral 4 denotes a correlated double sampling circuit for removing noise from the output of the CCD solid-state imaging device 161; 165, an automatic gain control circuit that changes the voltage gain according to the signal output level; 166, an A / D converter; , A digital signal processing circuit; 168, a D / A converter;
It is a C-DC converter. Timing generator 162, correlated double sampling circuit 164 and automatic gain control circuit 16
5. Digital signal processing device 167, A / D converter 16
6. The D / A converter 168 is formed of a single-chip integrated circuit that operates on a single power supply.

The CCD type solid-state image pickup device 161 generates timing by a timing generator 162 and outputs the timing to the DC-DC converter 1.
The output signal from the element is driven by a pulse having a predetermined voltage value by a driver 163 supplied with a voltage by a driver 69 and a DC voltage supplied from a DC-DC converter 169. After noise removal and gain control by the control circuit 165, the A / D converter 1
The digital signal is converted into a digital signal by the digital signal processor 66, the signal is processed by the digital signal processor 167, and the D / A converter 1
The signal is converted to an analog signal by 68 and becomes a TV signal.

[0008] This type of CCD solid-state image pickup device is described in, for example, Technical Report of the Institute of Television Engineers of Japan, Vol.
No. 11 pp. 61-72 (1989.2), Technical Report of the Institute of Television Engineers of Japan, Vol. 31-36
(1988.2), a digital signal processor for a camera using a CCD solid-state image pickup device of this type is described in the ISSS Digest of Technical Papers No. 250.
Page to page 251 (1991) (ISSCCDIGES
T OF TECHNICAL PAPERS pp.
250-251 (1987)).

[0009]

The above prior art is based on CC
Driving of the D-type solid-state imaging device does not consider usability improvement and low power consumption, and the imaging device is inconvenient.
It is difficult to reduce the power consumption of the camera. Further, there is a problem that it is difficult to reduce power consumption and noise of an output circuit in the image sensor. That is, first, as the peripheral circuits become more single-powered, the driving of the CCD type image pickup device shown in FIG. 15 requires a pulse having a multi-level voltage level shown in Table 1 and a DC voltage. The driver 163 that generates these and DC
-A DC converter 169 had to be provided in the camera system. This has made the CCD type image sensor difficult to handle. In addition, as camera adjustments are progressing due to digitization of signal processing circuits, su
The fact that the DC voltage for discharging the excess charge applied to the terminal b must be adjusted for each element has also been another factor that makes the CCD type imaging element difficult to handle.

Second, in order to reduce the power consumption of the camera, the power supply voltage of the timing generator 162 and the signal processing device 167 is changed from the current 5 V to 3.3 V, and further, 1.5 V.
And lower voltage. However, it is difficult to lower the drive voltage of the horizontal CCD 3 that requires high-speed transfer. Accordingly, the output voltages of the timing generator 162 are h1, h2
It becomes difficult to drive the horizontal CCD 3 by applying a voltage to the terminal, and it is necessary to provide a driver for driving the horizontal CCD in the camera system. When the driver section is provided outside the image sensor as described above, reactive power for driving a parasitic capacitance such as a wiring capacitance between the driver and the image sensor or a pin capacitance of the image sensor is generated, which is one of the causes of reducing the power consumption of the camera. Had become. Further, the DC for generating the above-described multi-value voltage
The power of the -DC converter 169 cannot be reduced, which has been another factor in reducing the power consumption of the camera.

Third, the timing generator 162
Is applied to the h1 and h2 terminals to drive the horizontal CCD 3, the channel voltage of the horizontal CCD is high and the rd terminal voltage is high. As a result, rd
The od terminal voltage, which is the power supply voltage of the output circuit set to the same voltage as the terminal, also increases, and the power consumption generated in the output circuit increases. Furthermore, since the power supply voltage is high, it is difficult to use a transistor having a short channel length, and there is a problem that noise is large.

Accordingly, a first object of the present invention is to provide a CCD solid-state imaging device which is easy to drive and easy to use.

A second object of the present invention is to provide a CCD type image sensor capable of reducing the power consumption of a camera.

Still another object of the present invention is to provide an output circuit of a CCD type solid-state imaging device which reduces the power supply voltage of the output circuit, consumes less power, and has low noise.

[0015]

To achieve the above first and second objects, a CCD type solid-state image pickup device according to the present invention comprises, as shown in FIG. With pulse and positive and negative power supply, vertical CC
D, a horizontal CCD, a reset transistor, and at least a voltage generation circuit (11 to 17) for driving an output circuit with a predetermined pulse voltage and a DC voltage by input of a trigger pulse.

Alternatively, the positive and negative two power supplies have a positive power supply value (VDD) equal to the power supply voltage value of the output circuit.
And a negative power supply value (Vss) equal to the lowest voltage value of the transfer pulse of the vertical CCD.

Alternatively or additionally, the voltage generating circuit includes a first conductivity type MOS transistor formed in the same manner as the first conductivity type MOS transistor of the output circuit, and a second conductivity type MOS transistor on the surface of the photoelectric conversion element. Complementary MOS in which a second conductivity type MOS transistor which forms a source / drain diffusion layer together with formation of a second impurity layer is interconnected.
A structure of a transistor is provided.

Here, the voltage generating circuit is a complementary MOS
The voltage generating circuit includes a first and a second complementary MO connected between a positive power supply and a ground power supply, between a ground power supply and a negative power supply, or between a positive power supply and a negative power supply.
S-transistor configuration, each complementary MOS
The gates of the transistors are connected to form an input point, the connection point between the source and drain of each complementary MOS transistor is set as an output point, and a trigger pulse is input to the input point of the first complementary MOS transistor. The output and input points of the second complementary MOS transistor are connected to each other, and the second
It is preferable to provide a configuration of a pulse generation circuit that uses the output point of the complementary MOS transistor as the output point of these circuits in order to reduce the power of the voltage generation circuit.

Here, in order to generate a negative output pulse in the above-mentioned pulse generating circuit by a positive input trigger pulse,
In the case of a pulse generating circuit supplied with negative power, the input point of the pulse generating circuit may be connected to an external pulse terminal via a capacitor and to a negative power terminal via a clamp diode.

In the case of a vertical CCD transfer pulse generation circuit as the voltage generation circuit, for example, as shown in FIG. 3, the pulse generation circuit is provided between a ground power supply and the negative power supply, An output pulse having a negative power supply value may be generated, and the output pulse may be applied to the vertical CCD.

Alternatively, for a vertical CCD tri-level pulse generating circuit for applying a ternary pulse of the negative power source value, the positive power source value, and the low voltage value to the vertical CCD, for example, as shown in FIG. A vertical CCD transfer pulse generation circuit having the above-mentioned pulse generation circuit between the positive power supply and the ground power supply, and generating an output pulse of the negative power supply value in response to the input of a trigger pulse, and an output of the positive power supply value A vertical CCD readout pulse generating circuit for generating a pulse may be provided, and a switch circuit for switching the output of both circuits may be provided to apply the output to the vertical CCD.

As a voltage generating circuit for achieving the above-mentioned second and third objects, a horizontal CCD transfer pulse generating circuit applied to a horizontal CCD, for example, as shown in FIG.
In addition to the above-described pulse generating circuit between the ground power supply and the negative power supply, the output of the circuit has a voltage amplitude limiting means for generating a negative voltage pulse whose voltage amplitude is limited from the negative power supply value pulse by input of a trigger pulse. To be applied to the horizontal CCD.

As shown in FIG. 6, for example, as shown in FIG. 6, a reset pulse generating circuit for applying a pulse voltage to the gate of the reset transistor has the above-mentioned pulse generating circuit between the positive power supply and the ground power supply and receives a trigger pulse. The voltage may be amplified to generate a pulse voltage, and this may be applied to the gate.

In order to achieve the third object by lowering the output voltage, the reset voltage generating circuit has the pulse generating circuit between a positive power supply and a ground power supply as shown in FIG. And a means for boosting and smoothing the voltage, and applying the boosted voltage to the drain of the reset transistor by input of a trigger pulse.

Here, as means for boosting the pulse voltage, one terminal of a capacitor is connected to the output point of the pulse generation circuit between the positive power supply and the ground power supply, and the other terminal of the capacitor is connected to the positive terminal. What is necessary is just to provide a configuration in which the diode is connected to the power supply and the other terminal and the output terminal are diode-connected.

In order to achieve the first object, a substrate voltage generating circuit for applying a voltage to a substrate for discharging an excessive voltage has the above-described pulse generating circuit between a positive power supply and a negative power supply. Having a DC power supply for the substrate, connecting a capacitor between the output point of the pulse generation circuit and the substrate,
In addition, the configuration may be such that the substrate and the DC power source for the substrate are connected via a switch including a depletion transistor. The voltage drop can be reduced by using the depletion transistor, and a high voltage can be applied to the substrate at high speed by capacitively coupling between the output point of the pulse generation circuit and the substrate.

Here, as the substrate DC power supply, for example, a positive power supply may be used as shown in FIG. 9 or, as shown in FIG. A circuit for generating and a means for adjusting the DC voltage may be provided so that the adjusted DC voltage is output to be applied to the substrate.

In this case, as a circuit for generating a DC voltage applied to the substrate, a DC voltage to be applied to the substrate is generated by stepping down from a voltage obtained by boosting the positive power supply voltage, and means for adjusting the DC voltage is used. If the step-down voltage is adjusted based on the voltage of the bias voltage generating circuit provided with the voltage adjusting means, the substrate voltage can be adjusted inside the element, and the usability is improved.

The vertical CCD ternary pulse generating circuit for applying a read voltage higher than the positive power supply voltage to the vertical CCD, for example, as shown in FIG. And a second and third complementary MOS transistors having the same configuration as the pulse generation circuit.
A transistor structure is added between the positive power supply and the ground power supply, and an input point connecting the gates of the third complementary transistor is connected to an output point of the second complementary MOS transistor. What is necessary is just to add a configuration in which the output point connecting the source and the drain of the type MOS transistor is connected to the vertical CCD via a capacitor.

An output circuit for achieving the third object has a multistage amplifier configuration.
It is assumed that the substrate impurity concentration of the driver transistors in the next and subsequent stages is lower than the substrate impurity concentration of the first stage driver transistor.

In the CCD type solid-state image pickup device of the present invention for achieving the first and second objects, the device which operates by receiving a single trigger pulse and two positive and negative power supplies from the outside includes: For example, as shown in FIG. 14, a timing generator for generating a plurality of trigger pulses at desired timing from the basic clock using the single external trigger pulse as a basic clock, and driving a built-in voltage generating circuit by the trigger pulse. Built-in.

Then, it is sufficient that the built-in timing generator gives a trigger pulse to the above-mentioned voltage generating circuit.

[0033]

According to the present invention, a trigger pulse from the outside and positive and negative 2
If a voltage generating circuit for generating a pulse of a predetermined voltage level and a predetermined DC voltage after power supply is built in the CCD type imaging device, a power supply of various voltage levels was conventionally required as an external power supply. However, the number of types of power supplies can be reduced.

In this case, the present invention focuses on the following points regarding the two power supply values and the formation of the built-in circuit. That is, the power supply voltage of the output circuit has the highest positive voltage value among the power supply voltages that require a large current driving capability for driving the CCD image pickup device, and the lowest voltage of the transfer pulse of the vertical CCD. Has the lowest negative voltage value.

Since the booster circuit of the integrated circuit usually has a small current driving capability, a trigger pulse is obtained by setting such a maximum positive voltage value or a minimum negative voltage value as a positive or negative power supply value and from the outside. This makes it possible to generate a pulse of a predetermined voltage and a DC voltage for driving the CCD with low power consumption.

In order to further reduce the power consumption of the built-in integrated circuit, it is desirable to form the circuit with complementary MOS transistors. Forming a one conductivity type MOS transistor, forming a second conductivity type second impurity layer on the surface of the photoelectric conversion element, and forming a second conductivity type MOS of the complementary MOS transistor;
By forming the source / drain diffusion layer of the transistor, it is possible to form the complementary MOS transistor without changing the manufacturing process for forming the CCD type imaging device.

By adopting such a power supply value and circuit formation based on the viewpoint, a low power consumption voltage generating circuit for driving a vertical CCD, a horizontal CCD, a reset transistor, and an output circuit with a predetermined pulse voltage and a DC voltage is used. It can be conveniently built in by being formed together with the solid-state imaging device.

As described above, according to the present invention, the conventional driver 16 as shown in FIG.
3 need not be provided, and the DC-DC converter 1
It is only necessary to supply two positive and negative voltages to the image sensor 69. As a result, usability of the CCD solid-state imaging device is improved. Further, since the number of voltage values supplied by the DC-DC converter is reduced, the power consumption of the camera can be reduced.

Further, a circuit for generating a DC voltage applied to the substrate by an external power supply is provided in the CCD image pickup device, and means for adjusting the DC voltage is provided. No adjustment is required when creating the system. As a result, usability of the CCD solid-state imaging device is improved.

The horizontal CCD transfer pulse generation circuit applies pulses of a predetermined voltage level to the terminals h1 and h2 in FIG. 15 with a pulse from the timing generator as a trigger. As a result, even if the power supply voltage of the timing generator drops, it is not necessary to provide a driver outside the element. Therefore, there is no generation of reactive power in the driver, the power supply voltage of the timing generator 162 and the signal processing device 167 in FIG. 16 can be reduced, and the power consumption of the camera can be reduced.

Alternatively, by making at least the low voltage of the horizontal buffer circuit negative, the channel voltage below the horizontal CCD becomes low, and the rd terminal voltage in FIG. 15 can be lowered. Further, by generating the rd terminal voltage from the od terminal voltage by the booster circuit, the od terminal voltage can be further reduced without increasing the number of power supplies supplied from outside the element. Usually, in order for the first-stage driver transistor to perform a saturation operation and the output circuit to operate in a linear range, the od terminal voltage needs to be higher than a value obtained by subtracting a threshold voltage of the first-stage driver transistor from the rd terminal voltage. Therefore, the threshold voltage of the first-stage driver transistor may be set to a high value in order to lower the odd terminal voltage. However, in the case where the next-stage driver has the same structure as the first-stage driver as described in FIG. 15, if the threshold voltage of the transistor is too high, the next-stage driver transistor does not conduct sufficiently and the operation of the next stage becomes difficult. Become. Therefore, in the present invention, the substrate impurity concentration of the driver transistor of the subsequent stage is made lower than the substrate impurity concentration of the driver transistor of the first stage, the threshold voltage of the first stage driver transistor is increased, the od terminal voltage is reduced, and the driver The threshold voltage of the transistor was lowered so that the next stage operates in the linear operation range. As a result, the voltage of the od terminal, which is the power source of the output circuit, can be reduced, and power consumption can be reduced. In addition, a reduction in the power supply voltage enables the use of a short-channel transistor, thereby reducing noise.

[0042]

【Example】First embodiment  A first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is an overall configuration diagram of the first embodiment, and FIG.
FIG. 2B is a cross-sectional view taken along the line A-A ′ in FIG.
(C) is a cross-sectional view of the B-B 'portion of FIG.
FIG. 3 is a sectional view of a portion corresponding to the star, and FIG.
FIG. 4 is a vertical CCD transfer pulse generating circuit according to the first embodiment.
FIG. 5 is a circuit diagram of a direct CCD ternary pulse generating circuit according to the first embodiment.
FIG. 6 shows a flat CCD transfer pulse generating circuit according to the first embodiment.
FIG. 7 is a reset pulse generation circuit of the first embodiment.
FIG. 8 shows an output circuit according to the first embodiment.
FIG. 9 shows a bias voltage generation circuit for a load transistor.
11 is a substrate voltage generation circuit according to the embodiment.

In FIG. 1, 1 to 10 are the same as in FIG. However, the reset transistor 5 is a depletion type transistor in which the same ion implantation is performed as under the second layer polysilicon electrode constituting the horizontal CCD.
11 is a substrate voltage generation circuit shown in FIG. 9, 12 is a vertical CCD transfer pulse generation circuit shown in FIG. 3, 13 is a vertical CCD ternary pulse generation circuit shown in FIG. 4, and 14 is a horizontal CC shown in FIG.
D transfer pulse generation circuit, 15 is a reset pulse generation circuit shown in FIG. 6, 16 is a reset voltage generation circuit shown in FIG. 7,
Reference numeral 17 denotes a bias voltage generating circuit for the output circuit load transistor shown in FIG. V1, V2, V3, V4 are vertical C
CD2 transfer pulse trigger-input terminal, V1R, V3
R is a trigger of a read pulse of the vertical CCD 2-an input terminal, and H1 and H2 are a trigger of a transfer pulse of the horizontal CCD 3-
Input terminal, RG is a reset pulse trigger input terminal,
SUB is an electronic shutter pulse trigger input terminal, W
ELL is a well voltage input terminal, VDD is a positive power supply voltage input terminal, Vss is a negative power supply voltage input terminal, and OUT is a signal output terminal. Timing generator trigger pulse and positive,
A pulse having a predetermined voltage and a DC voltage are generated inside the element from the two negative power supplies, and the same operation as described in FIG. 15 is performed.

Generally, a booster circuit used in an integrated circuit has a low current driving capability. Therefore, the positive power supply needs to be higher than the maximum voltage that requires a large current driving capability, and the negative power supply needs to be lower than the minimum voltage that requires a large current driving capability. In the case of a two-dimensional CCD image sensor, a large current driving capability is required for the high and low voltages of the transfer pulses of the vertical CCD 2 and the horizontal CCD 3 and the power supply voltage of the output circuit. As a result, the positive power supply voltage value may be higher than the power supply voltage value of the output circuit. In the present embodiment, the positive power supply value is set equal to the power supply voltage value of the output circuit in order to prevent unnecessary power consumption since a through current always flows through the power supply of the output circuit. The negative power supply value may be lower than the lowest voltage value of the transfer pulse of the vertical CCD. In this embodiment, the negative power supply value is set equal to the lowest voltage value of the transfer pulse of the vertical CCD so that an unnecessary step-down device may not be provided. That is, in this embodiment, the positive power supply value is equal to the power supply voltage value of the output circuit, and the negative power supply value is equal to the lowest voltage value of the transfer pulse of the vertical CCD. It is possible to easily generate a pulse having a predetermined voltage and a DC voltage from the two power supplies inside the element.

In order to reduce power consumption in the built-in circuits 11 to 17, it is desirable that the circuit be constituted by complementary MOS transistors. In the present embodiment, such a complementary transistor is realized without any change in a manufacturing process for forming a CCD image sensor.

This point will be described with reference to FIG. FIG. 1A is a cross-sectional view of a portion corresponding to the AA 'part of FIG. In the figure, 20 is an n-type substrate, 21 is p
22 is a p-type double well for preventing unnecessary charges such as smear charges from being mixed into the CCD n layer 23;
D polysilicon electrode, 25 is a photodiode n layer 26
An n-well 27 for discharging excess charges from the substrate to the substrate at a low voltage, a p + layer 27 provided on the surface of the photodiode for suppressing dark current, and a second layer aluminum 28 for light shielding. FIG. 1B is a cross-sectional view of the n-channel transistor taken along the line BB ′ of FIG. In the figure,
20, 21, 22, and 24 are the same as those in FIG.
Is a first layer aluminum for wiring, and 30 is an n-type source drain diffusion layer of an n-channel MOS transistor. An n-channel MOS transistor for realizing the built-in circuits 11 to 17 has a structure similar to that shown in FIG. Figure (c) is 1
FIG. 3 shows a sectional structural view of a newly provided p-channel MOS transistor for realizing the internal circuits 1 to 17; 20,
24, 25, and 27 are the same as those in FIG.
Is the same as The contact between the p + layer 27 and the wiring layer 29 is performed simultaneously with the contact between the p-type well 21 and the wiring layer 29 in the conventional example. In this embodiment, the source drain diffusion layer of the p-channel transistor is also used as the p + layer provided on the photodiode surface, so that C
A complementary transistor is realized without any change in a manufacturing process for forming a CD-type image sensor.

When it is desired to lower the threshold voltage of the p-channel transistor, the n-type well 25 need not be provided below the p-channel transistor. Alternatively, an ion implantation of boron, typically made of boron, for adjusting a channel voltage, which is implanted below the second-layer polysilicon electrode of the horizontal CCD, may be implanted below the polysilicon electrode 24. Conversely, if it is desired to increase the threshold voltage, the photodiode n layer 26 may be provided below the transistor.

Further, when it is desired to reduce the threshold voltage of the n-channel transistor, the p-type double well 22 need not be provided below the n-channel transistor.

When using the p-channel transistor of this embodiment, the source drain diffusion layer 27 is
The voltage applied to the n-type substrate is higher than the positive power supply so as not to be forward biased with respect to 0. (1) Vertical CCD transfer pulse generation circuit In order to generate a transfer pulse of a vertical CCD having a low negative voltage by a positive external trigger pulse, it is necessary to carry out a level shift and amplify the voltage.

FIG. 3 shows a vertical CCD transfer pulse generating circuit according to the first embodiment. In the figure, 31 is a coupling capacitance, 32 is a clamp diode, 33 is an n-channel MOS transistor constituting a first inverting circuit, 34 is a p-channel MOS transistor constituting a first inverting circuit, and 35 is a second N-channel MOS transistor constituting an inverting circuit, 36
Is a p-channel MOS transistor constituting a second inverting circuit.

A positive pulse from the outside is transmitted through the coupling capacitor 31 to the input point A clamped by the diode 32 to the negative power supply Vss with a voltage shift. Next, after the voltage is amplified by the first inverting circuit, the current is amplified by the second inverting circuit to be a vertical CCD transfer pulse. Since the voltage amplitude of the external pulse is smaller than the voltage amplitude of the vertical CCD transfer pulse, a through current flows through the first inversion circuit when the voltage of the external pulse is high. In order to reduce the through current and reduce the power consumption, the current driving capability of the first inverting circuit must be reduced, and a large capacity vertical CCD electrode cannot be driven.
Therefore, in the present embodiment, a second inverting circuit is provided so that the first inverting circuit does not need to have a high current driving capability. That is, according to the present embodiment, the input point is coupled to the external pulse by the capacitance, and the level shift and the voltage amplification are performed by providing the first inversion circuit clamped to the negative power supply. By providing a second inverting circuit which receives the output of the vertical CCD as an input, a vertical CCD transfer pulse generator with low power consumption is realized.

The diode 32 can be easily realized by providing an n-type diffusion layer in the p-type well 21 of FIG. Further, the clamp may be performed by a diode-connected MOS transistor. (2) Vertical CCD tri-level pulse generating circuit In this embodiment, a negative power source circuit for generating a vertical CCD transfer pulse and a positive power source circuit for generating a readout pulse are provided, and the output of these two circuits is switched by a switch, so that the vertical CCD tri-level pulse is generated. Generate a pulse.

FIG. 4 shows a vertical CCD ternary pulse generating circuit according to the first embodiment. In the figure, 41 is a coupling capacitance, 42 is a clamp diode, 43 and 37 are n-channel MOS transistors constituting a first inverting circuit, 44 and 38 are p-channel MOS transistors constituting a first inverting circuit,
5 and 39 are n-channel MOSs constituting the second inverting circuit
Transistors, 46 and 40 are p-channel MOS transistors constituting a second inverting circuit, and a circuit composed of 41 to 46 or a circuit composed of 37 to 40 is a circuit similar to FIG. Reference numeral 47 denotes an n-channel MOS transistor serving as a switch between the vertical CCD transfer pulse generation circuit and the vertical CCD electrode, and reference numeral 48 denotes a p-channel M transistor serving as a switch between the read pulse generation circuit and the vertical CCD electrode.
OS transistor. The well of the n-channel MOS transistor 47 is connected to the output of the second inverting circuit to prevent an increase in threshold voltage due to the body effect. Trigger of read pulse of vertical CCD 2-input terminal V1R,
When a low voltage is applied to V3R, the voltage of node B is VDD and the voltage of node C is 0V. As a result, the n-channel MOS transistor 47 conducts and the vertical C
A CD transfer pulse is applied to a node D connected to a vertical CCD electrode. On the other hand, a gate-grounded p-channel M
Since 0 V or the negative power supply voltage Vss is applied to the source drain of the OS transistor 48, it does not conduct. Next, when a high voltage is applied to the trigger input terminals V1R and V3R with the transfer pulse at 0 V,
As a result, the n-channel MOS transistor 47 is turned off. On the other hand, the node C becomes VDD and the p-channel MOS transistor 48 becomes conductive, and VDD is applied to the node D connected to the vertical CCD electrode. As described above, according to the present embodiment, the vertical CCD tri-level pulse is
A negative power supply circuit for generating a CD transfer pulse and a positive power supply circuit for generating a read pulse are provided, and the output of these two circuits is switched by a switch, so that the source-drain voltage of each MOS transistor is set to VDD or Vss.
And a ternary pulse can be generated with a low value. (3) Horizontal CCD transfer pulse generating circuit The horizontal CCD transfer pulse of this embodiment has a negative minimum voltage in order to lower the reset voltage and power supply voltage of the output circuit. Further, the minimum voltage is set to a value higher than the pinning voltage under the second-layer polysilicon electrode of the horizontal CCD in which the ion implantation is performed to reduce the channel voltage so as not to generate an invalid voltage region. As a result, the horizontal CCD
The transfer pulse minimum voltage has a negative value higher than the minimum voltage of the vertical CCD transfer pulse. On the other hand, the voltage amplitude is usually smaller than the vertical CCD transfer pulse to reduce power consumption. Therefore, in this embodiment, the transfer pulse of the horizontal CCD is generated by limiting the voltage amplitude of the negative power supply circuit after level shifting a positive trigger pulse from the outside.

FIG. 5 shows a horizontal CCD transfer pulse generation circuit according to the first embodiment. In the figure, reference numeral 51 denotes a coupling capacitance; 52, a clamp diode; 53, an n-channel MOS transistor forming a first inverting circuit; 54, a p-channel MOS transistor forming a first inverting circuit; N-channel MOS transistor constituting an inverting circuit, 56
Is a p-channel MOS transistor constituting a second inverting circuit, and a circuit composed of 51 to 56 is a circuit similar to FIG. 57 is a p-channel MOS transistor for limiting the negative voltage of the pulse, and 58 and 59 are p-channel MOS transistors.
P-channel MOS transistors for applying a bias voltage to the gate of channel MOS transistor 57;
Reference numerals 1 and 62 denote n-channel MOS transistors constituting a bias voltage generating circuit. The wells of the n-channel MOS transistors 60, 61 and 62 are connected to their respective sources.
And the threshold voltage of each transistor is equal. The negative voltage of the pulse generated by the trigger pulse applied to the H1 and H2 terminals is limited by the p-channel MOS transistor 57 and becomes a horizontal CCD transfer pulse. When the output of the second inverting circuit is 0 V, the node E is a p-channel MOS from the bias voltage of the bias voltage generating circuit.
The value is higher by the threshold voltage of the transistor 59. When the output of the second inverting circuit becomes Vss, the voltage of the node E decreases due to the capacitive coupling between the drain of the transistor 57 or the source and the gate. After this, node E
Becomes lower than a certain voltage, the transistor 58 is turned on, and the node E is clamped to a value lower than the bias voltage of the bias voltage generating circuit by the threshold voltage of the p-channel MOS transistor 58. As a result, the output of the second inverting circuit becomes the p-channel MOS transistor 57 from the node E.
Is limited to a value higher by the threshold voltage, that is, a value equal to the bias voltage of the bias voltage generating circuit. According to the present embodiment, the transfer pulse of the horizontal CCD can be generated by limiting the voltage amplitude of the negative power supply circuit after level shifting the external positive trigger pulse.

In order to limit the high voltage of the pulse, transistors 57 to 59 may be n-channel MOS transistors and a desired bias voltage may be applied.

Further, a voltage limiter may be applied to the power supply voltage in order to limit the pulse voltage. (4) Reset pulse generation circuit In this embodiment, the DC bias voltage of the output gate is set to 0 V which is the high voltage of the horizontal CCD transfer pulse. The reset transistor 5 is a depletion type transistor similar to that under the second-layer polysilicon electrode constituting the output gate. As a result, in order to prevent signal charges from leaking from the floating diffusion layer, the low voltage of the reset pulse may be 0 V or less. Therefore, in the present embodiment, a reset pulse is generated by a circuit that uses two power supplies of positive power and 0 V.

FIG. 6 shows a reset pulse generating circuit according to the first embodiment. In the figure, reference numeral 63 denotes n which forms a first inverting circuit.
A channel MOS transistor; 64, a p-channel MOS transistor forming a first inverting circuit; 65, an n-channel MOS transistor forming a second inverting circuit;
Reference numeral 6 denotes a p-channel MOS transistor constituting a second inverting circuit, and the circuit constituted by 63 to 66 is the same as that in FIG. According to this embodiment, the reset pulse can be generated by voltage-amplifying a positive trigger pulse from the outside. (5) Reset voltage generation circuit In this embodiment, in order to reduce the power supply voltage of the output circuit, the reset voltage is generated separately from the power supply voltage of the output circuit, and the reset voltage is generated by boosting the power supply voltage of the output circuit.

FIG. 7 shows a reset voltage generating circuit according to the first embodiment. In the figure, 63 to 66 are the same as in FIG.
Reference numeral 1 denotes a charge pump capacitor; and 72 and 73, diode-connected n-channel MOS transistors. In addition,
The well of n-channel MOS transistor 72 has power supply VD
D to prevent an increase in threshold voltage due to the substrate effect. Due to the charge pump by the trigger pulse, the reset voltage is about twice the DC voltage lower than the positive power supply voltage VDD by the threshold voltage of the n-channel MOS transistor. According to the present embodiment, the reset voltage is generated by boosting the reset voltage from the power supply voltage of the output circuit, so that the power supply voltage of the output circuit can be made lower than the reset voltage without increasing the number of externally supplied power sources. it can.

When an n-channel MOS transistor having a low threshold voltage is required to obtain a high reset voltage, a transistor having the structure shown in FIG. 2B and having no double p-well may be used. (6) Load transistor bias voltage generation circuit FIG. 8 shows a load transistor bias voltage generation circuit.
In the figure, 81, 82 and 83 are n-channel MOS transistors constituting a bias voltage generating circuit. The wells of the n-channel MOS transistors 81, 82 and 83 are connected to their respective sources, and the threshold voltages of the transistors are equal. The power supply voltage is divided into one third by a diode-connected transistor to become a load bias voltage. It is needless to say that the bias voltage can be freely set as required. (7) Substrate Voltage Generating Circuit It is necessary to apply a DC voltage for discharging excessive voltage to the n-type substrate 20 at all times, and to apply a high positive voltage during the operation of the electronic shutter. In this embodiment, this high voltage is applied to an external trigger.
A pulse, which is amplified in voltage from the pulse, is applied to the substrate by capacitive coupling to generate the pulse.

FIG. 9 shows a substrate voltage generating circuit according to the first embodiment. In the figure, reference numeral 91 denotes a coupling capacitance, and 92 denotes a clamp diode.
And 93, an n-channel MOS constituting a first inverting circuit
A transistor, 94 is a p-channel MOS transistor forming a first inverting circuit, 95 is an n-channel MOS transistor forming a second inverting circuit, 96 is a p-channel MOS transistor forming a second inverting circuit, 91
To 96 are the same as those in FIG.
Reference numeral 97 denotes a coupling capacitance between the second inverting circuit and the substrate;
Is a substrate capacitance, and 98 is a switch between the DC voltage VDD applied to the substrate and the substrate. The switch 98 is a CCD
N-channel depression M similar to
It consists of an OS transistor. When the voltage applied to the SUB terminal is low, the voltage of the node F becomes VDD, the switch 98 is turned on, and the substrate voltage becomes VDD. On the other hand,
De G is Vss. When the voltage applied to the SUB terminal increases, first, the node F becomes Vss, and the switch 98 is closed. Thereafter, the node G is changed from Vss to VDD.
And the substrate voltage is (VDD−Vss) voltage of 9
It increases by a value obtained by dividing the capacitance by 7 and the substrate capacitance 99. In this embodiment, as described above, a high voltage can be applied to the substrate at a high speed by boosting the voltage by capacitive coupling. Further, by using an n-channel depletion MOS transistor constituting a CCD as a switch, VDD can be applied to the substrate without voltage drop and boosting is possible.

When it is desired to increase the coupling capacitance in order to increase the amplitude of the shutter pulse, the coupling capacitance may be provided outside the element.

When it is not necessary to increase the amplitude of the shutter pulse, the low-voltage power supply Vss may be set to 0V.

Further, when a high voltage applied between the gate and drain when the switch 98 is turned off becomes a problem, a voltage limiter similar to that described with reference to FIG. As a result, the low voltage applied to the gate of the switch 98 can be set to the minimum voltage at which the switch becomes non-conductive when the source voltage is VDD, and the gate-drain voltage can be reduced.

According to the above-described embodiment, the outside of a single level
It can be driven by the unit pulse and two positive and negative power supplies,
Two-dimensional CCD that enables good camera power consumption
Type solid-state imaging device can be provided. Also, negative from external pulse
Circuit for generating horizontal CCD drive pulse of value, output circuit
Built-in boost circuit that generates reset voltage from power supply voltage
Power supply voltage of the output circuit can be lowered,
An output circuit with low power and low noise can be realized.Second embodiment  In the vertical CCD ternary pulse generating circuit of the first embodiment,
When the output pulse voltage is VDD and the voltage value is insufficient
There is. In the present embodiment, the positive power supply voltage VDD is used to drive the vertical CCD.
After applying the voltage to the moving electrode,
A read voltage higher than the positive power supply voltage is realized.
You.

FIG. 10 shows a vertical CCD ternary pulse generating circuit according to the second embodiment. In the figure, 41 to 47, 48, 37
To 40 are the same as in FIG. 104 is an n-channel MOS transistor forming a third inverting circuit, 105 is a p-channel MOS transistor forming a third inverting circuit, and 106 is an n-channel MOS forming a fourth inverting circuit.
The S transistor 107 is a p-type transistor forming a fourth inversion circuit.
A channel MOS transistor 103 is a diode-connected n-channel MOS transistor for boosting the voltage.
2, a gate-grounded p-channel MOS transistor for transmitting a boost pulse; 101, a coupling capacitance between the fourth inverting circuit and the vertical CCD electrode.

When a low voltage is applied to the trigger input terminals V1R and V3R of the readout pulse of the vertical CCD, the voltage of the node B is VDD and the voltages of the nodes C and I are 0V. As a result, n channel MOS transistor 4
7 is turned on, and the transfer pulse of the vertical CCD is applied to the node D connected to the vertical CCD electrode. On the other hand, since 0 V or the negative power supply voltage Vss is applied to the source drain of the p-channel MOS transistor 48 which is gate-grounded, it does not conduct. Further, the drain of the p-channel MOS transistor 102 is also at 0 V and does not conduct, the source thereof is floating, and the coupling capacitance 101 does not become a load of the transfer pulse. Then
When the transfer pulse becomes 0 V, the trigger-input terminal V1
When a high voltage is applied to R and V3R, node B becomes 0V
And the n-channel MOS transistor 47 becomes non-conductive. On the other hand, the node C becomes VDD, the p-channel MOS transistor 48 is turned on, and the node D connected to the vertical CCD electrode is applied with a voltage lower than VDD by the threshold voltage of the transistor 103. Thereafter, the node I becomes 0.
From V to VDD, the p-channel MOS transistor 1
02 conducts, and this voltage change further increases the voltage of the node D via the coupling capacitor 101. As described above, according to the present embodiment, a read voltage higher than the positive power supply voltage can be realized by applying the positive power supply voltage VDD to the drive electrodes of the vertical CCDs and then boosting the voltage by capacitive coupling.

The amplitude of the read pulse is increased.
If you want to increase the coupling capacitance,
It may be provided outside.Third embodiment  Usually, the first stage driver transistor operates in saturation and the output
For the circuit to operate in the linear range, the output circuit supply voltage must be
Driver transistor threshold at first stage from reset voltage
Must be higher than the voltage subtracted value. Therefore, the output circuit power
To lower the source voltage, the threshold of the first stage driver transistor 6
Should be set to a large value. However, referring to FIG.
The next-stage driver 9 has the same structure as the first-stage driver 6.
In the case of the conventional example with
If it is too long, the next stage driver transistor will not conduct enough and the next
The operation of the stage becomes difficult. Therefore, in the present embodiment,
Driver transistor substrate impurity concentration in the first stage
Lower than the substrate impurity concentration of the transistor
Lower the threshold voltage of the driver transistor
The next stage operates within the operating range.

FIG. 11 shows an output circuit configuration diagram of the third embodiment. In the figure, reference numerals 111 and 112 denote a driver transistor, a load transistor, and a driver transistor constituting a first source follower.
Reference numerals 13 and 114 denote driver transistors and load transistors constituting the next-stage source follower. Reference numerals 115 and 116 denote driver transistors and load transistors constituting the final-stage source follower. 117 denotes the bias voltage of the load transistor described in FIG. The generating circuit 119 is shown in FIG.
A formation region of a p-well 21 and a double p-well 22 formed on an n-type substrate 20 similar to the photoelectric conversion unit described in 1 above, 118
Is a third p-well formation region having the same depth as the p-well 21 and having a slightly higher concentration. The double p-well layer is set at a high concentration for suppressing smear. The output voltage of the first-stage source follower becomes a low voltage due to a voltage drop due to a large threshold voltage of the first-stage driver transistor 111. On the other hand, the next-stage and final-stage driver transistors 113 and 11
The threshold voltage of No. 5 is a small value close to 0 V, the voltage drop due to the threshold voltage is small, the input voltage and the output voltage of each stage are almost equal, and the operation of the next stage and the final stage does not become difficult.
According to the present embodiment, the driver transistor 11 in the next and subsequent stages
By making the substrate impurity concentration of the transistors 3 and 115 lower than the substrate impurity concentration of the first-stage driver transistor 111,
A large voltage drop due to a high threshold voltage in the first stage can be realized without lowering the operation range of the next stage and thereafter, and an output circuit with a low power supply voltage, low power consumption, and low noise can be realized.

In this embodiment, the case where the source follower has a three-stage configuration has been described for the purpose of improving the frequency characteristics of the output circuit. However, if the number of stages is two or more, the effect of the present invention can be similarly obtained. .

Although the third p-well 118 has a slightly higher concentration at the same depth as the p-well 21 in order to prevent a malfunction at the time of the electronic shutter, the third p-well 118 can be used when malfunction does not matter. May have the same structure as the p-well 21.

Further, load transistors 112 and 11
4 and 116 may be formed in a well having the same structure as 119.

The driver transistors 113 and 11
5 is formed in the isolated well, and the well is
By connecting to the output of the follower to eliminate the board effect
The threshold voltage of each transistor closer to 0V
Can beFourth embodiment  In the first embodiment, a direct current (DC)
The voltage was the positive power supply VDD. However, as explained in the conventional example
As described above, this DC voltage must be adjusted for each element.
You. Therefore, in this embodiment, the voltage was boosted from VDD.
A DC voltage applied to the substrate is generated from the voltage by stepping down,
This step-down device is provided with a means for adjusting the voltage.
You.

The fourth embodiment of the present invention will be described with reference to FIGS.
This will be described below. FIG. 12 is an overall configuration diagram of the fourth embodiment,
FIG. 13 shows a substrate voltage generating circuit according to the fourth embodiment. FIG.
In FIG. 2, 1 to 10 and 12 to 17 are the same as those in FIG. Reference numeral 121 denotes the substrate voltage generation circuit shown in FIG. Also, V1, V2, V3, V4, V1R, V3R, H1,
H2, RG, SUB, WELL, VDD, Vss, OU
T is the same as in FIG. A trigger pulse of the timing generator, a pulse having a predetermined voltage from two power supplies, positive and negative, and a DC voltage are generated inside the device, and the same operation as described in FIG. 17 is performed.

In FIG. 13, reference numerals 91 to 99 denote 1 as in FIG.
39 is a DC booster circuit similar to that of FIG. 7, 131 to 134 are n-channel MOS transistors for generating a bias voltage, and 135 is a fuse for adjusting the bias voltage.
And 137, an n-channel depletion MOS transistor similar to that constituting a CCD for generating a DC substrate voltage by lowering the boosted voltage in accordance with the bias voltage, and 138, a load for flowing a slight bias current to the transistor 137. The transistor 136 supplies a bias voltage to the load transistor 138 and is a circuit similar to that of FIG.

The output voltage of the booster circuit 139 is 131 to 1
34 from the bias voltage generated by N.34.
Threshold MOS transistor 137
The voltage drops to a voltage higher by the pair value, and becomes a substrate DC voltage. load
The bias current supplied from 138 is a high voltage applied to the substrate.
It prevents malfunctions when they occur. In addition, the voltage drop
Perform with n-channel depletion MOS transistor
As a result, a bias voltage lower than the power supply voltage VDD is given.
Can also generate a substrate voltage higher than VDD
I have. The switch 98 transmits a voltage higher than VDD.
To connect the well to the output of the substrate voltage generation circuit.
Threshold voltage rise due to the plate effect is prevented. Other than this circuit
Are the same as those in FIG. Adjustment of substrate voltage is necessary
By cutting the fuse 135.
You. By disconnecting the fuse, the voltage at node J will rise.
And the substrate voltage increases. According to the present embodiment, VDD
DC voltage applied to the board from the boosted voltage
Generate and add means to adjust the voltage to this buck
This makes it possible to adjust the substrate voltage inside the device,
The usability of the imaging device is improved.Fifth embodiment  In the first embodiment, a trigger pulse is externally applied to each terminal.
To build a camera system.
Wiring between the imming generator and the two-dimensional CCD type device must be performed.
I have to. This embodiment avoids such complexity.
Therefore, this is an example in which a timing generator is also incorporated.

FIG. 14 shows a configuration diagram of the fifth embodiment. In the figure, 1 to 17 are the same as in FIG. 1, and 141 is a step-down circuit for generating the power of the timing generator 142 from an external positive power supply VDD. A timing pulse of each pulse is generated from an external basic clock by the timing generator 142, and a pulse of a predetermined voltage level and a DC voltage are generated from this pulse and a positive or negative power supply as in FIG. Is performed. According to the present embodiment, it is possible to provide a two-dimensional CCD type solid-state imaging device which can be driven by a single external pulse, two positive and negative power supplies and an earth, and is easy to use.

In the above embodiment, the inter-line CCD is used.
Although the example of the type imaging device has been described, the present invention is not limited to the specific configuration of the CCD type imaging device, and may be a frame inter-line type,
C such as frame transfer type, charge sweep type, etc.
The same can be applied to a CD-type image sensor.

The present invention also relates to a vertical CCD and a horizontal CCD.
Regardless of the specific configuration of the CD, for example, a CCD type image pickup device in which two horizontal CCDs are provided in parallel has the same effect.

As a result, Table 2 was obtained for the first embodiment.
Driving is performed under the driving conditions shown by, and is used in the camera system by the configuration shown in FIG. In the fifth embodiment, driving is performed under the driving conditions shown in Table 3, and FIG.
Is used in the camera system. In each case, it can be seen that the types of power supply voltages are much smaller than those shown in Table 1 of the related art.

[0080]

[Table 2]

[0081]

[Table 3]

According to the present invention, a CCD type image pickup device is provided.
An external driver is not required, the number of power supplies supplied by the external DC-DC converter is reduced, and the usability is improved because there is no need to adjust the DC voltage applied to the substrate when creating a camera system. Furthermore, the number of power supplies supplied from the DC-DC converter is reduced, and even if the power supply voltage of the timing generator is reduced, it is not necessary to provide a driver for driving the horizontal CCD outside the element even outside the element. Electricity can be achieved. Further, since the reset voltage of the output circuit can be reduced, and the power supply voltage of the output circuit can be lowered from the reset voltage, power consumption and noise of the output circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of a first embodiment of the present invention.

FIG. 2 is a diagram showing a portion corresponding to AA ′ and BB ′ in FIG. 1 and a cross-sectional structure of a p-channel MOS transistor.

FIG. 3 is a circuit diagram showing a vertical CCD transfer pulse generation circuit of FIG. 1;

FIG. 4 is a circuit diagram showing a vertical CCD ternary pulse generating circuit of FIG. 1;

FIG. 5 is a circuit diagram showing a horizontal CCD transfer pulse generation circuit of FIG. 1;

FIG. 6 is a circuit diagram showing a reset pulse generation circuit of FIG. 1;

FIG. 7 is a circuit diagram showing a reset voltage generation circuit of FIG. 1;

FIG. 8 is a circuit diagram showing a bias voltage generating circuit of the output circuit load transistor of FIG. 1;

FIG. 9 is a circuit diagram showing a substrate voltage generation circuit of FIG. 1;

FIG. 10 is a circuit diagram showing a vertical CCD ternary pulse generating circuit according to a second embodiment of the present invention.

FIG. 11 is a diagram illustrating an output circuit configuration according to a third embodiment of the present invention.

FIG. 12 is a diagram showing an overall configuration of a fourth embodiment of the present invention.

FIG. 13 is a diagram illustrating the substrate voltage generation circuit of FIG. 12;

FIG. 14 is a diagram showing an overall configuration of a fifth embodiment of the present invention.

FIG. 15 is a diagram showing an overall configuration of a conventional CCD solid-state imaging device.

FIG. 1 is a diagram showing driving conditions of a conventional CCD solid-state imaging device.

FIG. 16 is a block diagram of a conventional CCD camera.

FIG. 2 is a diagram showing driving conditions of the CCD solid-state imaging device according to the first embodiment.

FIG. 17 shows a CC of the CCD solid-state imaging device according to the first embodiment;
It is a D camera block diagram.

FIG. 3 is a diagram showing driving conditions of a CCD solid-state imaging device according to a fifth embodiment.

FIG. 18 shows a CC of a CCD solid-state imaging device according to a fifth embodiment;
It is a D camera block diagram.

[Explanation of symbols]

1. Photo diode, 2. Vertical CCD, 3.
... horizontal CCD, 4 ... output gate, 5 ... reset gate, 6, 111 ... first stage source follower driver transistor, 8, 112 ... first stage source follower load transistor, 9, 113 ... next stage source follower -Driver transistors, 10, 114 ... next stage source follower load transistors, 11, 121 ... substrate voltage generation circuit, 12 ... vertical CCD transfer pulse generation circuit, 13 ...
Vertical CCD tri-level pulse generation circuit, 14: horizontal transfer pulse generation circuit, 15: reset pulse generation circuit, 16
... Reset voltage generation circuit, 17 ... Load gate bias generation circuit, 20 ... N-type substrate, 21 ... P-type well,
22: p-type double well, 23: vertical CCD n layer, 2
4 ... polysilicon electrode, 25 ... n-well, 26 ...
Photo diode n layer, 27... Surface p + layer, 28
... second layer aluminum for light shielding, 29 ... first layer aluminum for wiring, 3
0 ... n-type diffusion layer, 31, 41, 51, 71, 91, 9
7, 101: coupling capacity, 32, 42, 52, 92: clamp diode, 33, 43, 37, 53, 63, 93
... First inverting circuit n-channel transistor, 34, 44,
38, 54, 64, 94... First inverting circuit p-channel transistor, 35, 45, 39, 55, 65, 95.
Inverting circuit n-channel transistor, 36, 46, 40,
56, 66, 96: second inverting circuit p-channel transistor, 47: n-channel transistor switch, 48, 1
02: p-channel transistor switch, 57: p-channel transistor voltage limiter, 58, 59: p-channel transistor for voltage limit, 60, 61, 62, 8
1, 82, 83, 131, 132, 133, 134... Bias voltage generating circuit n-channel transistors, 72, 7
3, 103 ... booster circuit n-channel transistor, 98 ...
N-channel depletion transistor switch, 9
9: substrate capacitance; 104: third inversion circuit n-channel transistor; 105: third inversion circuit p-channel transistor; 106: fourth inversion circuit n-channel transistor;
07... Fourth inversion circuit p-channel transistor, 115.
Final source follower driver transistor, 116 ...
Final source follower load transistor 117, 13
6 Bias voltage generation circuit 118 118 Third p-well 119 119 Formation region of p-well 21 and p-type double well 22 135 Fuse 137 N-channel depletion transistor voltage limiter 138 Load n-channel transistor , 139 ... step-up circuit, 14
1. Step-down circuit, 142 ... Timing generation circuit, V1, V2, V3, V4 ... Vertical CCD transfer trigger
Pulse input terminal, V1R, V3R: vertical CCD read trigger-pulse input terminal, H1, H2: horizontal CCD transfer trigger-pulse input terminal, RG: reset trigger-pulse input terminal, SUB: electronic shutter trigger-pulse input terminal, VDD ... Positive power supply input terminal, Vss ... Negative power supply input terminal, OUT ... Signal output terminal, WELL ... Well voltage input terminal, 161,171,181 ... CCD imaging device, 162 ... Timing generator, 163 ... Driver, 164 ... Correlation Double sampling circuit, 165 automatic gain control circuit, 166 A / D converter, 167 digital signal processing circuit, 168 D / A converter, 169 D
C-DC converter, 170: camera battery.

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[Procedure amendment]

[Submission date] July 12, 2000 (2007.1.
2)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

[Title of the Invention] CCD type solid-state imaging device

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD type image pickup device, and more particularly to a two-dimensional CCD type image pickup device which can be easily driven with low power consumption, has low power consumption, and has a low noise output circuit.

[0002]

2. Description of the Related Art Conventionally, a CCD type solid-state imaging device has been widely used as a solid-state imaging device used in a home video camera or the like. Such a conventional CCD type solid-state imaging device has an element configuration called an interline type shown in FIG. 15, is driven under the driving conditions shown in Table 1, and is used in a camera system with the configuration shown in FIG. In FIG. 15, reference numeral 1 denotes a photodiode for performing photoelectric conversion, 2 and 3 denote vertical CCDs 2 and horizontal CCDs 3 and 4 for transferring signal charges photoelectrically converted by the photodiode 1, and 4 denotes a horizontal CCD.
An output gate 5 for separating the CD 3 from an output circuit composed of transistors 5 to 10 is provided with a floating diffusion layer connected to the gate of a first-stage source follower driver transistor 6 to which signal charges are sent from the horizontal CCD 3. Reset transistors 6 and 8 are a driver transistor and a load transistor constituting a first-stage source follower, respectively, and 9 and 10 are a driver transistor and a load transistor constituting a next-stage source follower, respectively. A partition in the vertical CCD 2 indicates one transfer stage composed of one polysilicon electrode, and a partition in the horizontal CCD 3 indicates one transfer stage composed of a first polysilicon layer and a second polysilicon electrode. In addition, boron ions are implanted below the second-layer polysilicon electrodes forming the horizontal CCD 3 and the output gate 4 in order to lower the channel voltage. The reset transistor 5 is a horizontal CCD.
3 comprises a depletion-type field-effect transistor formed in the same step as the portion including the n-channel under the first-layer polysilicon electrode. v1, v2, v3, v4
Is a four-phase pulse input terminal for driving the vertical CCD 2, and h 1 and h 2 are 2 terminals for driving the horizontal CCD 3
Phase pulse input terminal, og is a DC bias voltage input terminal of the output gate 4, rg is a reset pulse input terminal applied to the gate of the reset transistor 5, rd is a reset voltage input terminal of the floating diffusion layer, and vg is vg. Gate voltage input terminals of load transistors 8 and 10,
od is a power supply voltage input terminal of the output circuit unit, sub is a substrate voltage input terminal, well is a well voltage input terminal, vss is a well voltage input terminal of a protection circuit normally used in an integrated circuit, and out is a signal output terminal. .

The signal charge photoelectrically converted by the photodiode 1 is applied with a high voltage to the terminal v1 or v3, and the signal charge for one row is sent to the vertical CCD 2 collectively.
1 to 4 having medium and low voltage levels at terminals v4
Phase pulse is applied, and this causes a horizontal CC
D2, and then a two-phase horizontal CCD transfer pulse is applied to the h1 and h2 terminals to sequentially transfer the horizontal CCD3. A potential change due to a signal charge transferred from the horizontal CCD 3 to the floating diffusion layer connected to the gate of the first-stage source follower driver transistor 6 is detected by the first-stage source follower including the transistors 6 and 8, and the next stage including the transistors 9 and 10 is detected. The signal is output to the out terminal by the source follower. Next, a reset pulse is applied to the rg terminal, the reset transistor 5 is turned on, and the floating diffusion layer is reset to the reset voltage applied to the rd terminal. The above operation is repeated, and signals are sequentially output. In addition, a predetermined DC voltage is normally applied to the sub terminal to discharge excess charge generated by the photodiode, and a high voltage is applied during scanning to realize an electronic shutter for improving dynamic resolution and preventing flicker. Is done. The CCD type solid-state imaging device having such a configuration and operation is generally driven under the driving conditions shown in Table 1. Table 1 shows an example of a pulse applied to each terminal shown in FIG. 15 and a DC bias voltage.

[0004]

[Table 1] Using the well electrode terminal voltage as a reference voltage, the negative voltage at the terminals v1 to v4 is set to a voltage lower than the voltage at which the p-type inversion layer is formed on the surface of the n-layer of the vertical CCD 2 (hereinafter, pinning voltage) to reduce dark current. A vertical CCD scanning pulse is applied, and a high voltage is applied to the v1 and v3 terminals when transferring signal charges from the photodiode 1 to the vertical CCD2. The h1 and h2 terminals are connected to the timing generator 16 of FIG.
2 is applied directly without the driver 163. This is to prevent unnecessary power consumption due to the provision of the driver, and to reduce the power consumption of the camera system. Further, in order to transfer charges from the horizontal CCD to the floating diffusion layer without interruption, a voltage equal to the high voltage of the horizontal CCD transfer pulse applied to the h1 and h2 terminals is applied to the og terminal, and an output gate is applied to the rd terminal. A voltage sufficiently higher than the channel voltage 4 below is applied. The low voltage of the rg terminal is equal to the low voltage of the horizontal CCD transfer pulse in order to prevent the leakage of signal charges from the floating diffusion layer, and the high voltage is the horizontal C in order to realize a sufficiently low on-resistance.
A voltage sufficiently higher than the high voltage of the CD transfer pulse is applied. Further, the same voltage as that of the rd terminal is applied to the od terminal in order not to increase the number of types of power supply voltages. On the other hand, su
Since the DC voltage for discharging the excess charge applied to the terminal b varies from element to element, the DC voltage is adjusted for each element, and the high voltage for the electronic shutter pulse is set to the upper limit of the variation of the elements.

The above-mentioned CCD solid-state image pickup device is used in a camera with the configuration shown in FIG. In the drawing, reference numeral 161 denotes a CCD solid-state imaging device shown in FIG. 15; 162, a timing generator for driving the CCD solid-state imaging device 161; 163, a voltage value of each pulse for supplying a required value. , 164 is a correlated double sampling circuit for removing noise from the output of the CCD solid-state imaging device 161, 165 is an automatic gain control circuit that changes a voltage gain according to a signal output level, and 166 is an A / D converter vessel,
167 is a digital signal processing circuit, 168 is a D / A converter, and 169 is a DC-DC converter that supplies necessary voltages from the camera battery 170 to each part of the camera. The timing generator 162 and the correlated double sampling circuit 1
64, automatic gain control circuit 165, digital signal processor 167, A / D converter 166, D / A converter 168
Consists of integrated circuits formed on a single chip, each operating on a single power supply. CCD type solid-state imaging device 161
Generates the timing by the timing generator 162 and
-Driver 1 supplied with voltage by DC converter 169
63 is driven by a pulse having a predetermined voltage value and a DC voltage supplied from the DC-DC converter 169,
The output signal from the solid-state imaging device 161 is subjected to noise removal and gain control by a correlated double sampling circuit 164 and an automatic gain control circuit 165, and then converted to a digital signal by an A / D converter 166, and converted by a digital signal processing device 167 to a signal. The processing is executed, and is again converted into an analog signal by the D / A converter 168 to become a TV signal. In addition, this type of CCD solid-state imaging device is described in, for example, Technical Report of the Institute of Television Engineers of Japan, Vol. 61-72
(1989.2), Technical Report of the Institute of Television Engineers of Japan, 12
Vol. 13, No. 13 pp. 31-36 (1988. 2). Further, a digital signal processor for a camera using a CCD type solid-state image pickup device of this type is described in page 250 of the ISSS Digest of Technical Papers. Page 251 (19
91) (ISSCCDIGEST OF TECHNI)
CAL PAPERS pp. 250-251 (198
7)).

[0006]

The above prior art is based on CC
Driving of the D-type solid-state imaging device does not consider usability improvement and low power consumption, and the imaging device is inconvenient.
It is difficult to reduce the power consumption of the camera. Further, there is a problem that it is difficult to reduce power consumption and noise of an output circuit in the image sensor. That is, first, as the peripheral circuits become more single-powered, the driving of the CCD type image pickup device shown in FIG. 15 requires a pulse having a multi-level voltage level shown in Table 1 and a DC voltage. As shown in FIG. 16, a driver 163 and a DC-DC converter 169 for generating these multi-valued voltages must be provided in the camera system. That is, a trigger pulse for generating a read pulse or a transfer pulse of the CCD is input to the driver 163, and various multivalued pulses obtained as an output of the driver 163 are applied to each terminal of the image sensor. This has made the CCD type image sensor difficult to handle. In addition, as the digitalization of signal processing circuits has made camera adjustment unnecessary, the DC voltage for discharging excess charge applied to the sub terminal must be adjusted for each element. It was another factor that made it difficult.

Second, in order to reduce the power consumption of the camera, the power supply voltage of the timing generator 162 and the signal processing device 167 is changed from the current 5 V to 3.3 V, and further 1.5 V.
And lower voltage. However, it is difficult to lower the drive voltage of the horizontal CCD 3 that requires high-speed transfer. Therefore, it is difficult to drive the horizontal CCD 3 by applying the output voltage of the timing generator 162 to the terminals h1 and h2, and it is necessary to provide a driver for driving the horizontal CCD in the camera system. When the driver section is provided outside the image sensor in this manner, reactive power for driving a parasitic capacitance such as a wiring capacitance between the driver and the image sensor or a pin capacitance of the image sensor is generated, which is one of the factors that hinders low power consumption of the camera. It was. Further, the power of the DC-DC converter 169 for generating the above-described various pulses having different voltage values cannot be reduced, which is another factor that prevents the power consumption of the camera from being reduced. Third, the output voltages of 0 to 5 V of the timing generator 162 are defined as h1 and h2.
Since the voltage is applied to the terminal to drive the horizontal CCD 3, the channel voltage of the horizontal CCD 3 is high and the rd terminal voltage is high. As a result, the od terminal voltage, which is the power supply voltage of the output circuit set to the same voltage as the rd terminal, also increases, and the power consumption generated in the output circuit increases. further,
Since the power supply voltage is high, it is difficult to use a transistor with a short channel length, and there has been a problem that noise is large. In view of the above-mentioned various problems in the prior art, the present invention solves the first problem and aims to provide a CCD solid-state imaging device that is easy to drive and easy to use.

[0008]

In order to achieve the above-mentioned object of the present invention, in the present invention, a photoelectric conversion element group for converting light into an electric signal, and an optical signal charge generated in the photoelectric conversion element group are provided. , And a CCD type solid-state imaging device having an output circuit for detecting and amplifying optical signal charges arriving from the photoelectric conversion element group.
A positive power supply having a value equal to the power supply value of the output circuit is used as a power supply, and a trigger pulse is input. The configuration includes a read pulse generation circuit that outputs a read pulse of a voltage value.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. As shown in Table 1, the vertical C
Three types of voltage levels are required for a four-phase pulse for driving a CD, and a ternary pulse generation circuit is required for this. These three voltage levels, that is, the ground potential (Table 1)
Positive potential (15 V in Table 1) with respect to 0 V at
FIG. 2 shows a circuit for generating three-valued pulses of a negative potential (−9 V in Table 1) and a negative potential. This circuit has a positive power supply voltage value equal to the power supply value of an output circuit for detecting and amplifying an optical signal charge (a circuit portion composed of transistors 5 to 10 in FIG. 15), and a read pulse for outputting a read pulse. The generation circuit is a positive power supply VD
It is provided between D and a ground power supply. For this reason, in the circuit of FIG. 2, when this positive side power supply voltage value is reduced for power saving, the voltage applied to the drive electrodes of the vertical CCDs is the same as the high voltage value shown in Table 1 as it is. descend.

In order to solve this problem, as shown in FIG. 1, a read pulse generating circuit having a power supply having a voltage value equal to the positive power supply of the above-described output circuit is provided, and a two-stage subordinate circuit having a trigger pulse as an input is provided. An output pulse voltage obtained through a first pulse generation circuit using the connected complementary MOS transistors 37 and 38 and a second pulse generation circuit using the complementary MOS transistors 39 and 40, and the output pulse is input to the The complementary MOS transistors 104, 105 and 106, which are also cascaded in two stages,
07 and the pulse voltage synchronized with the trigger pulse obtained by using the boosting capacitor 101, the output voltage of the inverting circuit composed of the inverting circuit 07 and the voltage of the positive power supply and the vertical CCD are stabilized. A read pulse generating circuit that outputs a read pulse having a voltage value sufficient for operation is configured. As described above, in the present embodiment, the positive power supply voltage VDD is
Then, a voltage higher than the positive power supply voltage is realized by further increasing the voltage by capacitive coupling after application to the drive electrodes. Details of a specific configuration of the above circuit will be described below. That is, in FIG. 1, the capacitor 41, the diode 42, the output pulse on the negative potential side (Vss), the vertical C
Complementary MOS transistor 4 forming two sets of inverting circuits connected in series to generate a CD transfer pulse
3-46, output pulse on the other positive potential side, vertical CC
2 connected in series to form a D read pulse
Complementary MOS transistors 37 to 40 forming a set of inverting circuits, a transistor 47 for connecting these two sets of both complementary MOS transistors and performing transfer / read switching, and outputting a positive potential side output pulse. The transistors 48 are all the same as those shown in FIG. In FIG. 1, if a circuit constituted by transistors 37 and 38 is a first inverting circuit and a circuit constituted by transistors 39 and 40 is a second inverting circuit,
Is constituted by a complementary transistor of an n-channel MOS transistor 104 and a p-channel MOS transistor 105, and the fourth inverting circuit is an n-channel MOS transistor 106 and a p-channel MOS transistor
The transistor 107 is constituted by a complementary transistor. The n-channel MOS transistor 103 is diode-connected for boosting, and
The S transistor 102 is for transmitting a boosting pulse and is grounded at the gate. The capacitor 101 has a function of boosting by a coupling capacitance between the fourth inverting circuit and the vertical CCD electrode.

When a low voltage is applied to the trigger input terminals V1R and V3R of the read pulse of the vertical CCD, the voltage of the node B is VDD, and the voltages of the nodes C and I are 0V. As a result, the n-channel MOS transistor 47 conducts, and the transfer pulse of the vertical CCD is applied to the node D connected to the vertical CCD electrode. on the other hand,
Since 0 V or the negative power supply voltage Vss is applied to the source and drain of the gate-grounded p-channel MOS transistor 48, it does not conduct. Further, the drain of the p-channel MOS transistor 102 is also at 0 V and does not conduct, the source thereof becomes floating, and the coupling capacitance 101 does not become a load of the transfer pulse. Next, when a high voltage is applied to the trigger input terminals V1R and V3R in a state where the transfer pulse is 0 V, the node B becomes 0 V and the n-channel MOS transistor 47 is turned off. On the other hand, the node C becomes VDD, the p-channel MOS transistor 48 is turned on, and a voltage lower than VDD by the threshold voltage of the transistor 103 is applied to the node D connected to the vertical CCD electrode. After this,
The node I changes from 0 V to VDD, the p-channel MOS transistor 102 conducts, and the voltage change causes the coupling capacitor 101 to be charged, thereby further increasing the voltage at the node D.
As described above, according to the present invention, after the positive power supply voltage VDD is applied to the drive electrodes of the vertical CCDs, the voltage is further increased by capacitive coupling, thereby having a read voltage equal to or higher than the positive power supply voltage and being synchronized with the trigger pulse. Can be realized in the image sensor.

As a result, the functions of the driver 163 and the DC-DC converter 169 in the conventional camera system shown in FIG. 16 can be provided to the CCD solid-state imaging device, and the driver 163 and the DC-DC converter in the camera system can be provided.
A DC converter is not required, and an easy-to-use and easy-to-use CCD solid-state imaging device can be realized. In addition,
Capacitor 1 to increase the read pulse amplitude
When it is desired to increase the capacitance of the capacitor 01, the capacitor 101 may be provided outside the element. The terminals V1 / V3 are input terminals for a trigger pulse for generating a transfer pulse for the vertical CCD. The transfer pulse takes a negative value. Therefore, this transfer pulse generation circuit is provided between the negative power supply and the ground power supply, and the voltage between the terminals of the MOS transistors 43 to 46 constituting the transfer pulse generation circuit is It is lower than the negative power supply voltage Vss. Hereinafter, various embodiments related to the present invention will be described. First Embodiment A first embodiment of the present invention will be described with reference to FIGS. FIG. 3 is an overall configuration diagram of the first embodiment, and FIG.
4A is a cross-sectional view taken along the line AA ′ in FIG. 3 of the first embodiment, FIG. 4B is a cross-sectional view taken along the line BB ′ in FIG.
FIG. 5C is a cross-sectional view of a portion corresponding to a p-channel transistor. FIG. 5 is a vertical CCD transfer pulse generation circuit according to the first embodiment. FIG. 2 is a vertical CCD ternary pulse generation circuit according to the first embodiment. 6 is a horizontal CCD transfer pulse generation circuit of the first embodiment, FIG. 7 is a reset pulse generation circuit of the first embodiment, FIG. 8 is a reset drain voltage generation circuit of the first embodiment, and FIG. FIG. 10 shows a bias voltage generation circuit for the output circuit load transistor according to the first embodiment, and FIG. 10 shows a substrate voltage generation circuit according to the first embodiment.

In FIG. 3, 1 to 10 are the same as in FIG. However, the reset transistor 5 is a depletion type transistor in which the same ion implantation is performed as under the second layer polysilicon electrode constituting the horizontal CCD.
11 is a substrate voltage generation circuit shown in FIG. 10, 12 is a vertical CCD transfer pulse generation circuit shown in FIG. 5, 13 is a vertical CCD ternary pulse generation circuit shown in FIG. 2, and 14 is a horizontal CCD shown in FIG.
A CD transfer pulse generating circuit, 15 is a reset pulse generating circuit shown in FIG. 7, 16 is a reset voltage generating circuit shown in FIG. 8, and 17 is a bias voltage generating circuit of an output circuit load transistor shown in FIG. V1, V2, V3, V4 are transfer pulse trigger input terminals of the vertical CCD 2, V1R, V
3R is a trigger input terminal of a read pulse of the vertical CCD 2, H1 and H2 are trigger input terminals of a transfer pulse of the horizontal CCD 3, RG is a trigger input terminal of a reset pulse,
SUB is an electronic shutter pulse trigger input terminal, WE
LL is a well voltage input terminal, VDD is a positive power supply voltage input terminal, Vss is a negative power supply voltage input terminal, and OUT is a signal output terminal. A trigger pulse of the timing generator, a pulse having a predetermined voltage from two power supplies, positive and negative, and a DC voltage are generated inside the device, and the same operation as described in FIG. 15 is performed.

Usually, a booster circuit used in an integrated circuit has a low current driving capability. Therefore, the positive power supply needs to be higher than the maximum voltage that requires a large current driving capability, and the negative power supply needs to be lower than the minimum voltage that requires a large current driving capability. In the case of a two-dimensional CCD image sensor, a large current driving capability is required for the high and low voltages of the transfer pulses of the vertical CCD 2 and the horizontal CCD 3 and the power supply voltage of the output circuit. As a result, the positive power supply voltage value may be higher than the power supply voltage value of the output circuit. In the present embodiment, the positive power supply value is set equal to the power supply voltage value of the output circuit in order to prevent unnecessary power consumption since a through current always flows through the power supply of the output circuit. The negative power supply value may be lower than the lowest voltage value of the transfer pulse of the vertical CCD. In this embodiment, the negative power supply value is set equal to the lowest voltage value of the transfer pulse of the vertical CCD 2 so that an unnecessary step-down device may not be provided. That is, in the present embodiment, the positive power supply value is equal to the power supply voltage value of the output circuit, and the negative power supply value is equal to the lowest voltage value of the transfer pulse of the vertical CCD 2, whereby the trigger pulse of the timing generator is positive and negative. It is possible to easily generate a pulse having a predetermined voltage and a DC voltage from the two power sources inside the element.

In order to reduce the power consumption of the built-in circuits 11 to 17, it is desirable to configure the circuit with complementary MOS transistors. In this embodiment, such a complementary transistor is realized without any change in a manufacturing process for forming a CCD type image pickup device. This will be described with reference to FIG. FIG. 3A is a cross-sectional view of a portion corresponding to the line AA ′ in FIG. In the figure, 20 is an n-type substrate, 21 is a p-type well, 22 is a p-type double well for preventing unnecessary charges such as smear charges from being mixed into the CCD n-layer 23, 24 is a polysilicon electrode of the CCD, and 25 is a polysilicon electrode. An n-well for discharging excess charge from the photodiode n-layer 26 to the substrate at a low voltage;
27 is a p + layer provided on the photodiode surface for suppressing dark current, and 28 is a second layer aluminum for light shielding. FIG. 4B is a cross-sectional view of the n-channel transistor taken along the line BB 'in FIG. In the figure, 20,
Reference numerals 21, 22, and 24 are the same as those in FIG. 4A. Reference numeral 29 denotes a first layer aluminum for wiring, and reference numeral 30 denotes an n-type source / drain diffusion layer of an n-channel MOS transistor. 11 to 17
The n-channel MOS transistor for realizing the built-in circuit has a structure similar to that shown in FIG. FIG. 3C is a cross-sectional view of a newly provided p-channel MOS transistor for realizing 11 to 17 built-in circuits. 20, 2
4, 25 and 27 are the same as in FIG.
Same as (b). The contact between the p + layer 27 and the wiring layer 29 is performed simultaneously with the contact between the p-type well 21 and the wiring layer 29 in the conventional example. In the present embodiment, by using the source and drain diffusion layers of the p-channel transistor also as the p + layer provided on the photodiode surface, the complementary type without changing the manufacturing process for forming the CCD type image pickup device. Transistor is realized.

If it is desired to lower the threshold voltage of the p-channel transistor, the n-type well 25 need not be provided below the p-channel transistor. Alternatively, an ion implantation of boron, typically made of boron, for adjusting a channel voltage, which is implanted below the second-layer polysilicon electrode of the horizontal CCD, may be implanted below the polysilicon electrode 24. Conversely, when it is desired to increase the threshold voltage, the photodiode n-layer 26 may be provided below the transistor. Further, when it is desired to reduce the threshold voltage of the n-channel transistor, the p-type double well 22 need not be provided below the n-channel transistor. When the p-channel transistor of the present embodiment is used, the voltage applied to the n-type substrate is higher than the positive power supply so that the source / drain diffusion layer 27 is not biased in the forward direction with respect to the n-type substrate 20. . (1) Vertical CCD transfer pulse generation circuit In order to generate a transfer pulse of a vertical CCD having a low negative voltage by a positive external trigger pulse, it is necessary to perform a level shift and amplify the voltage. FIG. 5 shows a vertical CCD transfer pulse generation circuit according to the first embodiment. In the figure, 31
Is a coupling capacitance, 32 is a clamp diode, 33 is an n-channel MOS transistor constituting a first inverting circuit, 3
4 is a p-channel MOS transistor forming a first inverting circuit, 35 is an n-channel MOS transistor forming a second inverting circuit
The OS transistor 36 is a p-type transistor forming a second inverting circuit.
It is a channel MOS transistor. The positive pulse from the outside is transmitted to the input point A clamped to the negative power supply Vss by the diode 32 through the coupling capacitor 31 with the voltage shifted. Next, after the voltage is amplified by the first inverting circuit, the current is amplified by the second inverting circuit to be a vertical CCD transfer pulse. Since the voltage amplitude of the external pulse is smaller than the voltage amplitude of the vertical CCD transfer pulse, a through current flows through the first inversion circuit when the voltage of the external pulse is high. In order to reduce this through current and reduce the power consumption, the current driving capability of the first inverting circuit must be reduced, and the large capacity vertical CC is required.
D electrode cannot be driven. Therefore, in the present embodiment, the second
Is provided so that the first inverting circuit need not have a high current driving capability. That is, according to the present embodiment, the level shift and the voltage amplification are performed by providing the first inverting circuit in which the input point is coupled to the external pulse by the capacitance and is clamped by the negative power supply, thereby performing the first inversion. By providing a second inversion circuit that receives the output of the circuit as an input, a low power consumption vertical CCD transfer pulse generator is realized. The diode 32 is a p-type well 2 shown in FIG.
It can be easily realized by providing an n-type diffusion layer in 1. Further, the clamping may be performed by a diode-connected MOS transistor. (2) Vertical CCD tri-level pulse generation circuit In this embodiment, a negative power supply circuit for generating a vertical CCD transfer pulse and a positive power supply circuit for generating a read pulse are provided.
By switching the outputs of these two circuits by switches, a vertical CCD ternary pulse is generated. FIG. 2 shows the first
1 shows a vertical CCD ternary pulse generating circuit according to the embodiment.
In the figure, 41 is a coupling capacitance, 42 is a clamp diode, 4
Reference numerals 3 and 37 denote n-channel MOSs constituting the first inverting circuit
Transistors, 44 and 38 are p-channel MOS transistors forming a first inverting circuit, 45 and 39 are n-channel MOS transistors forming a second inverting circuit,
6 and 40 are p-channel MOSs constituting a second inverting circuit
A circuit composed of transistors 41 to 46 or a circuit composed of 37 to 40 is a circuit similar to that of FIG. Reference numeral 47 denotes an n-channel MOS transistor serving as a switch between a vertical CCD transfer pulse generation circuit and a vertical CCD electrode, and reference numeral 48 denotes a read pulse generation circuit and a vertical CCD.
A p-channel MOS transistor serving as a switch between the electrodes. The well of the n-channel MOS transistor 47 is connected to the output of the second inverting circuit to prevent an increase in threshold voltage due to the body effect. A transfer pulse generating circuit for generating a negative value vertical transfer pulse is provided between the negative power supply and the ground power supply, and the voltage between the terminals of the MOS transistors 43 to 46 constituting the transfer pulse generating circuit is lower than Vss. A read pulse generating circuit for generating a read pulse of a positive value is provided between the positive power supply and the ground power supply, and a MOS transistor 37 constituting the read pulse generating circuit is provided.
To 40 become VDD or less.

When a low voltage is applied to the trigger input terminals V1R and V3R of the read pulse of the vertical CCD 2, the voltage at the node B is VDD and the voltage at the node C is 0V. As a result, n channel MOS transistor 47
Is conducted, and a transfer pulse of the vertical CCD 2 having a negative voltage is applied to the node D connected to the vertical CCD electrode. On the other hand, a p-channel MOS transistor 4 having a gate grounded
0V or negative power supply voltage Vss
Is not applied, so that conduction does not occur. Next, with the transfer pulse at 0 V, the trigger input terminal V1R,
When a high voltage is applied to V3R, the potential at the node B becomes 0 V, and the n-channel MOS transistor 47 is turned off. On the other hand, the node C becomes VDD, the p-channel MOS transistor 48 becomes conductive, and the node D connected to the vertical CCD electrode
Is applied. That is, the voltage of the node B becomes V
When the n-channel MOS transistor 47 is conducting, the transfer pulse from 0 to Vss is applied to the node D connected to the vertical CCD electrode, and the voltage of the node C which is the output of the read pulse generation circuit becomes 0V. I have. As a result, the source-drain voltage of the p-channel MOS transistor 48 becomes Vss at the maximum. Also,
Node C becomes VDD, p-channel MOS transistor 48 conducts, and V is applied to node D connected to the vertical CCD electrode.
When DD is applied, the output of the negative power supply circuit that generates the vertical CCD transfer pulse is 0V. As a result,
The source-drain voltage of the n-channel MOS transistor 47 becomes VDD at the maximum.

As described above, according to the present embodiment, the negative power supply circuit for generating the vertical CCD transfer pulse for the vertical CCD ternary pulse and the positive power supply circuit for generating the read pulse are provided. Is switched by a switch, so that the voltage between the source and drain of each MOS transistor is set to a value as low as VDD or Vss.
A value pulse can be generated. The MOS transistor 47 is an n-channel, and the MOS transistor 48 is a p-channel.
The following operational effects can be obtained by using a channel and setting the gate voltage when each MOS transistor is off to the ground voltage. That is, when the voltage at the node B becomes VDD and the n-channel MOS transistor 47 is conducting, a transfer pulse from 0 to Vss is applied to the node D connected to the vertical CCD electrode. At this time, the voltage of the node C which is the output of the read pulse generation circuit is 0V. As a result, by applying 0 V to the gate, p
The channel MOS transistor 48 can be turned off, and its gate-source voltage can be 0 V, and its gate-drain voltage can be at most Vss. The voltage of the node C, which is the output of the read pulse generation circuit, is VDD.
When the p-channel MOS transistor 48 is turned on, VDD is applied to the node D connected to the vertical CCD electrode. At this time, the output of the negative power supply circuit that generates the vertical CCD transfer pulse is 0V. As a result, by setting the gate voltage to 0 V, the n-channel MOS transistor 47 can be turned off, the gate-source voltage can be 0 V, and the gate-drain voltage can be VDD at the maximum. . Therefore, a ternary pulse can be generated while the gate-drain voltage and the gate-source voltage of each switch MOS transistor at the time of off are set to values as low as VDD or Vss. (3) Horizontal CCD transfer pulse generating circuit The horizontal CCD transfer pulse of this embodiment has a negative minimum voltage in order to lower the reset voltage and power supply voltage of the output circuit. Further, the minimum voltage is set to a value higher than the pinning voltage under the second-layer polysilicon electrode of the horizontal CCD in which the ion implantation is performed to reduce the channel voltage so as not to generate an invalid voltage region. As a result, horizontal C
The CD transfer pulse minimum voltage has a negative value higher than the vertical CCD transfer pulse minimum voltage. On the other hand, the voltage amplitude is usually smaller than the vertical CCD transfer pulse to reduce power consumption.
Therefore, in the present embodiment, the transfer pulse of the horizontal CCD is generated by limiting the voltage amplitude of the negative power supply circuit after level shifting the external positive trigger pulse. FIG. 6 shows a horizontal CCD transfer pulse generation circuit according to the first embodiment. In the figure, 51 is a coupling capacitance, 52 is a clamp diode, and 53 is an n-channel MO constituting a first inverting circuit.
S transistor, 54 is a p-channel MOS transistor constituting a first inverting circuit, 55 is an n-channel MOS transistor constituting a second inverting circuit, 56 is a p-channel MOS transistor constituting a second inverting circuit, and 5
The circuit composed of 1 to 56 is a circuit similar to FIG. 57 is p for limiting the negative voltage of the pulse.
Channel MOS transistors 58 and 59 are p-channel MOS transistors for applying a bias voltage to the gate of p-channel MOS transistor 57, and 60, 61 and 62 are n-channel MOS transistors constituting a bias voltage generating circuit. The wells of the n-channel MOS transistors 60, 61 and 62 are connected to their respective sources, and the threshold voltages of the transistors are equal. The negative voltage of the pulse generated by the trigger pulse applied to the H1 and H2 terminals of the trigger input is limited by the p-channel MOS transistor 57 and becomes a horizontal CCD transfer pulse. When the output of the second inverting circuit is 0 V, the node E is connected to the p-channel M from the bias voltage of the bias voltage generating circuit.
The value is higher by the threshold voltage of the OS transistor 59. When the output of the second inverting circuit becomes Vss, the voltage at the node E decreases due to capacitive coupling between the drain or source of the transistor 57 and the gate. Thereafter, when the voltage at the node E falls below a certain voltage, the transistor 58
Is conducted, and the node E is clamped to a value lower than the bias voltage of the bias voltage generating circuit by the threshold voltage of the p-channel MOS transistor 58. As a result, the output of the second inverting circuit is limited to a value higher than the node E by the threshold voltage of the p-channel MOS transistor 57, that is, a value equal to the bias voltage of the bias voltage generating circuit. According to this embodiment, the transfer pulse of the horizontal CCD can be generated by limiting the voltage amplitude of the negative power supply circuit after level-shifting the external positive trigger pulse.

In order to limit the high voltage of the pulse, the transistors 57 to 59 may be n-channel MOS transistors and a desired bias voltage may be applied. In order to limit the voltage of the pulse, a voltage limiter is applied to the power supply voltage. May be. (4) Reset pulse generation circuit In this embodiment, the DC bias voltage of the output gate is set to 0 V which is the high voltage of the horizontal CCD transfer pulse.
The reset transistor 5 is a depression type transistor similar to the one under the second-layer polysilicon electrode constituting the output gate. As a result, in order to prevent signal charges from leaking from the floating diffusion layer, the low voltage of the reset pulse may be 0 V or less. Therefore, in the present embodiment, a reset pulse is generated by a circuit that uses two power supplies of positive power and 0 V. FIG. 7 shows a reset pulse generation circuit according to the first embodiment. In the figure, 63 is an n-channel MOS transistor forming a first inverting circuit, 64 is a p-channel MOS transistor forming a first inverting circuit, and 65 is an n-channel MOS transistor forming a second inverting circuit.
The transistor 66 is a p-channel MOS transistor constituting a second inverting circuit, and the circuit composed of 63 to 66 is a circuit similar to FIG. According to the present embodiment, the reset pulse can be generated by voltage-amplifying a positive trigger pulse from the outside. (5) Reset voltage generation circuit In this embodiment, in order to reduce the power supply voltage of the output circuit, the reset voltage is generated separately from the power supply voltage of the output circuit, and the reset voltage is generated by boosting the power supply voltage of the output circuit.

FIG. 8 shows a reset voltage generating circuit according to the first embodiment. In the figure, 63 to 66 are the same as those in FIG. 7, 71 is a charge pump capacitor, and 72 and 73 are diode-connected n-channel MOS transistors.
The well of the n-channel MOS transistor 72 is connected to the power supply VDD to prevent a rise in threshold voltage due to the body effect. By the charge pump by the trigger pulse, the reset voltage is about twice the DC voltage lower than the positive power supply voltage VDD by the threshold voltage of the n-channel MOS transistor. According to the present embodiment, the reset voltage is generated from the power supply voltage of the output circuit by boosting, so that the power supply voltage of the output circuit is made lower than the reset voltage without increasing the number of power supplies supplied from outside. Can be.

When an n-channel MOS transistor having a low threshold voltage is required to obtain a high reset voltage, a transistor having the structure shown in FIG. 4B and having no double p-well may be used. (6) Load transistor bias voltage generation circuit FIG. 9 shows a load transistor bias voltage generation circuit.
In the figure, 81, 82 and 83 are n-channel MOS transistors constituting a bias voltage generating circuit. The wells of the n-channel MOS transistors 81, 82, 83 are connected to their respective sources, and the threshold voltages of the transistors are equal. The power supply voltage is divided into １ ／ by a diode-connected transistor and becomes a bias voltage of a load. It is needless to say that the bias voltage can be freely set as required. (7) Substrate Voltage Generating Circuit It is necessary to apply a DC voltage for discharging excessive voltage to the n-type substrate 20 at all times, and to apply a high positive voltage during the operation of the electronic shutter. In this embodiment, a pulse obtained by amplifying this high voltage from an external trigger pulse is applied to the substrate by capacitive coupling to generate the pulse. FIG. 10 shows a substrate voltage generating circuit according to the first embodiment. In the figure, 91 is a coupling capacity,
92 is a clamp diode, 93 is an n-channel MOS transistor constituting a first inverting circuit, 94 is a p-channel MOS transistor constituting a first inverting circuit, 95
Is an n-channel MOS transistor forming a second inverting circuit, and 96 is a p-channel MOS transistor forming a second inverting circuit.
A circuit composed of S transistors and composed of 91 to 96 is a circuit similar to FIG. Reference numeral 97 denotes a coupling capacitance between the second inverting circuit and the substrate, 99 denotes a substrate capacitance, and 98 denotes a switch between the DC voltage VDD applied to the substrate and the substrate. The switch 98 is composed of an n-channel depletion MOS transistor similar to that constituting a CCD.
When the voltage applied to the SUB terminal is low, the voltage of the node F becomes VDD, the switch 98 is turned on, and the substrate voltage becomes VDD. On the other hand, node G is at Vss.
When the voltage applied to the SUB terminal increases, first, the node F becomes Vss, and the switch 98 closes. Thereafter, the node G changes from Vss to VDD, and the substrate voltage becomes (VDD).
−Vss) is increased by a value obtained by dividing the voltage by the capacitance 97 and the substrate capacitance 99. In this embodiment mode, a high voltage can be applied to the substrate at high speed by boosting by capacitive coupling as described above. Further, by using an n-channel depletion MOS transistor constituting a CCD as a switch, VDD can be applied to the substrate without voltage drop and boosting is possible.

When it is desired to increase the coupling capacitance in order to increase the amplitude of the shutter pulse, the coupling capacitance may be provided outside the element. When it is not necessary to increase the amplitude of the shutter pulse, the low-voltage side power supply Vss is set to 0.
V may be used. Further, when a high voltage applied between the gate and the drain becomes a problem when the switch 98 is turned off, a voltage limiter similar to that described with reference to FIG. Thus, the low voltage applied to the gate of the switch 98 can be set to the minimum voltage at which the switch is turned off when the source voltage is VDD, and the gate-drain voltage can be reduced.

According to the above-described embodiment, the two-dimensional C pulse which can be driven by a single-level external pulse and two positive and negative power supplies, is easy to use, and can reduce the power consumption of the camera.
A CD solid-state imaging device can be provided. In addition, a power supply voltage of the output circuit can be reduced by incorporating a circuit for generating a negative horizontal CCD drive pulse from an external pulse and a booster circuit for generating a reset voltage from the power supply voltage of the output circuit, thereby reducing power consumption and noise. Output circuit can be realized. Second Embodiment In the vertical CCD ternary pulse generating circuit according to the first embodiment, the voltage of the read pulse is VDD and the voltage value may be insufficient. In this embodiment, the positive power supply voltage VDD is
A read voltage higher than the positive power supply voltage is realized by boosting by capacitive coupling after application to the drive electrode of the CD. FIG. 1 shows a vertical CCD ternary pulse generating circuit according to a second embodiment. In the figure, 41 to 47, 48, 3
7 to 40 are the same as in FIG. 104 is an n-channel MOS transistor forming a third inverting circuit, 105 is a p-channel MOS transistor forming a third inverting circuit, and 106 is an n-channel MOS forming a fourth inverting circuit.
The S transistor 107 is a p-type transistor forming a fourth inversion circuit.
A channel MOS transistor 103 is a diode-connected n-channel MOS transistor for boosting,
2 is a grounded p-channel MOS transistor for transmitting a boost pulse, and 101 is a coupling capacitance between the fourth inversion circuit and the vertical CCD electrode.

When a low voltage is applied to the trigger input terminals V1R and V3R of the vertical CCD read pulse, the voltage at the node B is VDD, and the voltage at the nodes C and I is 0V. As a result, n channel MOS transistor 47
Is conducted, and the transfer pulse of the vertical CCD is applied to the node D connected to the vertical CCD electrode. On the other hand, since 0 V or the negative power supply voltage Vss is applied to the source / drain of the p-channel MOS transistor 48 whose gate is grounded, it does not conduct. Further, the drain of the p-channel MOS transistor 102 is also 0 V and does not conduct, the source thereof is floating, and the coupling capacitor 101 for boosting does not become a load of the transfer pulse. Next, when a high voltage is applied to the trigger input terminals V1R and V3R in a state where the transfer pulse is 0 V, the node B
Becomes 0 V, and the n-channel MOS transistor 47 is turned off. On the other hand, node C becomes VDD and p channel M
A voltage lower than VDD by the threshold voltage of the transistor 103 is applied to the node D connected to the vertical CCD electrode when the OS transistor 48 is turned on. Thereafter, the node I changes from 0 V to VDD, the p-channel MOS transistor 102 conducts, and this voltage change causes the coupling capacitance 10
The voltage of the node D further rises through the node 1. As described above, according to the present embodiment, a read voltage higher than the positive power supply voltage can be realized by applying the positive power supply voltage VDD to the drive electrodes of the vertical CCDs and then boosting the voltage by capacitive coupling. When it is desired to increase the coupling capacitance in order to increase the amplitude of the read pulse, the coupling capacitance may be provided outside the element. Third Embodiment In general, in order for the first stage driver transistor to perform a saturation operation and the output circuit to operate in a linear range, the output circuit power supply voltage needs to be higher than a value obtained by subtracting the threshold voltage of the first stage driver transistor from the reset voltage. There is. Therefore, to lower the output circuit power supply voltage, the threshold voltage of the first-stage driver transistor 6 may be set to a large value. However, in the case of the conventional example in which the second-stage driver 9 has the same structure as the first-stage driver 6 as described in FIG. 15, if the threshold voltage of the transistor is too high, the next-stage driver transistor does not conduct sufficiently. The operation of the next stage becomes difficult. Therefore, in the present embodiment, the substrate impurity concentration of the driver transistors of the next and subsequent stages is made lower than the substrate impurity concentration of the driver transistors of the first stage, the threshold voltage of the driver transistors of the next and subsequent stages is lowered, and To work. FIG.
FIG. 1 shows an output circuit configuration diagram of the third embodiment. In the figure,
Reference numerals 111 and 112 denote driver transistors and load transistors constituting first stage source followers.
4 is a driver transistor constituting a next-stage source follower, load transistors, 115 and 116 are driver transistors constituting a final-stage source follower, load transistors 117 are bias voltage generation circuits of load transistors described in FIG. A p-well 21 formed on an n-type substrate 20 similar to the photoelectric conversion unit described in (b).
And the formation region of the double p-well 22, 118 is the p-well 21
A third p-well formation region having the same depth as that of the third p-well and having a slightly higher concentration. The double p-well layer is set at a high concentration for suppressing smear. The output voltage of the first-stage source follower becomes low due to the voltage drop due to the large threshold voltage of the first-stage driver transistor 111. On the other hand, the threshold voltages of the driver transistors 113 and 115 of the next and final stages are small values close to 0 V, the voltage drop due to the threshold voltage is small, and the input voltage and output voltage of each stage are almost equal. Does not become difficult. According to the present embodiment, driver transistors 113 and 115 at the next and subsequent stages
Of the first-stage driver transistor 111
By lowering the substrate impurity concentration of the first stage, a large voltage drop due to a high threshold voltage in the first stage is realized without complicating the operation range of the next stage and thereafter, lowering the power supply voltage,
An output circuit with low power consumption and low noise can be realized. In this embodiment, the case where the source follower has a three-stage configuration has been described for the purpose of improving the frequency characteristics of the output circuit.
If the number of stages is two or more, the effect of the present invention can be similarly obtained. Although the third p-well 118 has a slightly higher concentration at the same depth as the p-well 21 in order to prevent a malfunction at the time of the electronic shutter, the third p-well 118 is replaced with the p-well 21 when the malfunction is not a problem. The structure may be the same as described above. Further, the load transistors 112, 114, 116
9 may be formed in the well having the same structure. Further, by forming the driver transistors 113 and 115 in separated wells and connecting the wells to the output of each source follower to eliminate the substrate effect, the threshold voltage of each transistor can be made closer to 0V. Fourth Embodiment In the first embodiment, the DC voltage for discharging the excess voltage applied to the substrate is the positive power supply VDD. However, as described in the related art section, the DC voltage needs to be adjusted for each element. Therefore, in the present embodiment, VD
A DC voltage applied to the substrate is generated by stepping down from a voltage boosted from D, and means for adjusting the voltage is added to this step-down device. A fourth embodiment of the present invention will be described with reference to FIGS. FIG. 12 is an overall configuration diagram of the fourth embodiment, and FIG. 13 is a substrate voltage generation circuit according to the fourth embodiment. 12, reference numerals 1 to 10 and 12 to 17 are the same as those in FIG. Reference numeral 121 denotes the substrate voltage generation circuit shown in FIG. V1, V2, V3, V4, V1R, V
3R, H1, H2, RG, SUB, WELL, VDD,
Vss and OUT are the same as in FIG. A trigger pulse of the timing generator, a pulse having a predetermined voltage from two power supplies, positive and negative, and a DC voltage are generated inside the element, and the same operation as described in FIG. 17 is performed. In FIG. 13, reference numerals 91 to 99 denote the same DC booster circuit as in FIG.
Reference numeral 134 denotes an n-channel MOS transistor for generating a bias voltage; 135, a fuse for adjusting the bias voltage; 137, a CCD for lowering the boosted voltage in accordance with the bias voltage to generate a DC substrate voltage. N-channel depletion MOS
Transistor 138 is a load transistor for supplying a slight bias current to transistor 137, and 136 supplies a bias voltage to load transistor 138.
Is a circuit similar to. The output voltage of the booster circuit 139 is 13
The voltage is lowered to a voltage higher than the bias voltage generated from 1 to 134 by the absolute value of the threshold voltage of the n-channel depletion MOS transistor 137, and becomes a substrate DC voltage. The bias current supplied from the load 138 prevents a malfunction when a high voltage is generated on the substrate. Further, by performing the voltage drop by the n-channel depletion MOS transistor, it is possible to generate a substrate voltage higher than VDD even when a bias voltage lower than the power supply voltage VDD is applied. Also, the switch 98 connects its well to the output of the substrate voltage generation circuit to transmit a voltage higher than VDD, thereby preventing a threshold voltage increase due to the substrate effect. Other operations of this circuit are the same as those in FIG. The substrate voltage can be adjusted by cutting the fuse 135 as necessary. By cutting the fuse, the voltage at the node J rises and the substrate voltage rises. According to the present embodiment, the DC voltage applied to the substrate is generated by stepping down from the voltage boosted from VDD, and a means for adjusting the voltage is added to this step-down device. The usability of the imaging device is improved. Fifth Embodiment In the first embodiment, a trigger pulse must be externally applied to each terminal. In order to construct a camera system, a wiring between a timing generator and a two-dimensional CCD element must be performed. No. The present embodiment is an example in which a timing generator is incorporated to avoid such complexity. FIG.
FIG. 4 shows a configuration diagram of the fifth embodiment. In the figure, 1 to 1
Reference numeral 7 is the same as in FIG. 3, and reference numeral 141 denotes a step-down circuit for generating the power of the timing generator 142 from the external positive power supply VDD. A timing pulse of each pulse is generated from the external basic clock by the timing generator 142, and a pulse of a predetermined voltage level and a DC voltage are generated from the pulse and the positive and negative power supplies as in FIG. Is performed. According to this embodiment, a single external pulse and two positive and negative pulses
Easy to use 2D C that can be driven by power and ground
A CD solid-state imaging device can be provided.

In the above embodiment, the interline C
Although the example of the CD-type image pickup device has been described, the present invention can be similarly applied to a CCD-type image pickup device such as a frame interline type, a frame transfer type, and a charge sweep type regardless of the specific configuration of the CCD type image pickup device. . Further, the present invention has the same effect regardless of the specific configuration of the vertical CCD and the horizontal CCD, for example, in a CCD type image pickup device in which two horizontal CCDs are provided in parallel. As a result, the first embodiment is driven under the driving conditions shown in Table 2, and used in a camera system with the configuration shown in FIG. Further, the fifth embodiment is driven under the driving conditions shown in Table 3, and is used in a camera system with the configuration shown in FIG. In each case, it can be seen that the types of power supply voltages are much smaller than those shown in Table 1 of the related art.

[0026]

[Table 2]

[0027]

[Table 3]

According to the present invention, an easy-to-use CCD is used.
Type solid-state imaging device can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a vertical CCD ternary pulse generating circuit according to the present invention.

FIG. 2 is a circuit diagram of a vertical CCD ternary pulse generation basic circuit.

FIG. 3 is a block diagram showing the overall configuration of the first embodiment of the present invention.

FIG. 4 is a sectional view showing a portion corresponding to AA ′ and BB ′ in FIG. 3 and a sectional structure of a p-channel MOS transistor;

FIG. 5 is a circuit diagram showing a vertical CCD transfer pulse generation circuit in FIG. 3;

FIG. 6 is a circuit diagram showing a horizontal CCD transfer pulse generation circuit in FIG. 3;

FIG. 7 is a circuit diagram showing a reset pulse generation circuit in FIG. 3;

FIG. 8 is a circuit diagram showing a reset voltage generation circuit in FIG. 3;

FIG. 9 is a circuit diagram of a bias voltage generating circuit of the output circuit load transistor in FIG. 3;

FIG. 10 is a circuit diagram showing a substrate voltage generation circuit in FIG. 1;

FIG. 11 is a circuit diagram showing an output circuit configuration according to a third embodiment of the present invention.

FIG. 12 is a block diagram showing an overall configuration of a fourth embodiment of the present invention.

FIG. 13 is a circuit diagram showing the substrate voltage generation circuit of FIG. 12;

FIG. 14 is a block diagram showing the overall configuration of a fifth embodiment of the present invention.

FIG. 15 is a block diagram showing the overall configuration of a conventional CCD solid-state imaging device.

FIG. 16 is a block diagram of a conventional CCD camera.

FIG. 17 is a block diagram of a CCD camera of the CCD solid-state imaging device according to the first embodiment;

FIG. 18 is a block diagram of a CCD camera of a CCD solid-state imaging device according to a fifth embodiment.

[Explanation of Signs] 1. Photodiode, 2. Vertical CCD, 3.
... horizontal CCD, 4 ... output gate, 5 ... reset gate, 6, 111 ... initial stage source follower driver transistor, 8, 112 ... initial stage source follower load transistor, 9, 113 ... next stage source follower driver transistor, 10, 114 ... Next-stage source follower load transistor, 11, 121: substrate voltage generation circuit, 12: vertical CCD transfer pulse generation circuit, 13:
Vertical CCD tri-level pulse generation circuit, 14: horizontal transfer pulse generation circuit, 15: reset pulse generation circuit, 16
... Reset voltage generation circuit, 17 ... Load gate bias generation circuit, 20 ... N-type substrate, 21 ... P-type well,
22: p-type double well, 23: vertical CCD n layer, 2
4 ... polysilicon electrode, 25 ... n-well, 26 ...
Photodiode n-layer, 27... Surface p + layer, 28
... second layer aluminum for light shielding, 29 ... first layer aluminum for wiring, 3
0 ... n-type diffusion layer, 31, 41, 51, 71, 91, 9
7, 101: coupling capacitance, 32, 42, 52, 92: clamp diode, 33, 43, 37, 53, 63, 93
... First inverting circuit n-channel transistor, 34, 44,
38, 54, 64, 94... First inverting circuit p-channel transistor, 35, 45, 39, 55, 65, 95.
Inverting circuit n-channel transistor, 36, 46, 40,
56, 66, 96: second inverting circuit p-channel transistor, 47: n-channel transistor switch, 48, 1
02: p-channel transistor switch, 57: p-channel transistor voltage limiter, 58, 59: p-channel transistor for voltage limit, 60, 61, 62, 8
1, 82, 83, 131, 132, 133, 134... Bias voltage generating circuit n-channel transistors, 72, 7
3, 103 ... booster circuit n-channel transistor, 98 ...
N-channel depletion transistor switch, 9
9: substrate capacitance; 104: third inversion circuit n-channel transistor; 105: third inversion circuit p-channel transistor; 106: fourth inversion circuit n-channel transistor;
07... Fourth inversion circuit p-channel transistor, 115.
Final source follower driver transistor, 116 ...
Final-stage source follower load transistor, 117, 13
6 Bias voltage generation circuit 118 118 Third p-well 119 119 Formation region of p-well 21 and p-type double well 22 135 Fuse 137 N-channel depletion transistor voltage limiter 138 Load n-channel transistor 139 ... booster circuit, 14
1. Step-down circuit, 142 ... Timing generation circuit, V1, V2, V3, V4 ... Vertical CCD transfer trigger
Pulse input terminal, V1R, V3R: vertical CCD read trigger-pulse input terminal, H1, H2: horizontal CCD transfer trigger-pulse input terminal, RG: reset trigger-pulse input terminal, SUB: electronic shutter trigger-pulse input terminal, VDD ... Positive power supply input terminal, Vss ... Negative power supply input terminal, OUT ... Signal output terminal, WELL ... Well voltage input terminal, 161,171,181 ... CCD image pickup device, 162 ... Timing generator, 163 ... Driver, 164 ... Correlation Double sampling circuit, 165: automatic gain control circuit, 166: A / D converter, 167: digital signal processing circuit, 168: D / A converter, 169: D
C-DC converter, 170: camera battery.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Haruhiko Tanaka 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. Central Research Laboratory (72) Inventor Akira Sato 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd.

Claims (1)

[Claims] A photoelectric conversion element group for converting light into an electric signal; a vertical CCD for sequentially transferring optical signal charges generated by the photoelectric conversion element group; and an output circuit for detecting and amplifying the optical signal charges. A positive power supply having a value equal to the power supply value of the output circuit, and a trigger pulse being input to the electrode of the vertical CCD, the voltage of the positive power supply being equal to or higher than that of the positive power supply, and stabilizing the vertical CCD. A read pulse generating circuit for outputting a read pulse of a voltage value sufficient to operate
D-type solid-state imaging device.