JP2000152090A - Solid-state imaging device - Google Patents

Abstract

(57) [Problem] To provide a separate power supply when the power supply voltage of the second or subsequent stage is lowered in an output circuit comprising a multi-stage source follower circuit. You must increase or secure a dedicated power supply. SOLUTION: Multi-stage source follower circuits 17-1, 17
-2, 17-3, the vertical transfer clocks Vφ1 to Vφ4 are used as the back gate voltage and source voltage of the load MOS transistors Q12L, Q13L of the second and subsequent source follower circuits 17-2, 17-3.
, Ie, the negative power supply voltage VSS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a charge transfer type solid-state image pickup device having an output circuit having a source follower circuit structure for receiving and outputting an electric signal supplied from a charge detection section. About.

[0002]

2. Description of the Related Art Conventionally, CCD (Charge Coupled Device)
In such a charge transfer type solid-state imaging device, the output circuit has a configuration based on a multi-stage source follower circuit, and is driven by a single power supply such as 15V.
FIG. 5 shows a conventional example of an output circuit including a charge detection unit.

[0005] In FIG. 5, a charge detection unit 101 includes a floating diffusion FD and a reset drain R.
D and a reset gate RG located therebetween, and a reset drain voltage VRD of, for example, 15 V is applied to the reset drain RD. Then, a reset gate pulse φR is applied to the reset gate RG.
When G is applied, a reset operation of discharging charges in the floating diffusion FD to the reset drain RD is performed.

The output circuit 102 is constituted by, for example, three-stage source follower circuits 103-1 to 103-3. The first-stage source follower circuit 103-1 includes:
Driver MOS transistor Q101D having a gate connected to floating diffusion FD, and load MOS transistor Q101L having a drain connected to the source of driver MOS transistor Q101D.
And a resistor R101 connected between the source of the load MOS transistor Q101L and the ground.

[0005] The second-stage source follower circuit 103-2 comprises:
Driver MOS of source follower circuit 103-1 of first stage
A driver MOS transistor Q102D having a gate connected to the source of transistor Q101D, a load MOS transistor Q102L having a drain connected to the source of driver MOS transistor Q102D, and a source connected between the source of load MOS transistor Q102L and ground. And a resistor R102.

The third-stage source follower circuit 103-3
Driver MOS for the second-stage source follower circuit 103-2
A driver MOS transistor Q103D having a gate connected to the source of transistor Q102D, a load MOS transistor Q103L having a drain connected to the source of driver MOS transistor Q103D, and a source connected between the source of load MOS transistor Q103L and ground. And a resistor R103.

A power supply voltage VDD of about 15 V, which is substantially the same as the reset drain voltage VRD, is applied to each drain of the driver MOS transistors Q101D, Q102D, and Q103D at each stage. Further, the load MOS transistors Q101L, Q102L, Q10
Each gate of 3L is biased by the gate bias voltage VGG generated by the bias circuit 104.

In the output circuit 102 according to the conventional example having the above configuration, the input voltage of the first-stage source follower circuit 103-1 is, for example, 15 V because the input voltage is regulated by the reset drain voltage VRD. If a parasitic capacitance is added to the floating diffusion FD, the charge-to-voltage conversion gain in the charge detection unit 101 decreases, and the sensitivity decreases. Therefore, normally, the floating diffusion FD is directly connected to the gate of the first-stage driver MOS transistor Q101D.
Therefore, the power supply voltage of the first-stage source follower circuit 103-1 is 15 V, which is almost the same as the reset drain voltage VRD.
Becomes

That is, the power supply voltage VDD of 15 V is a voltage set due to a high reset drain voltage VRD, a high readout voltage of the sensor unit, and the like, and a dynamic range of an output circuit which is originally required, that is, a dynamic range. This voltage is too high for a CCD output signal from several hundred mV to at most about 2V. The first-stage source follower circuit 103-1 consumes a small amount of current and does not promote the power consumption of the entire device, but the second-stage and third-stage source follower circuits 103-2 and 103-3 include: Since an external emitter follower circuit or the like needs to be driven, it is necessary to consume a large amount of current. Therefore, if a source follower circuit of the same 15V power supply as the first stage is used, the power consumption becomes enormous.

[0010]

As a measure to avoid this, in an output circuit comprising a multi-stage source follower circuit, the power supply voltage of the second or subsequent source follower circuit having a large power consumption is set to, for example, 5V. There is also proposed a configuration for lowering the voltage. However, in the case of this configuration, since a separate power supply is required, disadvantages such as an increase in the number of power supply terminals and a dedicated power supply need to be secured.

In a conventional source follower circuit using a 15 V power supply, when the gate voltage of a constant current load MOS transistor is reduced, the gate-drain voltage of the load MOS transistor is increased, and the withstand voltage of the gate oxide film is reduced. As a result, secondary electrons and secondary holes are generated, and a gate oxide film is broken. Therefore, a dedicated bias circuit for supplying a gate bias voltage to the load MOS transistor has been required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a solid-state imaging device capable of greatly reducing power consumption without requiring a separate power supply. is there.

Another object of the present invention is to provide a load MOS
An object of the present invention is to provide a solid-state imaging device which does not require a dedicated bias circuit for applying a gate bias voltage to a transistor.

[0014]

The solid-state imaging device according to the present invention comprises a charge detecting section for converting a signal charge obtained by photoelectric conversion into an electric signal, and a multi-stage source follower circuit, and is supplied from the charge detecting section. And an output circuit for receiving and outputting the electrical signal, the output circuit driving the vertical transfer unit as the back gate voltage and the source voltage of the load MOS transistor in the source follower circuit except at least the first stage. The configuration uses a low level voltage of the drive voltage of the vertical transfer clock.

In the solid-state image pickup device having the above-described configuration, generally, the vertical transfer clock is set to the ground level and -7.5V.
, And the negative voltage is supplied as a protection element base voltage. This negative voltage, that is, the low level voltage of the drive voltage of the vertical transfer clock is applied to the load M in the source follower circuit excluding at least the first stage in the output circuit including the multi-stage source follower circuit.
By using the OS transistor as the back gate voltage and the source voltage, the current consumption is the same as in the related art, and the power supply voltage is changed from the first-stage power supply voltage of, for example, 15V to 7.0.
This means that the power consumption has been reduced to 5 V, and the power consumption has been halved.

Another solid-state imaging device according to the present invention is a charge detecting section for converting a signal charge obtained by photoelectric conversion into an electric signal, and an output circuit for receiving and outputting the electric signal supplied from the charge detecting section. A driver MOS transistor having a gate input of an electric signal from the charge detection unit; a load MOS transistor having a gate connected to a reference potential point;
A resistance element connected between the source of the transistor and the reference potential point;
A source follower circuit having an auxiliary MOS transistor connected between the S transistor and a gate connected to the source of the load MOS transistor is provided.

In another solid-state imaging device having the above configuration, the gate of the load MOS transistor has a reference potential point,
For example, by being connected to the ground, it functions as a constant current circuit that obtains a constant source potential and flows a constant current through a resistance element. Since a ground level is applied to the load MOS transistor as a gate bias voltage, a bias circuit is not required. In addition, auxiliary MOS
The transistor is interposed between the driver MOS transistor and the load MOS transistor, and has its gate connected to the source of the load MOS transistor, so that a gate-to-drain between the gate of the load MOS transistor and the ground level is given. It has the function of solving the problem of the pressure resistance.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the following description, a case where the present invention is applied to a CCD imaging device will be described as an example. However, the present invention is not limited to this, and an output circuit that receives an electric signal from a charge detection unit and outputs the signal is provided. The present invention is applicable to general charge transfer type solid-state imaging devices.

FIG. 1 is a schematic diagram showing a CCD image pickup device of, for example, IS (interlace scan) -IT (interline transfer) according to the present invention. In FIG. 1, a plurality of sensor units (pixels) 11 are arranged in rows (vertical).
Arranged in a matrix in the direction and the column (horizontal) direction,
The incident light is converted into a signal charge having a charge amount corresponding to the light amount and stored. A plurality of vertical CCDs 12 are provided for each vertical column of the sensor units 11, and a readout gate unit 13 is interposed between the vertical CCDs 12 and each sensor unit 11.

The signal charges accumulated in the plurality of sensor units 11 are read out to the vertical CCD 12 when a readout pulse XSG described later is applied to the readout gate unit 13 and the potential of the readout gate unit 13 becomes deeper. The vertical CCD 12 is transfer-driven by, for example, four-phase vertical transfer clocks Vφ1 to Vφ4, and vertically transfers the read signal charges sequentially in a portion corresponding to one scanning line (one line) in a part of the vertical blanking period ( Line shift).

Here, in the vertical CCD 12, the transfer electrodes of the first phase and the third phase also serve as the gate electrodes of the read gate unit 13. For this reason, among the four-phase vertical transfer clocks Vφ1 to Vφ4, the first-phase vertical transfer clock Vφ1 and the third-phase vertical transfer clock Vφ3 are set to have three values of a low level, an intermediate level, and a high level. The third high-level pulse is a read pulse XSG applied to the read gate unit 13.

A horizontal CCD 14 extends in the left-right direction in the drawing adjacent to the end of each of the plurality of vertical CCDs 12 on the transfer destination side. The horizontal CCD 14 includes a plurality of vertical CCDs.
Signal charges corresponding to one line from 12 are sequentially transferred. The horizontal CCD 14 is transfer-driven by, for example, two-phase horizontal transfer clocks Hφ1 and Hφ2, and a plurality of vertical CCDs
The signal charges for one line line-shifted from the CD 12 are sequentially and horizontally transferred in a horizontal scanning period after a horizontal blanking period.

At the end of the horizontal CCD 14 on the transfer destination side, for example, a charge detection unit 15 having a floating diffusion amplifier configuration is arranged. The charge detection unit 15 includes a floating diffusion FD, a reset drain RD, and a reset gate RG positioned between the floating diffusion FD and the reset drain RD. The charge detector 15 sequentially converts signal charges horizontally transferred by the horizontal CCD 14 into a signal voltage and outputs the signal voltage.

In the charge detecting section 15, for example, a reset drain voltage V of 15 V is applied to the reset drain RD.
RD is applied. Then, by applying the reset gate pulse φRG to the reset gate RG,
A reset operation for discharging the charges in the floating diffusion FD to the reset drain RD is performed. The signal voltage from the floating diffusion FD is
It is supplied to the output circuit 16.

FIG. 2 shows an output circuit 1 including a charge detection section 15.
6 shows a specific circuit configuration. The circuit configuration of the output circuit 16 is a feature of the present invention. In the charge detector 15, although not shown in FIG. 1, the reset gate RG has a low clamp circuit 1 composed of a parallel connection of a resistor and a diode in order to define a low level thereof.
8, a DC bias voltage VRGL is applied.

In FIG. 2, the output circuit 16 is, for example, 3
It is constituted by source follower circuits 17-1, 17-2, 17-3 in stages. First-stage source follower circuit 17-1
Is a driver MOS transistor Q11D having a gate connected to the floating diffusion FD, a load MOS transistor Q11L having a gate connected to, for example, the ground (ground) at a reference potential point, and a gate between the source and the ground of the load MOS transistor Q11L. , The source of the driver MOS transistor Q11D and the load MOS transistor Q11L
And the gate is connected to the load MO
Auxiliary MO connected to the source of S transistor Q11L
And an S transistor Q11S.

In the first-stage source follower circuit 17-1, a power supply voltage VDD of about 15 V, which is substantially the same as the reset drain voltage VRD of the charge detection section 1, is applied to the drain of the driver MOS transistor Q11D.

The second source follower circuit 17-2 includes a driver MOS transistor Q12D having a drain connected to the ground, and a driver MOS transistor Q1
A load MOS transistor Q12L having a drain connected to the source of 2D;
And a resistor R12 having one end connected to the source of 12L. Then, the load MOS transistor Q1
The 2L gate and the other end of the resistor R12 have, for example,-
A power supply voltage VSS of 7.5 V is applied.

The third-stage source follower circuit 17-3
A driver MOS transistor Q13D having a gate connected to the source and a drain connected to the ground of the driver MOS transistor Q12D of the source follower circuit 17-2 at the stage;
A load MOS transistor Q13L having a drain connected to the source of D;
The resistor R13 has one end connected to the 3L source. Then, the load MOS transistor Q13
The gate of L and the other end of the resistor R13 have a power supply voltage V
SS is applied.

Here, in a general CCD image pickup device, a vertical transfer clock Vφ1 for driving the vertical CCD 12 is used.
4 to Vφ4, the vertical transfer clocks Vφ1 and Vφ3 of the first and third phases, which take the ternary level in particular, are, for example, read pulses X as shown in the waveform diagram of FIG.
The high level voltage that becomes SG is 15 V, and the intermediate level voltage is 0.
V (ground level) and the low level voltage are set to -7.5V. That is, the negative power supply voltage VS of -7.5 V
S is supplied as a protection element base voltage of the CCD.

In the present embodiment, this
7.5V negative power supply voltage VSS, that is, vertical transfer clock V
The low-level drive voltages of φ1 to Vφ4 are
Load MO of the source follower circuits 17-2 and 17-3 of the stage
This is used as the back gate voltage and source voltage of the S transistors Q12L and Q13L.

Between the first-stage source follower circuit 17-1 and the second-stage source follower circuit 17-2, ie, the source of the first-stage driver MOS transistor Q11D and the gate of the second-stage driver MOS transistor Q12D. And a capacitor C is inserted between them. A clamp MOS transistor Q14 is connected between the output terminal of the capacitor C and the ground. This clamp MO
The reset gate pulse φRG used in the charge detection unit 15 is applied to the gate of the S transistor Q14.

Here, since the MOS transistor is a kind of resistance element, the capacitor C forms a differentiating circuit 19 together with the clamp MOS transistor Q14, and a direct current is supplied to the signal path for inputting the output signal of the first stage to the second stage. It functions to cut the voltage component. On the other hand, clamp MOS
The transistor Q14 forms a clamp circuit 20, and is turned on during the reset period of the charge detection unit 15 to which the reset gate pulse φRG is applied, thereby changing the input DC level of the second-stage source follower circuit 17-2 to two stages. It is defined by clamping to the ground level which is the power supply voltage after the first.

This DC voltage component is cut, and in the differentiating circuit 19 for defining the input DC level of the source follower circuit 17-2 in the second stage, that is, in the DC level defining circuit, it is connected to the ground instead of the clamp MOS transistor Q14. It is also possible to use a resistive element described above. However,
When a resistance element is used, since a mounting area is required to increase the resistance, it is preferable to use a MOS transistor from the viewpoint of the mounting area.

By the clamping operation of the clamp MOS transistor Q14, the output CCDOUT of the output circuit 16 is output.
Is clamped to the ground level. In this clamping method, it is not necessary to perform a hard clamp to the ground level for each signal, and it suffices that the soft clamp is performed over a plurality of output signals.

FIG. 4 shows the reset gate pulse φRG and the waveform of the output CCDOUT of the output circuit 16. All noise generated by the clamp operation of the clamp MOS transistor Q14 is removed by CDS (correlated double sampling) by an external signal processing circuit (not shown) for performing various signal processing on the output CCDOUT. You. In external signal processing, reset section (P phase) of output CCDOUT
CDS processing is performed by using the data section (D phase).

Therefore, the feed-through clamp does not contaminate these signals and can also be used as the reset gate pulse φRG, so that a dedicated clamp pulse is newly generated or a circuit for generating the clamp pulse is added. You don't have to. Further, if the soft clamp is used, there is no need to increase the current consumption of the source follower circuit 17-1 in the first stage, so that there is also an advantage in terms of power consumption.

As a conventional technique, there is also a plan to use the CDS clamping operation in this portion. However, in the case of the hard clamp, the current consumption of the first-stage source follower circuit is increased and the power consumption is increased. There are many disadvantages such as the need for a pulse input terminal. If a large mutual conductance gm cannot be obtained in the first stage, a configuration in which a two-stage source follower circuit is provided before the clamp is adopted, and the deterioration of S / N and the increase in power consumption due to the increase in the total number of circuit stages are reduced. Will be invited.

A diode D is inserted between the gate of the second-stage driver MOS transistor Q12D and the ground. That is, the anode of the diode D is connected to the gate of the driver MOS transistor Q12D, and the cathode is connected to the ground. When the power is turned on, the output of the first-stage source follower circuit 17-1 rises, and the diode D rises.
It functions as a high clamp circuit for preventing a high voltage from being applied to the gate of the OS transistor Q12D. as a result,
Destruction of the second-stage gate oxide film can be prevented.

With the above circuit configuration, the second and third source follower circuits 17-2 and 17-3 are operated between the ground level and the negative power supply voltage VSS (-7.5V in this example). be able to.

As described above, in the output circuit 16 including the multi-stage source follower circuits, the load MOS transistors Q of the second and subsequent source follower circuits 17-2 and 17-3 are used.
By using the low-level drive voltage of the vertical transfer clocks Vφ1 to Vφ4 as the back gate voltage and source voltage of the 12L and Q13L, the power consumption voltage has been reduced from 15V to 7.5V, unchanged from the conventional case. , Power consumption can be reduced by half.

Next, the first-stage source follower circuit 17-1
The circuit operation on the load side will be described in comparison with the conventional circuit of FIG. Note that the principle of the circuit on the load side is to obtain a constant source potential by applying a predetermined DC bias to the gate of the load MOS transistor.
A constant current circuit is formed by constantly flowing a constant current through the resistance element connected to the source.

Based on this fact, in the conventional circuit shown in FIG. 5, the bias circuit 104 generates a gate bias voltage VGG of, for example, 3 V, and applies this to the gate of the load MOS transistor Q101L. I was trying to get 3V. At this time,
Threshold voltage Vth of load MOS transistor Q101L
Is about 0V.

Assuming that the same operation is performed by the load-side circuit of the source follower circuit 17-1 according to the present embodiment, that is, the load MOS transistor Q11L whose gate is grounded, the resistance R11 is the same as the conventional resistance R101. The load MOS transistor Q11 is set to a value such that the source potential becomes approximately 3 V when 0 V (ground level) is applied to the gate of the load MOS transistor Q11L.
By adjusting the potential of L, the same constant current characteristic as that of the conventional circuit is obtained. At this time, load MO
The threshold voltage Vth of S transistor Q11L is about -3V.

On the other hand, if the power supply voltage of the first stage is 15V, the output voltage of the first stage is about 10V to 15V.
At this time, if the gate bias voltage VGG of 0 V is applied to the load MOS transistor Q101L in the conventional circuit, the gate-drain voltage of the load MOS transistor Q101L becomes a high voltage of 10 V or more, and the withstand voltage of the gate oxide film is lost. .

On the other hand, in the source follower circuit 17-1 according to the present embodiment, the driver MOS transistor Q
The auxiliary MOS transistor Q11S is inserted between the source of the load MOS transistor Q11L and the drain of the load MOS transistor Q11L.
Since the configuration connected to the source of
The gate voltage of the OS transistor Q11S becomes about 3V. As a result, the gate-drain voltage of the auxiliary MOS transistor Q11S is maintained in the same relationship as in the conventional circuit, and the problem of the withstand voltage is solved.

That is, the driver MOS transistor Q
An auxiliary MOS transistor Q11S is inserted between the source of the load MOS transistor Q11L and the drain of the load MOS transistor Q11L.
By connecting to the source of L, even if a gate bias voltage of 0 V is applied to the load MOS transistor Q11L, it is possible to obtain a constant current characteristic while solving the problem of withstand voltage, and to use a dedicated bias for generating the gate bias voltage. There is no need to provide a circuit.

A technique for solving the problem of the withstand voltage is as follows.
The present invention is not limited to the application to the output circuit 16 according to the present embodiment shown in FIG. 2. For example, the source follower circuits 103-1 to 103-3 of each stage in the conventional circuit shown in FIG.
Can be applied to the load side circuit. By employing such a circuit configuration, the number of the bias circuits 104 can be reduced, so that the effect is extremely large in terms of simplifying the circuit configuration and reducing power consumption.

In the above embodiment, the present invention is applied to an output circuit comprising a three-stage source follower circuit, and the vertical transfer clocks Vφ1 to Vφ1 are used as the back gate voltage and source voltage of the load MOS transistors in the second and subsequent source follower circuits. The case where the configuration uses a low-level drive voltage of Vφ4 has been described as an example, but the present invention is not limited to this.

That is, the number of stages of the source follower circuit is 2
Any number of stages or more may be used. For example, the power supply voltage of 15 V is not limited to the first stage. In short, the source follower circuit excluding at least the first stage (second stage or later) In this case, any configuration may be used as long as the low gate voltage of the vertical transfer clocks Vφ1 to Vφ4 is used as the back gate voltage and the source voltage of the load MOS transistor.

[0051]

As described above, according to the present invention,
In a solid-state imaging device including an output circuit including a multi-stage source follower circuit, a low drive voltage of a vertical transfer clock is used as the back gate voltage and the source voltage of the load MOS transistors of the second and subsequent source follower circuits in the output circuit. By using the level voltage,
The current consumption is the same as the conventional one, and since the power supply voltage has been reduced from, for example, 15 V to 7.5 V, the power consumption can be greatly reduced.

In a solid-state imaging device having an output circuit, the output circuit is connected to a gate of the load MOS transistor at a reference potential point, a source is connected to a resistance element, and a driver MOS transistor and a load MOS transistor are connected. Since an auxiliary MOS transistor is interposed between the transistor and the gate and the gate is connected to the source of the load MOS transistor, a bias circuit for generating a gate bias voltage of the load MOS transistor is not required. In addition to simplification, power consumption can be reduced by the amount consumed by the bias circuit.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing an IS-IT CCD imaging device according to the present invention.

FIG. 2 is a circuit diagram showing a specific circuit configuration of an output circuit including a charge detection unit according to one embodiment of the present invention.

FIG. 3 is a waveform diagram of first and third phase vertical transfer clocks;

FIG. 4 is a waveform diagram of a reset gate pulse and a CCD output.

FIG. 5 is a circuit diagram showing a conventional example.

[Explanation of symbols]

11 sensor part, 12 vertical CCD, 14 horizontal CC
D, 15: charge detection unit, 16: output circuit, 17-1, 17
-2, 17-3: Source follower circuit, 19: Differentiator circuit, 2
0 ... Clamp circuit

Claims (4)

[Claims] 1. An output comprising a charge detection unit for converting signal charges obtained by photoelectric conversion into an electric signal, and a multi-stage source follower circuit, receiving an electric signal supplied from the charge detection unit and outputting the electric signal. A solid-state imaging device comprising: a driving circuit for driving a vertical transfer clock for driving a vertical transfer unit as a back gate voltage and a source voltage of a load MOS transistor in a source follower circuit excluding at least a first stage; A solid-state imaging device using a low-level voltage. 2. An output circuit according to claim 1, wherein said output circuit cuts a DC voltage component between a source follower circuit using a low-level voltage of the drive voltage of said vertical transfer clock and a source follower circuit at a stage preceding said source follower circuit. 2. The solid-state imaging device according to claim 1, further comprising a DC level defining circuit for defining an input DC level of the source follower circuit. 3. The solid-state imaging device according to claim 2, wherein the DC level defining circuit is operable in response to a reset signal for performing a reset operation of the charge detection unit to define the input DC level. apparatus. 4. A solid-state imaging device comprising: a charge detection unit that converts a signal charge obtained by photoelectric conversion into an electric signal; and an output circuit that receives and outputs the electric signal supplied from the charge detection unit. A driver MOS transistor having an electric signal from the charge detection unit as a gate input, a load MOS transistor having a gate connected to a reference potential point,
A resistance element connected between the source of the load MOS transistor and a reference potential point; a resistance element connected between the driver MOS transistor and the load MOS transistor; and a gate connected to the source of the load MOS transistor. A solid-state imaging device comprising a source follower circuit having an auxiliary MOS transistor.