JP2001024061A - Design method and primitive layout of asic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To cut a data layer by forming a contact hole in a predetermined position of a well contact layer and a sub-contact layer and generating a well contact and a sub-contact. SOLUTION: The width of a generation predetermined layer 6 in the direction set by a primitive cell frame is distinguished into a generation predetermined layer 6 which satisfies conditions and a generation predetermined layer 6 which does not satisfy conditions. The generation predetermined layer 6 which satisfies conditions is converted to a well contact layer and a sub-contact layer 9. A contact hole is generated at a center in the transverse direction of the well contact layer and the sub-contact layer 9, then a chip layout 4, a well contact and a sub-contact 11 are merged in a merge treatment process 12, and an actual chip layout 13 is prepared. As a result, a data layer can be cut.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for generating well contacts and sub-contacts after automatic placement in an ASIC chip design, and a program for causing a computer to execute a primitive layout and a method for generating well contacts and sub-contacts constituting an ASIC chip. And a computer-readable storage medium having recorded thereon.

[0002]

2. Description of the Related Art Generally, a required number of well contacts and sub-contacts are arranged in a chip in order to stabilize a substrate potential and to prevent latch-up. On the other hand, when the well contact and the sub contact are arranged in the primitive layout, it is not necessary to have the well contact and the sub contact in every primitive layout. In addition, a brief description will be given of a conventional method of preventing an increase in cell size of a primitive layout and arranging a required number of cells in a chip. Such a method has no well contact and sub-contact in the primitive layout,
Insertion of well contacts and sub-contacts after the chip layout is created prevents an increase in chip size. If the increase in the cell size of the primitive layout does not directly affect the cell size, the primitive layout has well contacts and sub-contacts.

An example of the above-described prior art will be described with reference to the drawings. FIG. 9 is a plan view showing a conventional primitive layout. The arrangement area of the primitive layout 36 shown in FIG. 9 is determined by the primitive cell frame (peripheral portion) 14. In addition, the primitive layout 36 is installed so as to satisfy the circuit function of each primitive cell (since the shape and size of the primitive cell are determined by the primitive cell frame, no particular reference numerals are given). This is the layout of the transistors and wirings. Such transistors and wirings are arranged in a primitive cell frame so as to satisfy a criterion of an interval between adjacent data when the chip is arranged. Further, the primitive layout 36 has the VDD supply wiring 15 and the GND supply wiring 16. Further, the source contact 17 for supplying VDD to the Pch transistor diffusion layer 43 and the Nch transistor diffusion layer 4
4 had a source contact 18 for supplying GND.

Next, a conventional method of generating well contacts and sub-contacts during automatic arrangement will be described with reference to FIGS. FIG. 10 is a flowchart of a conventional well contact and subcontact generation method. The placement information 1 is information of a primitive cell obtained by the automatic placement step 31 in the ASIC chip design. The chip layout creating step 3 reads the layout information 1 and the primitive layout 36, and reads the chip layout 4
Was output. In the potential tracking step 37, the chip layout 4 is input and each primitive layout 3
This was a step of detecting whether the diffusion layers (not shown) at both ends of No. 6 serve as a source or a drain. Next, the potential supplied from the diffusion layers at both ends of each primitive layout 36 to the diffusion layers is VDD or GN.
In the case of D, the source was determined, and in the case of the normal signal, the drain was determined. The determined result is the shape of the diffusion layers at both ends, as different layers in the source / drain, and as different layers in the N well (not shown) and the P well (not shown), for a total of four types of layers. And output to the source / drain definition 38. The boundary generation condition 39 defines the distance between the source diffusion layer and the well contact and the sub-contact, and the distance between the drain diffusion layer and the well contact and the sub-contact. For example, the distance between the source diffusion layer and the well contact and the sub-contact is 0 μm, and the distance between the drain diffusion layer and the well contact and the sub-contact is 0.3 μm. The well contact and sub-contact generation boundary creation step 40 includes source / drain definition 3
8 and the boundary generation condition 39 are input, and the well contact and the sub contact generation boundary 4 are set at a position at a distance defined by the boundary generation condition 39 from each source / drain definition 38.
Create 1. The well contact / subcontact generation boundary 41 has a width in the extension direction of the primitive cell frame 14 in which the well contact and the subcontact can be generated. Further, the well contact and sub-contact occurrence condition 7 is determined according to an adjacent occurrence boundary 41.
This defines the distance in which a well contact and a sub contact can be generated. Inter-boundary length measurement step 42
Has generated the well contact and sub-contact layer 9 by measuring the distance between the adjacent well contact and sub-contact occurrence boundary 41 with the occurrence boundary 41 and the well contact and sub contact occurrence condition 7 as inputs. Also, the well contact and sub contact layer 9
Was able to allocate another layer in the N-well and P-well. Subsequent steps are the same as in the first embodiment of the present invention, and a description thereof will be omitted.

[0005]

However, even the above-described prior art well contact and subcontact insertion methods have the following further problems. There are many processing steps such as the potential tracking step 37, and the processing time required for one processing is long. This is because the number of primitive cells and the number of transistors used are large in the current large-scale highly integrated chip. Furthermore, since at least four data layers are required, the processing time increases due to an increase in the amount of data to be handled. Potential tracking requires at least four layers of a P diffusion layer, an N diffusion layer, a contact, and a power supply wiring. If a power supply wiring uses an upper wiring layer, the number of necessary data layers increases. Also, the layers required to generate well contacts and sub-contacts are
The number of layers for recognizing the drain is increased by two, and a total of four layers are required.

The present invention has been made in view of the above-mentioned problems in the prior art, and simplifies a processing step by providing a dummy layer in a primitive cell in advance, reliably generates a well-con- Another object of the present invention is to improve performance and reduce costs by reducing the number of data layers.

[0007]

According to a first aspect of the present invention, there is provided an automatic arranging step of automatically arranging primitive cells, and a step of forming the primitive cells in a primitive cell so as to satisfy a circuit function of each primitive cell. A dummy layer is formed in a region defined by a peripheral portion of a primitive cell which is opposed to and adjacent to a diffusion layer of the transistor, and a primitive which is adjacent to the dummy layer. A chip for creating a chip layout using data of a primitive layout in which the width of the dummy layer in the extension direction of the peripheral portion of the cell is formed to a predetermined width and the arrangement information of the primitive cells obtained by the automatic arrangement step; Layout creation process,
Extract the dummy layer included in the primitive layout,
A generation contact layer extraction step of forming a generation contact layer, a well contact / subcontact generation contact area step of giving the well contact / subcontact occurrence condition to the generation contact layer, and a well contact from the well contact / subcontact occurrence condition. A step of generating a well contact and a sub contact, in which the generation scheduled layer determined to be possible is determined as a well contact layer and a sub contact layer, and a contact is made at a predetermined position of the well contact layer and the sub contact layer. A contact hole forming step of forming a hole and generating a well contact and a sub contact.

Therefore, according to the well contact and sub-contact generation method of the first invention of the present application, an automatic arrangement step for automatically arranging the primitive cells, and a method for arranging the primitive cells in the primitive cells so as to satisfy the circuit function of each primitive cell. This is a layout of the formed transistor and wiring, in which a dummy layer is formed in a region which is opposed to the diffusion layer of the transistor and which is set by the peripheral portion of the primitive cell which is close to the transistor, and which is close to the dummy layer. A chip layout is created using data of a primitive layout in which the width of the dummy layer in the extension direction of the peripheral portion of the primitive cell is formed to a predetermined width and the arrangement information of the primitive cell obtained by the automatic arrangement step. Chip layout creation process and damage included in primitive layout Extracting a layer to form a layer to be generated; extracting a layer to be generated; forming a well contact and a sub-contact in the generated layer; From the conditions, it is determined whether or not a well contact and a sub contact occur,
A step of generating a well contact and a sub-contact using a layer to be generated determined to be possible as a well contact layer and a sub-contact layer, and forming a contact hole in a predetermined position of the well contact layer and the sub-contact layer; This is characterized in that the method comprises a step of forming a contact hole for generating the processing time, so that there is an advantage that the processing time and the processing step are reduced. Therefore, it is possible to improve productivity, improve workability, and further reduce costs.

Further, the second invention of the present application provides an automatic arrangement step of automatically arranging primitive cells, a transistor, a wiring, a well contact, and a well formed in the primitive cells so as to satisfy the circuit function of each primitive cell. A layout of sub-contacts, wherein a dummy layer is formed in a region defined by a peripheral portion of a primitive cell which is opposed to and adjacent to a diffusion layer of a transistor, and a peripheral portion of the primitive cell which is adjacent to the dummy layer. The width of the dummy layer in the extension direction of the portion is formed to a predetermined width,
Further, a primitive layout in which a dummy layer is formed on the upper layer of the well contact and the sub contact, and a chip layout creating step of creating a chip layout using data of the arrangement information of the primitive cells obtained by the automatic arrangement step, Extracting a dummy layer included in the primitive layout and forming a generation scheduled layer; forming a generation scheduled layer; a well contact and sub contact generation scheduled region step of giving the well contact and sub contact generation condition to the generation scheduled layer; From the well contact and sub-contact occurrence conditions, determine whether or not the well contact and sub-contact can be generated, and a well contact and sub-contact generation step of setting the generation scheduled layer determined to be possible as a well contact layer and a sub-contact layer, Provide the necessary conditions of the well contact and the sub-contact which define the required number of the well contact and the sub-contact arranged in the chip constituted by the primitive layout, and determine whether the well contact and the sub-contact layer exist at a necessary interval in the chip. A contact hole forming step of forming a contact hole at a predetermined position of a well contact and a sub contact layer to generate a well contact and a sub contact; This is the generation method.

Therefore, according to the well contact and sub contact generation method of the second invention of the present application, an automatic arrangement step for automatically arranging the primitive cells, and a method for forming the primitive cells in the primitive cells so as to satisfy the circuit function of each primitive cell. Layout of a transistor, wiring, well contact and sub-contact, wherein a dummy layer is formed in a region which is opposed to a diffusion layer of the transistor and which is set by a peripheral portion of a primitive cell adjacent thereto. A primitive layout in which the width of the dummy layer in the extension direction of the peripheral portion of the primitive cell close to the layer is formed to a predetermined width, and further the dummy layer is formed on the well contact and the sub contact,
A chip layout creation step of creating a chip layout using data of the primitive cell placement information obtained by the automatic placement step, and a dummy layer included in the primitive layout, and a generation scheduled layer for forming a generation scheduled layer From the extraction step, the well contact and subcontact occurrence region step of giving the well contact and subcontact occurrence conditions to the occurrence scheduled layer, and whether or not the well contact and subcontact occurrence can be determined from the well contact and subcontact occurrence conditions The well contact and subcontact generation step in which a layer to be generated determined to be possible is defined as a well contact layer and a subcontact layer, and the required number of well contacts and subcontacts to be arranged in a chip having a primitive layout. An essential condition determining step of determining whether a well contact and a sub-contact layer are present at a required interval in a chip by providing a well contact and a sub-contact essential condition to be defined, and contacting a predetermined position of the well contact and the sub-contact layer To form a hole,
And a contact hole forming step for generating well contacts and sub-contacts. Therefore, even in a large-scale and highly integrated chip, the dummy layer can be formed in a short time by a simple method such as graphic processing. Has the advantage that a well contact and a sub contact can be generated. Further, the processing steps can be simplified.
Further, the number of required data layers is smaller than that of the conventional one, and the amount of data to be handled is reduced, so that there is an advantage that the processing time is shortened. Therefore, it is possible to improve productivity, improve workability, and further reduce costs.

Further, in the third invention of the present application, the well contact and the sub contact generation condition may be such that a dummy layer set by a distance between a peripheral edge of a primitive cell facing a diffusion layer of the transistor and a diffusion layer of the transistor. It is characterized in that the propriety is determined only by the width.

Therefore, according to the well contact and sub-contact generation method of the third invention of the present application, the well contact and sub-contact generation conditions are based on the peripheral portion of the primitive cell facing the diffusion layer of the transistor and the diffusion layer of the transistor. Is determined only by the width of the dummy layer set by the distance of
When forming the contact, the step of determining the width of the dummy layer in the extension direction of the peripheral portion of the primitive cell facing the diffusion layer of the transistor capable of forming the contact is omitted, and the well contact is formed only by simple graphic processing. In addition, there is an advantage that it is possible to determine whether or not a sub-contact occurs. That is, there is an advantage that simplification of a processing step and reduction of cost can be realized.

The fourth invention of the present application is characterized in that the predetermined position in the contact hole forming step is near the center of the well contact and the sub contact layer.

Therefore, according to the well contact and sub-contact generation method of the fourth invention of the present application, the predetermined position in the contact hole forming step can be set near the center of the well contact and sub-contact layer. There is an advantage that a well contact and a sub contact capable of performing a function can be reliably generated.

In a fifth aspect of the present invention, in a primitive layout including a transistor and a wiring, a peripheral portion of the primitive cell opposed to a diffusion layer of the transistor provided in the primitive cell in which the primitive layout is configured; A primitive layout comprising a dummy layer disposed in a region formed by a diffusion layer of a transistor.

Therefore, according to the semiconductor device of the fifth aspect of the present invention, in a primitive layout including a primitive cell including a transistor and a wiring, a predetermined position where a dummy layer in the primitive cell is arranged in an automatic arrangement step. Is characterized by being arranged in a region formed by a part of the peripheral edge of the primitive cell facing the diffusion layer of the transistor provided in the primitive cell and the diffusion layer of the transistor, There is an advantage that a well contact and a sub contact can be reliably generated in such a dummy layer by a simple method in a short time.

The sixth invention of the present application is characterized in that the width of the dummy layer in the extension direction of the peripheral portion of the primitive cell adjacent to the dummy layer is formed to a predetermined width.

Therefore, according to the semiconductor device of the sixth aspect of the present invention, the width of the dummy layer in the extension direction of the peripheral portion of the primitive cell adjacent to the dummy layer is formed to a predetermined width. There is an advantage that well contacts and sub-contacts can be generated only by simple graphic processing. That is, there is an advantage that simplification of a processing step and reduction of cost can be realized.

Further, the seventh invention of the present application is directed to an automatic arranging step of automatically arranging primitive cells, and a layout of transistors and wirings formed in the primitive cells so as to satisfy the circuit functions of each primitive cell. A dummy layer is formed in a region defined by a peripheral portion of a primitive cell which is opposed to and adjacent to a diffusion layer of a transistor, and a dummy in an extension direction of a peripheral portion of the primitive cell which is adjacent to the dummy layer. A chip layout creating step of creating a chip layout by using data of a primitive layout having a layer width formed to a predetermined width and arrangement information of primitive cells obtained by the automatic arrangement step; A generation layer extraction step of extracting a dummy layer to be generated and generating a generation layer, From the well contact and sub contact generation region step of providing a well contact and sub contact generation condition to the planned layer and the well contact and sub contact generation condition, it is determined whether the well contact and the sub contact can be generated, and it is determined that the generation is possible. Forming a well contact and a sub contact layer using the layer to be generated as a well contact and a sub contact layer; and forming a contact hole at a predetermined position of the well contact layer and the sub contact layer to generate a well contact and a sub contact. Forming step;
A method of generating a well contact and a sub-contact, comprising: inputting a well contact and a sub-contact and a chip layout; and outputting a real chip layout in a state where the well contact and the sub-contact are merged into the chip layout. Is a computer-readable storage medium that stores a program that causes a computer to execute the program.

Therefore, according to the computer-readable storage medium storing a program for causing a computer to execute the well contact and sub-contact generation method of the seventh invention of the present application, an automatic arrangement step for automatically arranging primitive cells; This is a layout of transistors and wirings formed in the primitive cell so as to satisfy the circuit function of each primitive cell. A layer is formed,
The data of the primitive layout in which the width of the dummy layer in the extension direction of the peripheral portion of the primitive cell adjacent to the dummy layer is formed to a predetermined width and the arrangement information of the primitive cell obtained by the automatic arrangement step are A chip layout creation step of creating a chip layout, a dummy layer extraction step of extracting a dummy layer included in the primitive layout and generating a generation layer, and a well contact and sub contact generation condition for the generation layer. A given well contact and subcontact generation region step, and judging whether or not a well contact and a subcontact can be generated based on the well contact and subcontact generation conditions, and setting the generation planned layer determined to be possible as a well contact and a subcontact layer. Well contact and support A contact generating step, a contact hole forming step of generating a contact hole at a predetermined position of a well contact layer and a sub contact layer, and generating a well contact and a sub contact; And a merge processing step of outputting an actual chip layout in a state where the well contact and the sub-contact are merged into the layout. A computer that operates by reading a recording medium on which such a procedure is recorded, and that operates based on the algorithm of each process, can be used for simple processing such as graphic processing even for a large-scale highly integrated chip. There is an advantage that the well contact and the sub contact can be generated in a short time by the method. Further, the number of required data layers is smaller than that of the conventional one, and the amount of data to be handled is reduced, so that there is an advantage that the processing time is shortened. Therefore, it is possible to improve productivity, improve workability, and further reduce costs.

According to an eighth aspect of the present invention, there is provided an automatic arranging step for automatically arranging primitive cells, a transistor, a wiring, a well contact, and a well formed in the primitive cells so as to satisfy the circuit function of each primitive cell. A layout of sub-contacts, wherein a dummy layer is formed in a region defined by a peripheral portion of a primitive cell which is opposed to and adjacent to a diffusion layer of a transistor, and a peripheral portion of the primitive cell which is adjacent to the dummy layer. The width of the dummy layer in the extension direction of the portion is formed to a predetermined width,
Further, a primitive layout in which a dummy layer is formed on the upper layer of the well contact and the sub contact, and a chip layout creating step of creating a chip layout using data of the arrangement information of the primitive cells obtained by the automatic arrangement step, A generation layer extraction step of extracting a dummy layer included in the primitive layout and forming a generation layer, a well contact and sub contact generation area step of providing a well contact and a sub contact generation condition to the generation layer, and the well A step of generating a well contact and a sub-contact by determining whether or not a well contact and a sub-contact can be generated based on the contact and sub-contact generation conditions; A well contact and a sub-contact essential condition for defining a required number of well contacts and sub-contacts to be arranged in a chip configured in the active layout; and the well contact and the sub contact essential condition. A contact hole forming step of forming a contact hole at a predetermined position of a well contact and a sub contact layer to generate a well contact and a sub contact, and a well contact; And a merge processing step of inputting the sub-contact and the chip layout and outputting a real chip layout in a state where the well contact and the sub-contact are merged into the chip layout. The program for executing the contact occurs techniques computer is a computer-readable recording medium having recorded.

Therefore, according to the computer-readable recording medium on which the program for causing a computer to execute the well contact and sub-contact generation method according to the eighth aspect of the present invention, an automatic arrangement step for automatically arranging primitive cells, This is a layout of transistors, wiring, well contacts, and sub-contacts formed in the primitive cell so as to satisfy the circuit function of each primitive cell. A dummy layer is formed in a region to be set, and the width of the dummy layer in the extension direction of the peripheral portion of the primitive cell adjacent to the dummy layer is formed to have a predetermined width. Primitive with dummy layer formed on Using the data of the layout and the arrangement information of the primitive cells obtained by the automatic arrangement step, a chip layout creation step of creating a chip layout, and extracting a dummy layer included in the primitive layout to form a layer to be generated A generation scheduled layer extraction step, a well contact / sub contact generation planned area step of giving a well contact / sub contact generation condition to the generation scheduled layer, and whether or not a well contact and a sub contact can be generated based on the well contact and sub contact generation condition. A step of generating a well contact and a sub-contact in which a layer to be generated is determined as a well contact layer and a sub-contact layer, and a well contact and a sub-contact arranged in a chip having a primitive layout Well contact and sub-contact essential conditions that define the required number, and the well contact and sub-contact essential conditions are given, and an essential condition determining step of determining whether the well contact and the sub contact layer are present at a necessary interval in the chip, A contact hole is formed at a predetermined position of a well contact and a sub contact layer, a contact hole forming step for generating the well contact and the sub contact, the well contact and the sub contact, and the chip layout are input, and the well contact and the sub contact are included in the chip layout. And a merge processing step of outputting an actual chip layout in a merged state. A device that operates based on the algorithm of each process by a computer that reads and operates a recording medium on which such a procedure is recorded can be operated by a simple method such as graphic processing, even for a large-scale highly integrated chip. There is an advantage that a well contact and a sub contact can be generated in a short time. Further, the number of required data layers is smaller than that of the conventional one, and the amount of data to be handled is reduced, so that there is an advantage that the processing time is shortened. Therefore, productivity improvement,
It is possible to improve workability and further reduce cost.

In the ninth invention of the present application, the well contact and sub-contact generation conditions are such that the width of the dummy layer is set by the distance between the periphery of the primitive cell facing the diffusion layer of the transistor and the diffusion layer of the transistor. It is characterized in that the determination is made only by using the information.

Therefore, according to the computer-readable recording medium on which the program for causing a computer to execute the well contact and sub-contact generation method of the ninth invention of the present application, the well contact and sub-contact generation conditions are determined by the transistor The determination is made based on only the width of the dummy layer set by the distance between the peripheral edge of the primitive cell facing the diffusion layer and the diffusion layer of the transistor. An apparatus that operates based on the algorithm of each step by a computer that reads and operates a recording medium on which such a procedure is recorded is a dummy in the peripheral direction of a primitive cell in which a contact can be formed when a contact is formed. It is not necessary to determine the width of the layer, and there is an advantage that well contacts and sub-contacts can be generated only by graphic processing. That is, there is an advantage that simplification of a processing step and reduction of cost can be realized.

The tenth invention of the present application is characterized in that the predetermined position in the contact hole forming step is near the center of the well contact and the sub contact layer.

Therefore, according to the computer-readable recording medium on which the program for causing a computer to execute the well contact and sub-contact generation method according to the tenth aspect of the present invention, a predetermined position in the contact hole forming step is set to the well contact position. And near the center of the sub-contact layer. An apparatus that operates based on the algorithm of each process by a computer that reads and operates a recording medium on which such a procedure is recorded has an advantage that a well contact and a subcontact can be reliably generated.

[0027]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a first embodiment of the present invention; This will be described with reference to the drawings.

Embodiment 1 FIG. 1 is a layout diagram showing a primitive layout according to Embodiment 1 of the present invention. FIG. 2 is a flowchart of a well contact and subcontact generation method at the time of automatic arrangement according to the first embodiment of the present invention. Before describing the method of generating well contacts and sub-contacts at the time of automatic placement according to the first embodiment of the present invention in FIG. 2, a primitive layout 2 as a component thereof will be described with reference to FIG. In FIG. 1, a primitive layout 2 according to the first embodiment of the present invention is a layout of transistors and wiring arranged so as to satisfy a circuit function of each primitive cell on a chip layout 4. Primitive cell frames 1 are arranged so that the transistors and wirings laid out satisfy the interval standard between adjacent data at the time of chip arrangement.
4. Further, the primitive layout 2 is formed by the primitive cell frame 14 facing the Pch transistor diffusion layer 43 or the Nch transistor diffusion layer 44 provided in the primitive cell, and the Pch transistor diffusion layer 43 and the Nch transistor diffusion layer 44. Dummy layers 19, 20, and 21 for generating well contacts and sub-contacts are provided in the region. The primitive cell frame 14 defines a region of a primitive cell. The primitive layout 2 is configured inside the primitive cell frame 14. That is, the primitive cell frame 14 has a standardized size, and each element such as a transistor is configured inside the primitive cell frame 14. Further, the primitive layout 2 has a VDD supply line 15 and a GND supply line 16. Further, source contact 17 for supplying VDD to Pch transistor diffusion layer 43, N
The source contact 18 for supplying GND to the channel transistor diffusion layer 44 is provided. The dummy layer 19 for generating a well contact and a sub-contact in an N-well (not shown) is arranged between the end of the Pch transistor diffusion layer 43 serving as a source and the primitive cell frame 14. . Further, the dummy layer 19 is formed in a region which is opposed to the diffusion layer of the transistor and is set by the peripheral portion of the primitive cell adjacent thereto, and a primitive cell frame which is adjacent to the dummy layer. 14 is formed to have a predetermined width (hereinafter, height). Further, the height is formed to be a width capable of generating a well contact and a sub contact. Also, a dummy layer 20 for generating a well contact and a sub-contact formed in a P-well (not shown)
Is the source Nch transistor diffusion layer 44
And the primitive cell frame 14. The dummy layer 20 is formed at a height at which well contacts and sub-contacts can be generated similarly to the dummy layer 19. The height at which the well contact and the sub contact described above can be generated differs depending on the type of the chip, and thus is not particularly defined. The well layer and the sub-contact generation dummy layer 21 in the P-well define the distance between the N-channel transistor diffusion layer 44 and the well contact and the sub-contact from the end of the N-channel transistor diffusion layer 44 serving as the drain. It is arranged between a position separated by a distance satisfying the design criteria and the primitive cell frame 14. Dummy layer 21
Is formed at a height at which well contacts and sub-contacts can be generated. Also, the dummy layers 19 for generating the well contacts and sub-contacts in the N-well and the dummy layers 20 and 21 for generating the well contacts and sub-contacts in the P well have different properties from the layers used in the actual layout. You have assigned layers. A dummy layer is not arranged at the right end in the N well. However, if a distance satisfying a design standard defining the distance between the Nch transistor diffusion layer 43 and the well contact and the sub contact cannot be ensured, the dummy layer is not necessary. Good.

Next, with reference to FIG. 2, a description will be given of a method of generating well contacts and sub-contacts during automatic placement according to the first embodiment of the present invention. Dummy layers that are components of the well contact and sub-contact generation method described here are the dummy layers 19, 20, and 21 shown in FIG.
The chip layout in FIG. 2 includes the primitive layout 2 shown in FIG. 1 as a component. The dummy layer is selected and converted into a different data layer as the process sequentially proceeds. From the above points,
The dummy layers in the description of FIG. 2 are described without reference numerals in order to avoid confusion due to the reference numbers. The description of such a dummy layer will be made later with reference to another drawing.

Referring to FIG. 2, a method of generating well contacts and sub-contacts during automatic placement will be described. In this paragraph, the configuration will be described first. The arrangement information 1 is information that can be obtained by the automatic arrangement 31 of the primitive cells in the ASIC chip design. The chip layout creation step 3 is a step of reading the layout information 1 and the primitive layout 2 and outputting the chip layout 4. In addition, an expected generation area extraction step 5
Is a step of extracting a dummy layer included in the primitive layout 2 and generating a generation scheduled layer 6 corresponding to each of the dummy layers in the N well and the P well. The well contact and sub-contact occurrence condition 7 is defined as
Are conditions for determining whether or not it is possible to generate the well contact and the sub contact 11 in advance. For example, such a condition is defined as the width of the layer 6 to be generated. In addition, the width is limited due to the process limitation, the well contact and the sub contact 1
The width is set to the minimum necessary for arranging 1. The width is the width of the Pch transistor diffusion layer 43, the Nch transistor diffusion layer 44, and the width of the layer 6 to be generated in the direction set by the primitive cell frame 14. However, since the dummy layer included in the primitive layout 2 of the present invention has a height capable of generating the well contact and the sub contact 11, only the width can be used as a criterion. The well contact and sub contact generation step 8 is a step of converting a layer to be generated that satisfies the well contact and sub contact generation condition 7 into a well contact layer and a sub contact layer 9. For example, the well contact and sub-contact generation condition 7 is satisfied as the width of the Pch transistor diffusion layer 43 and the Nch transistor diffusion layer 44 of the layer 6 to be generated and the width of the layer 6 to be generated in the direction set by the primitive cell frame 14. The layer 6 is determined to be a layer 6 which is to be generated and a layer 6 which is not to be generated.
This is the output step. Next, a contact hole generating step 10 in which a contact hole is generated in the well contact layer and the sub contact layer 9 to supply VDD and GND will be described. A contact hole is formed below the VDD supply line and the GND supply line at the center of the well contact layer and the sub contact layer 9 in the lateral direction. Thereby, a well contact and a sub contact 11 are generated. Next, in the merge processing step 12, the chip layout 4
And the well contact and the sub contact 11 are merged to create an actual chip layout 13. The method of generating well contacts and sub-contacts at the time of automatic placement according to the present invention has the above configuration.

Next, the operation according to the well contact and sub-contact generation method at the time of automatic arrangement according to the present invention having the above configuration will be described in more detail with reference to the drawings. 1 and 2, the layout information 1 and the primitive layout 2 obtained in the automatic layout step 31 are input to a chip layout creation step 3. In the chip layout creating step, the primitive layout 2 is arranged on the chip along the arrangement coordinates, direction, and the like of each primitive cell included in the input arrangement information 1, and the chip layout 4 is created.

FIG. 3 is a layout diagram showing an example of the chip layout 4. The layout coordinates and direction of each primitive layout 2 having various circuit functions such as inverters constituting the chip layout 4 are determined by the layout information 1. Further, the dummy layer 22 in the N well included in each primitive layout 2 is, for example, an a layer. Also, the dummy layer 2 formed in the P well
3 is a layer b.

The chip layout 4 is input to a scheduled generation area extraction step 5. The generation-target-region extracting step 5 includes the dummy layers 22 and 2 included in the input chip layout 4.
An OR process is performed on the three dummy layers, and two adjacent dummy layers are set as one generation scheduled area 6 (reference numeral in FIG. 2). At this time, when there is no adjacent dummy layer, the dummy layer is used as the expected generation area 6 as it is.

FIG. 4 is a diagram showing the expected generation area 6 as an output result of the expected generation area extraction step 5 with the chip layout 4 shown in FIG. 3 as an input. It has a region 24 to be generated in an N-well (not shown). Further, in the expected generation region 25 in the N well, a part of the dummy layers 22 and 23 is in contact between the adjacent primitive cells, and becomes one expected generation region 25 by OR processing. At this time, the scheduled occurrence area 24 and the scheduled occurrence area 25
Are both a layers. Further, it has a region 26 to be generated in a P-well (not shown). Also, in the region 27 to be generated in the P well, part of the dummy layer 23 is in contact between adjacent primitive cells, and
One occurrence scheduled area 27 is obtained by the R processing. At this time, the scheduled generation area 26 and the scheduled generation area 27 remain in the b layer.

The area 6 to be generated and the well contact and sub contact generation condition 7 are input to a well contact layer and sub contact layer generation step 8. The well contact and subcontact occurrence condition 7 defines the width of the region 6 to be generated. Further, it is determined whether or not each of the expected regions 6 satisfies the width, and the suffice is output as the well contact layer and the sub contact layer 9. The determination method is performed using a tool or a method equivalent to checking whether the layout satisfies the design criteria. By outputting the check result as a layout in the layers used in the well contact layer and the sub contact layer 9,
Those that satisfy the design criteria are output as well contact layers and sub-contact layers 9. At this time, the generation regions in the N well and the planned generation regions 24, 2 in the P well
Layers 5, 26, and 27 having different properties from the layers used in the actual layout are assigned.

FIG. 5 is a diagram showing the well contact layer and the sub-contact layer 9 output by the well contact layer and the sub-contact layer generating step 8 by using the region to be generated 6 shown in FIG. 4 as an input. Here, for example, N
Well contact layer and sub-contact layer 2 in well
Reference numeral 8 denotes a c layer, and the well contact layer in the P well and the sub contact layer 29 become a d layer.

The well contact layer and the sub contact layer 9 are inputted to the contact hole generating step 10 and the contact hole is located at the center of the well contact layer and the sub contact layer in the horizontal direction and at the coordinates below the VDD / GND supply wiring. Generate. As a result, a well contact and a sub contact have been generated.

FIG. 6 is a diagram in which a contact hole is formed on the well contact layer and the sub contact layers 28 and 29 shown in FIG. Also, the contact hole 30
It is located below the DD supply wiring 15 and the GND supply wiring 16, and further includes each well contact layer and sub contact layer 2.
8 and 29 are arranged at the center in the horizontal direction.

Next, the well contacts and sub-contacts 11 and the chip layout 4 are input to the merge processing 12, and an actual chip layout 13 in which the well contacts and the sub-contacts 11 are merged into the chip layout 4 is output.

According to the well contact and sub contact generation method at the time of automatic arrangement described above, the dummy layer 1
By arranging 9, 20, and 21 in a primitive layout, well contacts and sub-contacts can be generated only by simple graphic processing without performing a process such as the potential tracking step 37 in the conventional example. That is,
The processing time can be reduced, and the cost can be further reduced. Further, since only two data layers are required in the first embodiment, the processing time is reduced by reducing the data to be handled. The two layers used in the first embodiment are for identifying the inside of the N well and the inside of the P well.

Second Embodiment Next, a computer-readable recording medium on which a program for causing a computer to execute the primitive layout, the well contact and the sub contact generation method, and the well contact and the sub contact generation method according to the first embodiment described above. A second embodiment of the present invention, which is different from the first embodiment, will be described with reference to the drawings. Referring to FIG. 7, the second embodiment of the present invention is different from the first embodiment in that a primitive layout 32 has a data configuration, a well contact and sub-contact essential condition 33, and an essential condition determination step. This is different from a computer-readable recording medium that records a well contact and sub-contact generation method, and a program for causing a computer to execute the well contact and sub-contact generation method. The well contact and sub-contact essential condition 33 defines the required number of well contacts and sub-contacts to be arranged in a chip. For example, it is stipulated that one well contact and a sub contact (not shown) are always arranged within 20 μm. In addition, the essential condition determination step 34 receives the well contact layer and the sub contact layer 9 and the well contact and the sub contact essential condition 33 as inputs, and determines whether the well contact layer and the sub contact layer 9 are present at necessary intervals in the chip. This is the step of determining. If it does not exist at the required interval, the process returns to the automatic arrangement step 31 to perform rearrangement. If it exists at the required interval, the process proceeds to the contact hole generating step 10.

FIG. 8 shows a primitive layout 3
2 is a layout diagram of FIG. Embodiment 1 shown in FIG.
In the primitive layout, a dummy layer is also arranged between a diffusion layer of a transistor at both ends of the primitive and a primitive cell frame. Embodiment 2 of the present invention
The difference lies in that a dummy layer covers the well contact and the sub contact 30 in the primitive layout. The dummy layer to be overlaid is a layer having the same properties as the dummy layer disposed between the diffusion layer of the transistor at both ends of the primitive cell and the primitive cell frame. .

Next, regarding the operation of the second embodiment of the present invention,
This will be described with reference to FIGS. The dummy layers 19 and 20 included in the primitive layout 32 include Pch transistor diffusion layers 43 and N at both ends of the primitive cell.
It is arranged between the channel transistor diffusion layer 44 and the primitive cell frame. Furthermore, primitive layout 3
A dummy layer 35 is disposed on the well contact and the sub contact 45 in the second layer 2. The dummy layer 35 on the well contact and the sub-contact 45 in the primitive layout is used in the steps from the chip layout creation step 4 to the generation of the well contact layer and the sub-contact layer 9 (the positions in FIG. 8 are 19, 20, and 35). Then, the same processing as that for the dummy layers 19 and 20 between the diffusion layers of the transistors at both ends of the primitive cell and the primitive cell frame is performed to generate the well contact layer and the sub contact layer 9. The well contact layer and the sub contact layer 9 corresponding to the dummy layer 35 on the well contact and the sub contact 45 have the same data as the well contact and the sub contact 45 in the primitive layout. That is, the place where the dummy layer 35 is arranged is a place where the well contact and the sub contact can be already generated. Therefore, the dummy layer 35 is arranged on the well contact and the sub contact 45,
When the processing is sequentially performed, the well contact layer and the sub contact layer 9 always have the same shape as the dummy layers 19 and 20. In an actual manufacturing stage (not shown), the well contact and sub-contact 45 and the well contact layer and sub-contact layer 9 in the primitive layout have the same layer, and therefore have the same data. Also, no layout problem occurs for the above reasons.

The well contact layer and the sub contact layer 9 have data of all the well contacts and the sub contacts 45 generated in the chip (the area where the primitive cells are arranged). That is, only the well contact and the sub contact 45 in the region where the primitive cell is arranged correspond to the well contact and the sub contact 45 arranged in the primitive layout and the newly generated well contact layer and the sub contact layer 9. Becomes Here, the well contact and the sub contact 45 arranged in the primitive layout correspond to the well contact layer and the sub contact layer 9.
Contains the same data. Therefore, the well contact layer and the sub-contact layer 9 and the well contact and the sub-contact essential condition 33 are input, and if there is an interval equal to or longer than the distance given by the essential condition 33, the process proceeds to the automatic arrangement step 31. Is repeated until there are no more errors.

The second embodiment of the present invention described above is
As in the first embodiment of the present invention, well contacts and sub-contacts (not shown) can be generated only by graphic processing without performing processing such as the potential tracking step 37 in the conventional example. Therefore, the processing time can be reduced, and the cost can be further reduced. Further, unlike the second embodiment of the present invention, the presence or absence of the well contact and the sub contact can be checked at a necessary interval on the chip.
As a result, the size of the dummy layers 19, 20, 21, and 35 included in the primitive layout, that is, the size of the well contact and sub contact regions, the number of well contacts and sub contacts already existing in the primitive cell, and the number of The required number of well contacts and sub-contacts to be arranged can be expected to be sufficient due to the prescribed relationship. That is, by checking whether the well contact and the sub-contact exist at necessary intervals on the chip, it is possible to improve the reliability of the stability of the substrate potential and the suppression of the latch-up.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing a primitive layout according to a first embodiment;

FIG. 2 is a flowchart showing a well contact and subcontact generation method during automatic placement according to the first embodiment;

FIG. 3 is a layout diagram showing a chip layout according to the first embodiment;

FIG. 4 is a layout diagram showing only a scheduled occurrence area according to the first embodiment;

FIG. 5 is a layout diagram showing only a well contact layer and a sub contact layer according to the first embodiment;

FIG. 6 is a layout diagram showing only contact hole arrangement positions according to the first embodiment;

FIG. 7 is a flowchart of a well contact and subcontact generation method at the time of automatic arrangement according to the second embodiment;

FIG. 8 is a layout diagram of a primitive layout according to the second embodiment;

FIG. 9 is a layout diagram showing a conventional primitive layout.

FIG. 10 is a flowchart showing a conventional well contact and subcontact generation method at the time of automatic placement.

[Explanation of symbols]

1. 1. Placement information 2. Primitive layout 3. Chip layout creation process Chip layout5. 5. Expected region extraction step Scheduled occurrence area 7. 7. Conditions for occurrence of well contact and sub-contact 8. Step of generating well contact and sub-contact 9. Well contact layer and sub-contact layer Contact hole generation step 11. 11. Well contact and sub-contact Merge processing step 13. Actual chip layout 14. Primitive cell frame 15. VDD supply wiring 16. GND supply wiring 17. Source contact 18. Source contact 19. Dummy layer 20. Dummy layer 21. Dummy layer 22. Dummy layer 23. Dummy layer 23. Dummy layer 24. Dummy layer 25. Expected area 26. Scheduled occurrence area 27. Scheduled occurrence area 28. Well contact layer and sub-contact layer 29. Well contact layer and sub contact layer 30. Contact hole 31. Automatic placement process 32. Primitive layout 33. Well contact and sub contact essential conditions Essential condition determination step 35. Dummy layer 36. Primitive layout 37. Potential tracking step 38. Source / drain definition 39. Boundary occurrence condition 40. Well contact and sub-contact generation boundary creation step Occurrence boundary 42. Inter-boundary length measuring step 43. Pch transistor diffusion layer 44. Nch transistor diffusion layer 45. Well contact and sub-contact 46. Gate end 47. Gate wiring

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[Procedure amendment]

[Submission date] July 14, 1999 (1999.7.1)
4)

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

Patent application title: ASIC design method and primitive
Layout

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ASIC design method.
Method for generating well contacts and sub-contacts after automatic placement in an ASIC chip design , in particular, a primitive layout constituting an ASIC chip, and
The present invention relates to a computer-readable storage medium storing a program for causing a computer to execute an ASIC design method .

[0002]

2. Description of the Related Art Generally, a required number of well contacts and sub-contacts are arranged in a chip in order to stabilize a substrate potential and to prevent latch-up. On the other hand, when the well contact and the sub contact are arranged in the primitive layout, it is not necessary to have the well contact and the sub contact in every primitive layout. In addition, a brief description will be given of a conventional method of preventing an increase in cell size of a primitive layout and arranging a required number of cells in a chip. Such a method has no well contact and sub-contact in the primitive layout,
Insertion of well contacts and sub-contacts after the chip layout is created prevents an increase in chip size. If the increase in the cell size of the primitive layout does not directly affect the cell size, the primitive layout has well contacts and sub-contacts.

An example of the above-described prior art will be described with reference to the drawings. FIG. 9 is a plan view showing a conventional primitive layout. The arrangement area of the primitive layout 36 shown in FIG. 9 is determined by the primitive cell frame (peripheral portion) 14. In addition, the primitive layout 36 is installed so as to satisfy the circuit function of each primitive cell (since the shape and size of the primitive cell are determined by the primitive cell frame, no particular reference numerals are given). This is the layout of the transistors and wirings. Such transistors and wirings are arranged in a primitive cell frame so as to satisfy a criterion of an interval between adjacent data when the chip is arranged. Further, the primitive layout 36 has the VDD supply wiring 15 and the GND supply wiring 16. Further, the source contact 17 for supplying VDD to the Pch transistor diffusion layer 43 and the Nch transistor diffusion layer 4
4 had a source contact 18 for supplying GND.

FIG. 9 shows a conventional ASIC design method .
This will be described with reference to FIG. FIG. 10 shows a conventional ASI.
6 is a flowchart of a method for designing C. The arrangement information 1 is
This is information on primitive cells obtained by the automatic placement step 31 in the ASIC chip design. The chip layout creating step 3 is a step of reading the layout information 1 and the primitive layout 36 and outputting the chip layout 4. The potential tracking step 37 is performed in the chip layout 4
And detecting whether the diffusion layers (not shown) at both ends of each primitive layout 36 are the source or the drain. Next, from the diffusion layers at both ends of each primitive layout 36, if the potential supplied to the diffusion layers is VDD or GND, it is determined as a source, and if it is a normal signal, it is determined as a drain. The determined result is the shape of the diffusion layers at both ends, as different layers in the source / drain, and as different layers in the N well (not shown) and the P well (not shown), for a total of four types of layers. Source / drain definition 3
8 had been output. The boundary generation condition 39 defines the distance between the source diffusion layer and the well contact and the sub-contact, and the distance between the drain diffusion layer and the well contact and the sub-contact. For example, the distance between the source diffusion layer and the well contact and the sub-contact is 0 μm, and the distance between the drain diffusion layer and the well contact and the sub-contact is 0.3 μm. The well contact and sub-contact generation boundary creation step 40 receives the source / drain definition 38 and the boundary generation condition 39 as inputs and places the well contact and sub-contact at a position defined by the boundary generation condition 39 from each source / drain definition 38. A contact generation boundary 41 is created. The well contact / subcontact generation boundary 41 has a width in the extension direction of the primitive cell frame 14 in which the well contact and the subcontact can be generated. Further, the well contact and sub contact generation condition 7 defines a distance in which a well contact and a sub contact can be generated between adjacent generation boundaries 41. The boundary-to-boundary length measuring step 42 includes the generation boundary 41
And the well contact and subcontact generation condition 7 are input, the distance between the adjacent well contact and subcontact generation boundary 41 is measured, and the well contact and subcontact layer 9 is generated. The well contact and sub-contact layer 9 can be assigned different layers in the N well and the P well. Subsequent steps are the same as in the first embodiment of the present invention, and a description thereof will be omitted.

[0005]

However, even the above-described prior art well contact and subcontact insertion methods have the following further problems. There are many processing steps such as the potential tracking step 37, and the processing time required for one processing is long. This is because the number of primitive cells and the number of transistors used are large in the current large-scale highly integrated chip. Furthermore, since at least four data layers are required, the processing time increases due to an increase in the amount of data to be handled. Potential tracking requires at least four layers of a P diffusion layer, an N diffusion layer, a contact, and a power supply wiring. If a power supply wiring uses an upper wiring layer, the number of necessary data layers increases. Also, the layers required to generate well contacts and sub-contacts are
The number of layers for recognizing the drain is increased by two, and a total of four layers are required.

The present invention has been made in view of the above-mentioned problems in the prior art, and simplifies a processing step by providing a dummy layer in a primitive cell in advance, reliably generates a well-con- Another object of the present invention is to improve performance and reduce costs by reducing the number of data layers.

[0007]

According to a first aspect of the present invention, there is provided an automatic arranging step of automatically arranging primitive cells, and a step of forming the primitive cells in a primitive cell so as to satisfy a circuit function of each primitive cell. A dummy layer is formed in a region defined by a peripheral portion of a primitive cell which is opposed to and adjacent to a diffusion layer of the transistor, and a primitive which is adjacent to the dummy layer. A chip for creating a chip layout using data of a primitive layout in which the width of the dummy layer in the extension direction of the peripheral portion of the cell is formed to a predetermined width and the arrangement information of the primitive cells obtained by the automatic arrangement step; Layout creation process,
Extract the dummy layer included in the primitive layout,
A generation contact layer extraction step for forming a generation contact layer, a well contact / subcontact generation contact area step for giving the well contact / subcontact occurrence condition to the generation contact layer, and a well contact from the well contact / subcontact occurrence condition. A step of generating a well contact and a sub contact, in which the generation scheduled layer determined to be possible is determined as a well contact layer and a sub contact layer, and a contact is made at a predetermined position of the well contact layer and the sub contact layer. A method for designing an ASIC, comprising: forming a hole and forming a contact hole for generating a well contact and a sub contact.

Therefore, according to the well contact and sub-contact generation method of the first invention of the present application, an automatic arrangement step for automatically arranging the primitive cells, and a method for arranging the primitive cells in the primitive cells so as to satisfy the circuit function of each primitive cell. This is a layout of the formed transistor and wiring, in which a dummy layer is formed in a region which is opposed to the diffusion layer of the transistor and which is set by the peripheral portion of the primitive cell which is close to the transistor, and which is close to the dummy layer. A chip layout is created using data of a primitive layout in which the width of the dummy layer in the extension direction of the peripheral portion of the primitive cell is formed to a predetermined width and the arrangement information of the primitive cell obtained by the automatic arrangement step. Chip layout creation process and damage included in primitive layout Extracting a layer to form a layer to be generated; extracting a layer to be generated; forming a well contact and a sub-contact in the generated layer; From the conditions, it is determined whether or not a well contact and a sub contact occur,
A step of generating a well contact and a sub-contact using a layer to be generated determined to be possible as a well contact layer and a sub-contact layer, and forming a contact hole in a predetermined position of the well contact layer and the sub-contact layer; This is characterized in that the method comprises a step of forming a contact hole for generating the processing time, so that there is an advantage that the processing time and the processing step are reduced. Therefore, it is possible to improve productivity, improve workability, and further reduce costs.

Further, the second invention of the present application provides an automatic arrangement step of automatically arranging primitive cells, a transistor, a wiring, a well contact, and a well formed in the primitive cells so as to satisfy the circuit function of each primitive cell. A layout of sub-contacts, wherein a dummy layer is formed in a region defined by a peripheral portion of a primitive cell which is opposed to and adjacent to a diffusion layer of a transistor, and a peripheral portion of the primitive cell which is adjacent to the dummy layer. The width of the dummy layer in the extension direction of the portion is formed to a predetermined width,
Further, a primitive layout in which a dummy layer is formed on the upper layer of the well contact and the sub contact, and a chip layout creating step of creating a chip layout using data of the arrangement information of the primitive cells obtained by the automatic arrangement step, Extracting a dummy layer included in the primitive layout and forming a generation scheduled layer; forming a generation scheduled layer; a well contact and sub contact generation scheduled region step of giving the well contact and sub contact generation condition to the generation scheduled layer; From the well contact and sub-contact occurrence conditions, determine whether or not the well contact and sub-contact can be generated, and a well contact and sub-contact generation step of setting the generation scheduled layer determined to be possible as a well contact layer and a sub-contact layer, Provide the necessary conditions for the number of well contacts and sub-contacts to be arranged in a chip configured in a primitive layout, and provide the necessary conditions for well contacts and sub-contacts to determine whether the well contacts and sub-contact layers are present at necessary intervals in the chip. An ASIC design comprising: an essential condition determining step of determining; and a contact hole forming step of forming a contact hole at a predetermined position of a well contact and a sub contact layer to generate a well contact and a sub contact.
Is the way .

Therefore, the ASIC of the second invention of the present application
According to the design method , an automatic placement step for automatically placing primitive cells and a layout of transistors, wiring, well contacts, and sub-contacts formed in the primitive cells so as to satisfy the circuit function of each primitive cell. Forming a dummy layer in a region defined by a peripheral edge of a primitive cell which is opposed to and adjacent to a diffusion layer of a transistor, and a dummy extending in a direction of extension of a peripheral edge of the primitive cell which is adjacent to the dummy layer. The width of the layer is formed to a predetermined width, further using a primitive layout in which a dummy layer is formed on the upper layer of the well contact and the sub contact, and the data of the arrangement information of the primitive cell obtained by the automatic arrangement step, The chip layout creation process for creating the chip layout, and the Extracting a dummy layer included in the blankout and forming a generation scheduled layer; forming a generation scheduled layer; a well contact and sub contact generation scheduled region step of giving the well contact and sub contact generation conditions to the generation scheduled layer; A step of generating a well contact and a sub-contact by determining whether or not a well contact and a sub-contact can be generated based on conditions for generating the well contact and the sub-contact; And the necessary conditions for defining the required number of well contacts and sub-contacts to be arranged in a chip are determined, and it is determined whether the well contact and the sub-contact layer are present at a necessary interval in the chip. Must Large-scale and high-integration because the method includes a condition determining step and a contact hole forming step of forming a contact hole at a predetermined position of a well contact and a sub contact layer to generate a well contact and a sub contact. Even in the case of a manufactured chip, there is an advantage that a well contact and a sub contact can be generated in the dummy layer in a short time by a simple method such as graphic processing. Further, the processing steps can be simplified. Further, the number of required data layers is smaller than that of the conventional one, and the amount of data to be handled is reduced, so that there is an advantage that the processing time is shortened. Therefore, it is possible to improve productivity, improve workability, and further reduce costs.

Further, in the third invention of the present application, the well contact and the sub contact generation condition may be such that a dummy layer set by a distance between a peripheral edge of a primitive cell facing a diffusion layer of the transistor and a diffusion layer of the transistor. It is characterized in that the propriety is determined only by the width.

Therefore, the ASIC of the third invention of the present application
According to the design method , the condition for generating the well contact and the sub contact is determined only by the width of the dummy layer set by the distance between the peripheral edge of the primitive cell facing the diffusion layer of the transistor and the diffusion layer of the transistor. Therefore, when forming a contact, the step of determining the width of the dummy layer in the extension direction of the peripheral portion of the primitive cell facing the diffusion layer of the transistor capable of forming the contact is omitted, There is an advantage that it is possible to determine whether or not a well contact and a sub contact can be generated by only simple graphic processing. That is,
There is an advantage that simplification of processing steps and reduction of cost can be realized.

The fourth invention of the present application is characterized in that the predetermined position in the contact hole forming step is near the center of the well contact and the sub contact layer.

Therefore, the ASIC of the fourth invention of the present application
According to the design method , the predetermined position in the contact hole forming step can be set near the center of the well contact and the sub-contact layer, so that the well contact and the sub-contact capable of performing a desired function can be reliably generated. There are advantages that can be.

In a fifth aspect of the present invention, in a primitive layout including a transistor and a wiring, a peripheral portion of the primitive cell opposed to a diffusion layer of the transistor provided in the primitive cell in which the primitive layout is configured; A primitive layout comprising a dummy layer disposed in a region formed by a diffusion layer of a transistor.

[0016] Therefore, the primitive of the fifth invention of the present application.
According to I Bed layout, the transistor and primitive layout made up of primitive cell including the wiring, the predetermined position where the dummy layer in the primitive cell in the automatic placement process is placed, the transistors provided in the primitive cell Since it is characterized by being arranged in a region formed by a part of the peripheral portion of the primitive cell facing the diffusion layer and the diffusion layer of the transistor, the dummy layer can be provided in a short time by a simple method. There is an advantage that a well contact and a sub contact can be reliably generated.

The sixth invention of the present application is characterized in that the width of the dummy layer in the extension direction of the peripheral portion of the primitive cell adjacent to the dummy layer is formed to a predetermined width.

Therefore, the primitive of the sixth invention of the present application.
According to the active layout , the width of the dummy layer in the extension direction of the peripheral portion of the primitive cell adjacent to the dummy layer is formed to a predetermined width. There is an advantage that a contact can be generated. That is, there is an advantage that simplification of a processing step and reduction of cost can be realized.

Further, the seventh invention of the present application is directed to an automatic arranging step of automatically arranging primitive cells, and a layout of transistors and wirings formed in the primitive cells so as to satisfy the circuit functions of each primitive cell. A dummy layer is formed in a region defined by a peripheral portion of a primitive cell which is opposed to and adjacent to a diffusion layer of a transistor, and a dummy in an extension direction of a peripheral portion of the primitive cell which is adjacent to the dummy layer. A chip layout creating step of creating a chip layout by using data of a primitive layout having a layer width formed to a predetermined width and arrangement information of primitive cells obtained by the automatic arrangement step; A generation layer extraction step of extracting a dummy layer to be generated and generating a generation layer, From the well contact and sub contact generation region step of providing a well contact and sub contact generation condition to the planned layer and the well contact and sub contact generation condition, it is determined whether the well contact and the sub contact can be generated, and it is determined that the generation is possible. Forming a well contact and a sub contact layer using the layer to be generated as a well contact and a sub contact layer; and forming a contact hole at a predetermined position of the well contact layer and the sub contact layer to generate a well contact and a sub contact. Forming step;
A ASIC design method comprising: inputting a well contact and a sub contact and a chip layout; and outputting a real chip layout in a state where the well contact and the sub contact are merged into the chip layout. It is a computer-readable storage medium that stores a program to be executed.

Therefore, the ASIC of the seventh invention of the present application
According to a computer-readable storage medium recording a program for causing a computer to execute the design method of
An automatic placement step for automatic placement of primitive cells, and a layout of transistors and wiring formed in the primitive cells so as to satisfy the circuit function of each primitive cell. A dummy layer is formed in a region defined by the peripheral portion of the primitive cell, and the width of the dummy layer in the extension direction of the peripheral portion of the primitive cell adjacent to the dummy layer is formed to a predetermined width. A chip layout creation step of creating a chip layout using data of the layout and the arrangement information of the primitive cells obtained by the automatic arrangement step, and a dummy layer included in the primitive layout is extracted to generate a layer to be generated Planned layer extraction process, well contact and sub- A well contact and sub contact generation scheduled region step for giving a tact generation condition; and determining whether or not a well contact and a sub contact can be generated based on the well contact and sub contact generation conditions. A step of generating a well contact and a sub contact as a sub contact layer, a step of forming a contact hole at a predetermined position of the well contact layer and the sub contact layer, and a step of forming a well contact and a sub contact; And a merge processing step of inputting a contact and a chip layout and outputting an actual chip layout in a state where the well contact and the sub-contact are merged into the chip layout. A computer that operates by reading a recording medium on which such a procedure is recorded, and that operates based on the algorithm of each process, can be used for simple processing such as graphic processing even for a large-scale highly integrated chip. There is an advantage that the well contact and the sub contact can be generated in a short time by the method. Further, the number of required data layers is smaller than that of the conventional one, and the amount of data to be handled is reduced, so that there is an advantage that the processing time is shortened. Therefore, it is possible to improve productivity, improve workability, and further reduce costs.

According to an eighth aspect of the present invention, there is provided an automatic arranging step for automatically arranging primitive cells, a transistor, a wiring, a well contact, and a well formed in the primitive cells so as to satisfy the circuit function of each primitive cell. A layout of sub-contacts, wherein a dummy layer is formed in a region defined by a peripheral portion of a primitive cell which is opposed to and adjacent to a diffusion layer of a transistor, and a peripheral portion of the primitive cell which is adjacent to the dummy layer. The width of the dummy layer in the extension direction of the portion is formed to a predetermined width,
Further, a primitive layout in which a dummy layer is formed on the upper layer of the well contact and the sub contact, and a chip layout creating step of creating a chip layout using data of the arrangement information of the primitive cells obtained by the automatic arrangement step, A generation layer extraction step of extracting a dummy layer included in the primitive layout and forming a generation layer, a well contact and sub contact generation area step of providing a well contact and a sub contact generation condition to the generation layer, and the well A step of generating a well contact and a sub-contact by determining whether or not a well contact and a sub-contact can be generated based on the contact and sub-contact generation conditions; A well contact and a sub-contact essential condition for defining a required number of well contacts and sub-contacts to be arranged in a chip configured in the active layout; and the well contact and the sub contact essential condition. A contact hole forming step of forming a contact hole at a predetermined position of a well contact and a sub contact layer to generate a well contact and a sub contact, and a well contact; as input sub contact and chip layout, co the ASIC design method characterized by comprising the merge processing step of outputting an actual chip layout of the state where the well contact and sub-contact is merged with the chip layout A computer-readable recording medium recording a program to be executed by computer.

Therefore, the ASIC of the eighth invention of the present application
According to a computer-readable recording medium recording a program for causing a computer to execute the design method of
An automatic layout process for automatically arranging primitive cells and a layout of transistors, wiring, well contacts and sub-contacts formed in the primitive cells so as to satisfy the circuit function of each primitive cell. And forming a dummy layer in a region defined by the peripheral edge of the primitive cell adjacent thereto and a predetermined width of the dummy layer in the extension direction of the peripheral edge of the primitive cell adjacent to the dummy layer. And a chip layout using a data of a primitive layout in which a dummy layer is formed on a well contact and a sub contact, and placement information of a primitive cell obtained by the automatic placement step. Creation process and included in primitive layout An extraction layer for extracting a dummy layer to be formed and a generation layer to be formed, a well contact and sub contact generation area step for giving a well contact and a sub contact generation condition to the generation layer, and the well contact and the sub contact From the occurrence conditions,
It is determined whether or not a well contact and a sub-contact can be generated, and the well contact and the sub-contact generation process is performed using the layer determined to be possible as the well contact layer and the sub-contact layer. The well contact and sub contact essential conditions that define the required number of well contacts and sub contacts, and the well contact and sub contact essential conditions are given, and it is determined whether the well contact and the sub contact layer exist at a necessary interval in the chip. An essential condition determining step; a contact hole forming step of forming a contact hole at a predetermined position of the well contact and the sub contact layer to generate a well contact and a sub contact; and a well contact, a sub contact, and a chip layout It was an input, characterized by comprising the merged process of outputting the actual chip layout of the state where the well contact and sub-contact is merged with the chip layout. A device that operates based on the algorithm of each process by a computer that reads and operates a recording medium on which such a procedure is recorded can be operated by a simple method such as graphic processing, even for a large-scale highly integrated chip. There is an advantage that a well contact and a sub contact can be generated in a short time. Further, the number of required data layers is smaller than that of the conventional one, and the amount of data to be handled is reduced, so that there is an advantage that the processing time is shortened. Therefore, it is possible to improve productivity, improve workability, and further reduce costs.

In the ninth invention of the present application, the well contact and sub-contact generation conditions are such that the width of the dummy layer is set by the distance between the periphery of the primitive cell facing the diffusion layer of the transistor and the diffusion layer of the transistor. It is characterized in that the determination is made only by using the information.

Therefore, the ASIC of the ninth invention of the present application
According to a computer-readable recording medium recording a program for causing a computer to execute the design method of
Whether the well contact and the sub contact are generated is determined based on the width of the dummy layer set by the distance between the peripheral edge of the primitive cell facing the diffusion layer of the transistor and the diffusion layer of the transistor. An apparatus that operates based on the algorithm of each step by a computer that reads and operates a recording medium on which such a procedure is recorded is a dummy in the peripheral direction of a primitive cell in which a contact can be formed when a contact is formed. It is not necessary to determine the width of the layer, and there is an advantage that well contacts and sub-contacts can be generated only by graphic processing. That is, there is an advantage that simplification of a processing step and reduction of cost can be realized.

The tenth invention of the present application is characterized in that the predetermined position in the contact hole forming step is near the center of the well contact and the sub contact layer.

Therefore, the ASI of the tenth invention of the present application
According to a computer-readable recording medium on which a program for causing a computer to execute the design method of C is recorded, a predetermined position in the contact hole forming step is near the center of the well contact and the sub-contact layer. An apparatus that operates based on the algorithm of each process by a computer that reads and operates a recording medium on which such a procedure is recorded has an advantage that a well contact and a subcontact can be reliably generated.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION An AS according to an embodiment of the present invention will be described below.
An IC design method and a primitive layout will be described with reference to the drawings.

Embodiment 1 FIG. 1 is a layout diagram showing a primitive layout according to Embodiment 1 of the present invention. FIG. 2 is a flowchart of the ASIC design method according to the first embodiment of the present invention. FIG. 2 shows the configuration of the ASIC according to the first embodiment of the present invention.
Before describing the measurement method , a primitive layout 2 as a component thereof will be described with reference to FIG. In FIG. 1, a primitive layout 2 according to the first embodiment of the present invention
Is a layout of transistors and wiring arranged so as to satisfy the circuit function of each primitive cell on the chip layout 4. The laid-out transistors and wirings are arranged in the primitive cell frame 14 so as to satisfy the standard of the interval between adjacent data when arranging the chip. The primitive layout 2 includes the primitive cell frame 14 facing the Pch transistor diffusion layer 43 or the Nch transistor diffusion layer 44 provided in the primitive cell, the Pch transistor diffusion layer 43 and the Nc
The dummy layer 1 for generating a well contact and a sub contact is formed in a region formed with the h transistor diffusion layer 44.
9, 20, and 21. Also, primitive cell frame 1
Reference numeral 4 designates an area of a primitive cell.
The primitive layout 2 is configured inside the primitive cell frame 14. That is, the primitive cell frame 14 has a standardized size, and each element such as a transistor is configured inside the primitive cell frame 14. Further, the primitive layout 2 has a VDD supply line 15 and a GND supply line 16. Further, a source contact 17 for supplying VDD to the Pch transistor diffusion layer 43 and a source contact 18 for supplying GND to the Nch transistor diffusion layer 44 are provided. The dummy layer 19 for generating a well contact and a sub-contact in an N-well (not shown) is arranged between the end of the Pch transistor diffusion layer 43 serving as a source and the primitive cell frame 14. . Further, the dummy layer 19 is formed in a region which is opposed to the diffusion layer of the transistor and is set by the peripheral portion of the primitive cell adjacent thereto, and a primitive cell frame which is adjacent to the dummy layer. 14 is formed to have a predetermined width (hereinafter, height). Also,
The height is formed to a width that can generate a well contact and a sub contact. The dummy layer 20 for generating a well contact and a sub contact formed in a P well (not shown) is disposed between the end of the Nch transistor diffusion layer 44 serving as a source and the primitive cell frame 14. Have been. Such a dummy layer 2
Numeral 0 is formed at a height at which well contacts and sub-contacts can be generated similarly to the dummy layer 19.
The height at which the well contact and the sub contact described above can be generated differs depending on the type of the chip, and thus is not particularly defined. The well layer and the sub-contact generation dummy layer 21 in the P-well define the distance between the N-channel transistor diffusion layer 44 and the well contact and the sub-contact from the end of the N-channel transistor diffusion layer 44 serving as the drain. It is arranged between a position separated by a distance satisfying the design criteria and the primitive cell frame 14. Similarly, the dummy layer 21 is formed at a height at which a well contact and a sub contact can be generated. Also, the dummy layers 19 for generating the well contacts and sub-contacts in the N-well and the dummy layers 20 and 21 for generating the well contacts and sub-contacts in the P well have different properties from the layers used in the actual layout. You have assigned layers. A dummy layer is not arranged at the right end in the N well. However, if a distance satisfying a design standard defining the distance between the Nch transistor diffusion layer 43 and the well contact and the sub contact cannot be ensured, the dummy layer is not necessary. Good.

Next, a method of designing an ASIC according to the first embodiment of the present invention will be described with reference to FIG. Explained here
The dummy layer which is a component of the ASIC design method is shown in FIG.
Are the dummy layers 19, 20, and 21 shown in FIG. FIG.
Has a primitive layout 2 shown in FIG. 1 as a component thereof. The dummy layer is selected and converted into a different data layer as the process sequentially proceeds. In view of the above, the dummy layers in the description of FIG. 2 will be described without reference numerals in order to avoid confusion due to the reference numerals. The description of such a dummy layer will be made later with reference to another drawing.

With reference to FIG. 2, an ASIC design method will be described. In this paragraph, the configuration will be described first. The arrangement information 1 is information that can be obtained by the automatic arrangement 31 of the primitive cells in the ASIC chip design. The chip layout creation step 3 is a step of reading the layout information 1 and the primitive layout 2 and outputting the chip layout 4. In addition, the scheduled generation region extracting step 5 is a step of extracting a dummy layer included in the primitive layout 2 and generating a scheduled generation layer 6 corresponding to each of the dummy layers in the N well and the P well. Well contact and sub contact generation condition 7
Is a condition for determining whether or not the well contact and the sub contact 11 can be generated in the generation scheduled layer 6. For example, such a condition is defined as the width of the layer 6 to be generated. In addition, the width is set to a minimum width required for arranging the well contact and the sub-contact 11 due to process restrictions. The width is the same as that of the Pch transistor diffusion layer 43.
And the width of the Nch transistor diffusion layer 44 and the width of the layer 6 to be generated in the direction set by the primitive cell frame 14.
However, since the dummy layer included in the primitive layout 2 of the present invention has a height capable of generating the well contact and the sub contact 11, only the width can be used as a criterion. Also, the well contact and sub contact generation step 8 includes the generation scheduled layer 6
Well contact and sub-contact occurrence condition 7
This is a step of converting a material satisfying the above conditions into a well contact layer and a sub contact layer 9. For example, the Pch of the layer 6 where the well contact and subcontact
The width of the transistor diffusion layer 43, the Nch transistor diffusion layer 44, and the width of the generation scheduled layer 6 in the direction set by the primitive cell frame 14 satisfy the condition.
This is a step of discriminating between the occurrence scheduled layer 6 that does not satisfy the condition and converting and outputting the occurrence scheduled layer 6 satisfying the condition to the well contact layer and the sub contact layer 9. Next, a contact hole generating step 10 in which a contact hole is generated in the well contact layer and the sub contact layer 9 to supply VDD and GND will be described. A contact hole is formed below the VDD supply line and the GND supply line at the center of the well contact layer and the sub contact layer 9 in the lateral direction. Thereby, a well contact and a sub contact 11 are generated. Next, in a merge processing step 12, the chip layout 4 is merged with the well contacts and the sub-contacts 11 to create an actual chip layout 13.
The ASIC design method of the present invention has the above configuration.

Next, the ASIC according to the present invention having the above-described structure will be described.
The operation according to the design method will be described in more detail with reference to the drawings. 1 and 2, the arrangement information 1 and the primitive layout 2 obtained by the automatic arrangement step 31 are:
It is input to the chip layout creation step 3. In the chip layout creating step, the primitive layout 2 is arranged on the chip along the arrangement coordinates, direction, and the like of each primitive cell included in the input arrangement information 1, and the chip layout 4 is created.

FIG. 3 is a layout diagram showing an example of the chip layout 4. The layout coordinates and direction of each primitive layout 2 having various circuit functions such as inverters constituting the chip layout 4 are determined by the layout information 1. Further, the dummy layer 22 in the N well included in each primitive layout 2 is, for example, an a layer. Also, the dummy layer 2 formed in the P well
3 is a layer b.

The chip layout 4 is input to a scheduled generation area extraction step 5. The generation-target-region extracting step 5 includes the dummy layers 22 and 2 included in the input chip layout 4.
An OR process is performed on the three dummy layers, and two adjacent dummy layers are set as one generation scheduled area 6 (reference numeral in FIG. 2). At this time, when there is no adjacent dummy layer, the dummy layer is used as the expected generation area 6 as it is.

FIG. 4 is a diagram showing the expected generation area 6 as an output result of the expected generation area extraction step 5 with the chip layout 4 shown in FIG. 3 as an input. It has a region 24 to be generated in an N-well (not shown). Further, in the expected generation region 25 in the N well, a part of the dummy layers 22 and 23 is in contact between the adjacent primitive cells, and becomes one expected generation region 25 by OR processing. At this time, the scheduled occurrence area 24 and the scheduled occurrence area 25
Are both a layers. Further, it has a region 26 to be generated in a P-well (not shown). Also, in the region 27 to be generated in the P well, part of the dummy layer 23 is in contact between adjacent primitive cells, and
One occurrence scheduled area 27 is obtained by the R processing. At this time, the scheduled generation area 26 and the scheduled generation area 27 remain in the b layer.

The area 6 to be generated and the well contact and sub contact generation condition 7 are input to a well contact layer and sub contact layer generation step 8. The well contact and subcontact occurrence condition 7 defines the width of the region 6 to be generated. Further, it is determined whether or not each of the expected regions 6 satisfies the width, and the suffice is output as the well contact layer and the sub contact layer 9. The determination method is performed using a tool or a method equivalent to checking whether the layout satisfies the design criteria. By outputting the check result as a layout in the layers used in the well contact layer and the sub contact layer 9,
Those that satisfy the design criteria are output as well contact layers and sub-contact layers 9. At this time, the generation regions in the N well and the planned generation regions 24, 2 in the P well
Layers 5, 26, and 27 having different properties from the layers used in the actual layout are assigned.

FIG. 5 is a diagram showing the well contact layer and the sub-contact layer 9 output by the well contact layer and the sub-contact layer generating step 8 by using the region to be generated 6 shown in FIG. 4 as an input. Here, for example, N
Well contact layer and sub-contact layer 2 in well
Reference numeral 8 denotes a c layer, and the well contact layer in the P well and the sub contact layer 29 become a d layer.

The well contact layer and the sub contact layer 9 are inputted to the contact hole generating step 10 and the contact hole is located at the center of the well contact layer and the sub contact layer in the horizontal direction and at the coordinates below the VDD / GND supply wiring. Generate. As a result, a well contact and a sub contact have been generated.

FIG. 6 is a diagram in which a contact hole is formed on the well contact layer and the sub contact layers 28 and 29 shown in FIG. Also, the contact hole 30
It is located below the DD supply wiring 15 and the GND supply wiring 16, and further includes each well contact layer and sub contact layer 2.
8 and 29 are arranged at the center in the horizontal direction.

Next, the well contacts and sub-contacts 11 and the chip layout 4 are input to the merge processing 12, and an actual chip layout 13 in which the well contacts and the sub-contacts 11 are merged into the chip layout 4 is output.

According to the ASIC design method described above, by placing the dummy layers 19, 20, and 21 in a primitive layout, the processing such as the potential tracking step 37 in the conventional example is not performed, and only the simple graphic processing is performed. Well contacts and sub-contacts can be generated. That is, the processing time can be reduced, and the cost can be further reduced. Further, since only two data layers are required in the first embodiment, the processing time is reduced by reducing the data to be handled. The two layers used in the first embodiment are for identifying the inside of the N well and the inside of the P well.

Second Embodiment Next, the ASIC design method and the ASIC of the first embodiment are described.
Embodiment 2 of the present invention, which is different from the primitive layout , will be described with reference to the drawings. Referring to FIG. 7, the second embodiment of the present invention is different from the ASIC of the first embodiment in that it has a data configuration of a primitive layout 32, a well contact and sub-contact essential condition 33, and an essential condition determination step . Design method and primitive layer
Different from Uto . The well contact and sub-contact essential condition 33 defines the required number of well contacts and sub-contacts to be arranged in a chip. For example, it is stipulated that one well contact and a sub contact (not shown) are always arranged within 20 μm. In addition, the essential condition determination step 34 receives the well contact layer and the sub contact layer 9 and the well contact and the sub contact essential condition 33 as inputs, and determines whether the well contact layer and the sub contact layer 9 are present at necessary intervals in the chip. This is the step of determining. If it does not exist at the required interval, the process returns to the automatic arrangement step 31 to perform rearrangement. If it exists at the required interval, the process proceeds to the contact hole generating step 10.

FIG. 8 shows a primitive layout 3
2 is a layout diagram of FIG. Embodiment 1 shown in FIG.
In the primitive layout, a dummy layer is also arranged between a diffusion layer of a transistor at both ends of the primitive and a primitive cell frame. Embodiment 2 of the present invention
The difference lies in that a dummy layer covers the well contact and the sub contact 30 in the primitive layout. The dummy layer to be overlaid is a layer having the same properties as the dummy layer disposed between the diffusion layer of the transistor at both ends of the primitive cell and the primitive cell frame. .

Next, regarding the operation of the second embodiment of the present invention,
This will be described with reference to FIGS. The dummy layers 19 and 20 included in the primitive layout 32 include Pch transistor diffusion layers 43 and N at both ends of the primitive cell.
It is arranged between the channel transistor diffusion layer 44 and the primitive cell frame. Furthermore, primitive layout 3
A dummy layer 35 is disposed on the well contact and the sub contact 45 in the second layer 2. The dummy layer 35 on the well contact and the sub-contact 45 in the primitive layout is used in the steps from the chip layout creation step 4 to the generation of the well contact layer and the sub-contact layer 9 (the positions in FIG. 8 are 19, 20, and 35). Then, the same processing as that for the dummy layers 19 and 20 between the diffusion layers of the transistors at both ends of the primitive cell and the primitive cell frame is performed to generate the well contact layer and the sub contact layer 9. The well contact layer and the sub contact layer 9 corresponding to the dummy layer 35 on the well contact and the sub contact 45 have the same data as the well contact and the sub contact 45 in the primitive layout. That is, the place where the dummy layer 35 is arranged is a place where the well contact and the sub contact can be already generated. Therefore, the dummy layer 35 is arranged on the well contact and the sub contact 45,
When the processing is sequentially performed, the well contact layer and the sub contact layer 9 always have the same shape as the dummy layers 19 and 20. In an actual manufacturing stage (not shown), the well contact and sub-contact 45 and the well contact layer and sub-contact layer 9 in the primitive layout have the same layer, and therefore have the same data. Also, no layout problem occurs for the above reasons.

The well contact layer and the sub contact layer 9 have data of all the well contacts and the sub contacts 45 generated in the chip (the area where the primitive cells are arranged). That is, only the well contact and the sub contact 45 in the region where the primitive cell is arranged correspond to the well contact and the sub contact 45 arranged in the primitive layout and the newly generated well contact layer and the sub contact layer 9. Becomes Here, the well contact and the sub contact 45 arranged in the primitive layout correspond to the well contact layer and the sub contact layer 9.
Contains the same data. Therefore, the well contact layer and the sub-contact layer 9 and the well contact and the sub-contact essential condition 33 are input, and if there is an interval equal to or longer than the distance given by the essential condition 33, the process proceeds to the automatic arrangement step 31. Is repeated until there are no more errors.

The second embodiment of the present invention described above is
As in the first embodiment of the present invention, well contacts and sub-contacts (not shown) can be generated only by graphic processing without performing processing such as the potential tracking step 37 in the conventional example. Therefore, the processing time can be reduced, and the cost can be further reduced. Further, unlike the second embodiment of the present invention, the presence or absence of the well contact and the sub contact can be checked at a necessary interval on the chip.
As a result, the size of the dummy layers 19, 20, 21, and 35 included in the primitive layout, that is, the size of the well contact and sub contact regions, the number of well contacts and sub contacts already existing in the primitive cell, and the number of The required number of well contacts and sub-contacts to be arranged can be expected to be sufficient due to the prescribed relationship. That is, by checking whether the well contact and the sub-contact exist at necessary intervals on the chip, it is possible to improve the reliability of the stability of the substrate potential and the suppression of the latch-up.

[Brief description of the drawings]

FIG. 1 is a layout diagram showing a primitive layout according to a first embodiment;

FIG. 2 is a flowchart illustrating an ASIC design method according to the first embodiment;

FIG. 3 is a layout diagram showing a chip layout according to the first embodiment;

FIG. 4 is a layout diagram showing only a scheduled occurrence area according to the first embodiment;

FIG. 5 is a layout diagram showing only a well contact layer and a sub contact layer according to the first embodiment;

FIG. 6 is a layout diagram showing only contact hole arrangement positions according to the first embodiment;

FIG. 7 is a flowchart of an ASIC design method according to the second embodiment;

FIG. 8 is a layout diagram of a primitive layout according to the second embodiment;

FIG. 9 is a layout diagram showing a conventional primitive layout.

FIG. 10 is a flowchart showing a conventional ASIC design method.

[Explanation of Codes] 1. Placement information 2. Primitive layout 3. Chip layout creation process Chip layout5. 5. Expected region extraction step Scheduled occurrence area 7. 7. Conditions for occurrence of well contact and sub-contact 8. Step of generating well contact and sub-contact 9. Well contact layer and sub-contact layer Contact hole generation step 11. 11. Well contact and sub-contact Merge processing step 13. Actual chip layout 14. Primitive cell frame 15. VDD supply wiring 16. GND supply wiring 17. Source contact 18. Source contact 19. Dummy layer 20. Dummy layer 21. Dummy layer 22. Dummy layer 23. Dummy layer 23. Dummy layer 24. Dummy layer 25. Expected area 26. Scheduled occurrence area 27. Scheduled occurrence area 28. Well contact layer and sub-contact layer 29. Well contact layer and sub contact layer 30. Contact hole 31. Automatic placement process 32. Primitive layout 33. Well contact and sub contact essential conditions Essential condition determination step 35. Dummy layer 36. Primitive layout 37. Potential tracking step 38. Source / drain definition 39. Boundary occurrence condition 40. Well contact and sub-contact generation boundary creation step Occurrence boundary 42. Inter-boundary length measuring step 43. Pch transistor diffusion layer 44. Nch transistor diffusion layer 45. Well contact and sub-contact 46. Gate end 47. Gate wiring

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B046 AA08 BA04 5F064 BB35 CC12 DD02 DD12 DD14 EE02 EE26 EE27 EE52 HH06 HH11 HH12

Claims (10)

[Claims] 1. A layout of transistors and wirings formed in a primitive cell so as to satisfy a circuit function of each primitive cell, and an automatic placement step of automatically placing a primitive cell. A dummy layer is formed in a region defined by the peripheral edge of the primitive cell adjacent thereto, and the width of the dummy layer in the extension direction of the peripheral edge of the primitive cell adjacent to the dummy layer is set to a predetermined width. Using the data of the formed primitive layout and the placement information of the primitive cells obtained by the automatic placement step, a chip layout creation step of creating a chip layout, and extracting a dummy layer included in the primitive layout,
A generation scheduled layer extracting step of forming a generation scheduled layer, a well contact / sub contact generation scheduled area step of giving the well contact / sub contact generation condition to the generation scheduled layer, and a well contact based on the well contact / sub contact generation condition. A step of generating a well contact and a sub-contact, in which the generation scheduled layer determined to be possible is determined to be a well contact layer and a sub-contact layer, Forming a hole and generating a well contact and a sub-contact. A method for generating a well contact and a sub-contact, comprising: 2. An automatic arrangement step for automatically arranging primitive cells, and a layout of transistors, wirings, well contacts and sub-contacts formed in the primitive cells so as to satisfy the circuit function of each primitive cell,
A dummy layer is formed in a region defined by a peripheral portion of a primitive cell which is opposed to and adjacent to a diffusion layer of a transistor, and a dummy layer in an extension direction of a peripheral portion of the primitive cell which is adjacent to the dummy layer. The chip is formed by using data of a primitive layout in which a dummy layer is formed above the well contact and the sub contact, and a primitive cell arrangement information obtained by the automatic arrangement step. A chip layout creation process for creating a layout and a dummy layer included in a primitive layout are extracted,
A generation scheduled layer extraction step for forming a generation scheduled layer; a well contact and sub contact generation planned area step for providing the well contact and sub contact generation conditions to the generation planned layer; and a well contact based on the well contact and sub contact generation conditions. A step of generating a well contact and a sub contact, in which a generation scheduled layer determined to be possible is determined as a well contact layer and a sub contact layer, and a well contact arranged in a chip having a primitive layout An essential condition determining step of providing a well contact and a sub contact essential condition for defining a required number of sub contacts and a required number of sub contacts, and determining whether the well contact and the sub contact layer exist at a necessary interval in the chip; A contact hole forming step of forming a contact hole at a predetermined position of a contact layer and generating a well contact and a sub contact. 3. The condition for generating a well contact and a sub-contact is to judge whether or not the well contact and the sub-contact are generated only by a width of a dummy layer which is set by a distance between a peripheral portion of a primitive cell facing a diffusion layer of the transistor and a diffusion layer of the transistor. The method for generating a well contact and a sub-contact according to claim 1 or 2, wherein: 4. The well contact and subcontact generation method according to claim 1, wherein the predetermined position in the contact hole forming step is near the center of the well contact and subcontact layers. 5. A primitive layout including a transistor and a wiring, comprising: a peripheral portion of a primitive cell opposed to a diffusion layer of a transistor provided in a primitive cell in which the primitive layout is formed; and a diffusion layer of the transistor. A primitive layout characterized by arranging a dummy layer in a region to be formed. 6. The primitive layout according to claim 5, wherein a width of the dummy layer in the extension direction of a peripheral portion of the primitive cell adjacent to the dummy layer is formed to a predetermined width. 7. An automatic arranging step for automatically arranging primitive cells, and a layout of transistors and wirings formed in the primitive cells so as to satisfy a circuit function of each primitive cell, wherein the layout is opposite to a diffusion layer of the transistor; A dummy layer is formed in a region set by the peripheral portion of the primitive cell adjacent thereto, and the width of the dummy layer in the extension direction of the peripheral portion of the primitive cell adjacent to the dummy layer is set to a predetermined width. Using the data of the formed primitive layout and the placement information of the primitive cells obtained by the automatic placement step, a chip layout creation step of creating a chip layout, and extracting a dummy layer included in the primitive layout,
A generation scheduled layer extraction step of generating a generation scheduled layer; a well contact and sub contact generation scheduled area step of providing a well contact and sub contact generation condition to the generation scheduled layer; and a well contact and a sub contact generation condition based on the well contact and sub contact generation conditions. A step of generating a well contact and a sub contact, in which the generation scheduled layer determined to be possible is determined as a well contact and a sub contact layer, and a contact hole is formed at a predetermined position of the well contact layer and the sub contact layer. A contact hole forming step of generating a well contact and a sub contact; and inputting the well contact, the sub contact, and the chip layout, and merging the well contact and the sub contact into the chip layout. A computer-readable storage medium storing a program for causing a computer to execute a well contact and sub-contact generation method, which comprises a merge processing step of outputting an actual chip layout. 8. An automatic arranging step for automatically arranging primitive cells, and a layout of transistors, wirings, well contacts and sub-contacts formed in the primitive cells so as to satisfy the circuit function of each primitive cell. A dummy layer is formed in a region which is opposed to the diffusion layer and is set by the periphery of the primitive cell adjacent thereto, and the dummy layer in the extension direction of the periphery of the primitive cell adjacent to the dummy layer is formed. A chip layout is formed by using data of a primitive layout in which a width is formed to a predetermined width and a dummy layer is formed on a well contact and a sub contact, and arrangement information of primitive cells obtained by the automatic arrangement step. Chip layout creation process to create Extract the dummy layer included in the out,
A generation scheduled layer extracting step of forming a generation scheduled layer; a well contact / sub contact generation scheduled area step of providing a well contact / sub contact generation condition to the generation scheduled layer; and a well contact and a sub contact generation condition; A step of determining whether or not sub-contact can be generated; a step of generating a well-contact and a sub-contact having a layer to be generated determined to be possible as a well contact layer and a sub-contact layer; Given the well contact and sub contact essential conditions that define the required number of sub contacts, and the well contact and sub contact essential conditions, it is determined whether the well contacts and sub contact layers are present at the required intervals in the chip. A contact hole forming step of forming a contact hole at a predetermined position of a well contact and a sub contact layer, and generating a well contact and a sub contact; And a merge processing step of outputting a real chip layout in a state in which the well contacts and sub-contacts are merged into the layout. A computer-readable recording program for causing a computer to execute a well contact and sub-contact generation method. recoding media. 9. A condition for generating a well contact and a sub-contact is to determine whether or not the well contact and the sub-contact can be determined only by a width of a dummy layer set by a distance between a peripheral portion of a primitive cell facing a diffusion layer of the transistor and a diffusion layer of the transistor. A computer-readable recording medium on which a program for causing a computer to execute the well contact and subcontact generation method according to claim 7 or 8 is recorded. 10. The method for generating a well contact and a sub-contact according to claim 7, wherein the predetermined position in the contact hole forming step is near the center of the well contact and the sub-contact layer. A computer-readable recording medium that stores a program to be executed by a computer.