JP2001016078A - Polycrystalline silicon circuit - Google Patents

Abstract

(57) Abstract: A polycrystalline silicon circuit having characteristics comparable to a single crystal silicon circuit is provided. A differential amplifier of a comparator circuit has n-type MOSFETs N1 and N2 that receive input signals, p-type MOSFETs P1 and P2 of a current mirror circuit, and an n-type MOSFET N3 of a current source circuit. The output stage has a p-type MOSFET: P3 for transmitting a signal and an n-type MOSFET: N4 of the current source circuit. The differential amplifier further includes n-type MOSFETs: N5 and N6 connected in series to n-type MOSFETs: N1 and N2, respectively. The output stage further has an n-type MOSFET N7 connected in series with the n-type MOSFET N4. n-type MOSFET:
A voltage bias circuit is connected to the gates of N5, N6, and N7. The n-type MOSFETs N5, N6, and N7 suppress voltage fluctuations at points Xa, Xb, and OUT due to poor saturation characteristics of the main n-type MOSFETs N1, N2, and N4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a MIS (Metal Insulator Semiconductor) having a polycrystalline silicon layer as an active region.
r) Field effect transistors having a structure (including a metal oxide semiconductor (MOS) structure), that is, a polycrystalline silicon circuit for compensating for a poor saturation characteristic of a MISFET, and particularly, an input / output characteristic of a comparator circuit and a logic gate circuit. Technology for improving.

[0002]

2. Description of the Related Art As a technique for increasing the degree of integration of a semiconductor device and providing a protection circuit on the same chip as a power element, polycrystalline silicon is formed on a single-crystal silicon substrate layer for forming a power element through an insulating film. Forming a semiconductor layer, and using the semiconductor layer as an active region.
A method of forming such as has been studied. According to this method, the cost can be significantly reduced as compared with a method in which an element is formed using a single crystal SOI (Silicon On Insulator) or the like. In this specification, a semiconductor element having a polycrystalline silicon layer as an active region is referred to as a polycrystalline silicon semiconductor element.
For example, a semiconductor device having a single crystal silicon layer as an active region is referred to as a polycrystalline silicon MOSFET, and a single crystal silicon semiconductor device, for example, a single crystal silicon MOSFET.

By arranging a polycrystalline silicon MOSFET on the same chip as a power element, it is possible to reduce the chip area and cost. However, compared to a single-crystal silicon MOSFET,
SFETs, especially n-type MOSFETs, have poor saturation characteristics. Therefore, according to the study of the present inventors, the single crystal silicon M
When a comparator circuit or a logic gate circuit is configured similarly to the OSFET, there is a problem that input / output characteristics are poor and input / output gain is reduced.

FIG. 1 is a graph showing static characteristics of a polycrystalline silicon n-type MOSFET. FIG. 2 is a graph showing static characteristics of the polycrystalline silicon p-type MOSFET. In a MOSFET having good saturation characteristics formed using a single crystal silicon layer as an active region, the drain current approaches a constant current in a region where the drain voltage is high (several volts or more). On the other hand, the static characteristic of the polycrystalline silicon n-type MOSFET is a characteristic in which the drain current increases with the drain voltage,
There is almost no saturation characteristic. Polycrystalline silicon p-type MO
The static characteristics of the SFET are such that the drain current is close to a constant current when the drain voltage is 2 to 4 V.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in consideration of such circumstances, and has been made in consideration of the above circumstances.
By improving the saturation characteristics of T through circuit contrivance,
It is an object to provide a polycrystalline silicon circuit having characteristics comparable to a single crystal silicon circuit, for example, a comparator circuit and a CMOS logic gate circuit.

[0006]

SUMMARY OF THE INVENTION A first aspect of the present invention is as follows.
An n-type first MISFET having a polycrystalline silicon layer as an active region and connected between a node of a signal transmission line and a low potential source, between the node and the first MISFET. And a means for applying a bias voltage to a gate of the second MISFET, the n-type second MISFET having a polycrystalline silicon layer as an active region, and a means for applying a bias voltage to a gate of the second MISFET. A characteristic variation in voltage at the node is suppressed by the second MISFET.

According to a second aspect of the present invention, in the polycrystalline silicon circuit according to the first aspect, a means for applying a bias voltage to a gate of the first MISFET is further provided,
It is characterized by constituting a current source circuit.

According to a third aspect of the present invention, there is provided a polycrystalline silicon circuit according to the first aspect, wherein an n-type polycrystalline silicon layer connected as an active region to the low potential source in parallel with the first MISFET is used. A third MISFET and the third MISFET;
An n-type fourth MISFET having a polycrystalline silicon layer as an active region connected in series to a drain of the FET, and first and second inputs for inputting a differential signal to gates of the first and third MISFETs, respectively. Means and said fourth MISF
Means for applying a bias voltage to the gate of the ET;
And further comprising a differential amplifier.

According to a fourth aspect of the present invention, there is provided a polycrystalline silicon circuit according to the first aspect, wherein an n-type polycrystalline silicon layer connected to the low potential source in parallel with the first MISFET and having a polycrystalline silicon layer as an active region is used. A third MISFET and the third MISFET;
An n-type fourth MISFET having a polycrystalline silicon layer as an active region, connected in series to a drain of the FET, means for connecting a gate of the first MISFET to a gate and a drain of the third MISFET, and
Means for applying a bias voltage to the gate of the SFET, further comprising a current mirror circuit of the differential amplifier.

According to a fifth aspect of the present invention, there is provided a polycrystalline silicon circuit according to the first aspect, further comprising a p-type polycrystalline silicon layer connected between the node and a high potential source and having a polycrystalline silicon layer as an active region. A third MISFET and the first and third MISFETs
Input means for inputting a logic signal to the gate of the CMO, wherein a logic signal is output from the node.
It is characterized by forming an S logic gate circuit.

According to a sixth aspect of the present invention, in the polycrystalline silicon circuit according to the fifth aspect, the node and the third MIS are provided.
A p-type fourth MISFET having a polycrystalline silicon layer as an active region connected between the fourth MISFET and the fourth MISFET;
Means for applying a bias voltage to the gate of the ET;
And a voltage variation at the node due to a poor saturation characteristic of the third MISFET.
It is characterized by being suppressed by ISFET.

According to a seventh aspect of the present invention, in the polycrystalline silicon circuit according to any one of the first to sixth aspects, a polycrystalline silicon layer connected between the node and a high potential source is connected to an active region. A bias voltage is applied to a p-type main MISFET, a p-type sub-MISFET connected between the node and the main MISFET, the p-type sub-MISFET having a polycrystalline silicon layer as an active region, and a gate of the sub-MISFET. Means for suppressing the fluctuation of the voltage at the node due to the poor saturation characteristic of the main MISFET by the sub MISFET.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the course of developing the present invention, the present inventors have a problem that arises when the structure of a single-crystal silicon circuit is used as it is and a single-crystal silicon MOSFET is simply replaced with a polycrystalline silicon MOSFET. Was studied. As a result, the present inventors have obtained the following knowledge.

FIG. 3 is a circuit diagram showing a conventional comparator circuit on the assumption that a single-crystal silicon MOSFET is used. The n-type MOSFETs N1 and N2 and the p-type MOSFETs P1 and P2 have the same characteristics.

The comparator circuit shown in FIG. 3 operates as follows when it is composed of a single crystal silicon MOSFET having a good saturation characteristic. That is, an n-type MOSFET:
N1 and n-type MOSFET: Since the source of N2 is common, if N1 and N2 operate in the saturation region, IN1
> IN2, regardless of the source-drain voltage
A current of I1> I2 flows. p-type MOSFET: P1,
When the current I1 flows to the point Xa of the current mirror circuit of P2, the current I3 equal to the current I1 flows to the point Xb. Therefore, the current at the point Xb has a relationship of I3> I2, and the voltage at the point Xb increases. The rise of the voltage at the point Xb turns off the p-type MOSFET P3 in the output stage, and the OUT voltage falls. When IN1 <IN2, the operation is performed with the reverse voltage-current relationship as described above.

On the other hand, when each of the n-type MOSFETs of the comparator circuit shown in FIG. 3 is composed of a polycrystalline silicon n-type MOSFET having a poor saturation characteristic, this comparator circuit causes the following problem, Decrease the output gain. That is, when the polycrystalline silicon n-type MOSFET is used, the currents I1, I2, and I3 change depending on the source-drain voltage. For example, IN1> I
At N2, the current of I1 increases and the current of I2 decreases. The current I is applied to the point Xa of the current mirror circuit of P1 and P2.
When 1 flows, a current I3 equal to the current I1 flows to the point Xb. When the current I3 flows, the voltage at the point Xb starts to rise, but the rise of the voltage is suppressed by the influence of the following phenomenon.

The current I3 of P2 increases → the point Xb voltage increases → N
2. The rise in the voltage between the drain and the source 2 → the increase in the current I2 in the N2 → the rise in the voltage at the point Xb is suppressed. A similar problem occurs in the output stage, and an increase in the OUT voltage is suppressed. Current I of P3
5 increase → OUT voltage increase → N4 drain-source voltage increase → N4 current I4 increase → OUT voltage increase is suppressed.
When IN1 <IN2, the opposite phenomenon occurs, and the voltage drop at the point Xb and the OUT voltage are suppressed.

FIG. 4 is a graph showing the characteristics of a prototype example in which the comparator circuit shown in FIG. 3 is constructed using a polycrystalline silicon MOSFET as each MOSFET. As shown in FIG. 4, the input / output gain of this circuit is about 4 at the maximum. That is, when a comparator circuit as shown in FIG. 3 on the assumption that a single-crystal silicon MOSFET is used is configured by using a polycrystalline silicon MOSFET,
It can be seen that the input / output gain has a low value.

FIG. 5 is a circuit diagram showing another conventional comparator circuit on the assumption that a single-crystal silicon MOSFET is used. 3 is an n-type MOSF
While receiving the input signal at ET, the comparator circuit of FIG. 5 receives the input signal at the p-type MOSFET. In addition,
n-type MOSFET: N1, N2, p-type MOSFET: P
1 and P2 have the same characteristics.

The comparator circuit shown in FIG. 5 operates as follows when it is composed of a single-crystal silicon MOSFET having a good saturation characteristic. That is, a p-type MOSFET:
Since the sources of P1 and p-type MOSFET: P2 are common, when IN1 <IN2, a current of I1> I2 flows. n-type MOSFET: N1 and N2 operate in the saturation region, regardless of the source-drain voltage.
When the current I1 flows through the point Xa of the current mirror circuit 1 and N2, the current I3 equal to the current I1 flows through the point Xb. Therefore, the current at the point Xb has a relationship of I3> I2, and the voltage at the point Xb falls. The output stage n-type MOSFET: N3 is turned off by the fall of the voltage at the point Xb, and the output OUT
The voltage rises. When IN1> IN2, the operation is performed with the reverse voltage-current relationship as described above.

On the other hand, if each of the n-type MOSFETs of the comparator circuit shown in FIG. 5 is made of a polycrystalline silicon n-type MOSFET having a poor saturation characteristic, this comparator circuit causes the following problem, Decrease the output gain. That is, when the polycrystalline silicon n-type MOSFET is used, the currents I1, I2, and I3 change depending on the source-drain voltage. For example, IN1 <I
At N2, the current of I1 increases and the current of I2 decreases. The current I is applied to the point Xa of the current mirror circuit of N1 and N2.
When 1 flows, a current I3 equal to the current I1 flows to the point Xb. When the current I3 flows, the voltage at the point Xb starts dropping, but the drop of the voltage is suppressed by the influence of the following phenomenon.

The current I3 of N2 increases → the point Xb voltage decreases → N
The voltage between the drain and the source of No. 2 drops → The current I3 of N2 decreases → The drop of the point Xb voltage is suppressed. A similar problem occurs in the output stage, and an increase in the OUT voltage is suppressed. N3 current I5 decrease → OUT voltage rise → N3 drain-source voltage rises → N3 current I5 increase → OUT voltage rise is suppressed. When IN1> IN2, the opposite phenomenon occurs, and a rise in the voltage at the point Xb and a fall in the OUT voltage are suppressed.

FIG. 6 is a graph showing the characteristics of a prototype example in which the comparator circuit shown in FIG. 5 is constructed by using a polycrystalline silicon MOSFET as each MOSFET. As shown in FIG. 6, the input / output gain of this circuit is about 5 at the maximum. That is, when a comparator circuit as shown in FIG. 5 on the assumption that a single-crystal silicon MOSFET is used is configured using a polycrystalline silicon MOSFET,
It can be seen that the input / output gain has a low value.

FIG. 7 is a circuit diagram showing an inverter circuit which is an example of a conventional logic gate on the assumption that a single crystal silicon MOSFET is used.

The inverter circuit shown in FIG.
ET is a single crystal silicon MOSFET with good saturation characteristics
If it consists of, the operation is performed as follows. That is, if IN is G
When shifting from the ND level to the power supply level, the n-type MOSF
ET: Current I1 of N1 increases and p-type MOSFET: P
Through a process in which the current I2 of 1 decreases and the OUT voltage decreases, OUT falls to the GND level. Conversely, I
When N transitions from the power supply level to the GND level, OUT falls to the power supply level through the reverse process.

On the other hand, when the n-type MOSFET of the inverter circuit shown in FIG. 7 is made of a polycrystalline silicon n-type MOSFET having a poor saturation characteristic, this inverter circuit causes the following problems, Decrease the gain. That is, when IN shifts from the GND level to the power supply level, the current I1 of the n-type MOSFET: N1 increases and p
Type MOSFET: The current I2 of P1 decreases, and the OUT voltage decreases. At this time, the voltage between the drain and the source of the n-type MOSFET N1 decreases, and the current I1 of the N1 decreases, thereby suppressing the decrease of the OUT voltage. Conversely, IN
When the power supply shifts from the power supply level to the GND level, the rise of the OUT voltage is suppressed through the reverse process.

FIG. 8 is a graph showing the characteristics of a prototype example in which a polycrystalline silicon MOSFET is used as each MOSFET to constitute the inverter circuit shown in FIG. As shown in FIG. 7, the input / output gain of this circuit is about 4 at the maximum. That is, when the inverter circuit shown in FIG. 7 on the assumption that a single-crystal silicon MOSFET is used is configured by using a polycrystalline silicon MOSFET, the input / output gain becomes low.

FIGS. 9 and 11 show single-crystal silicon MOSFs.
It is a circuit diagram which respectively shows the NAND gate (2 inputs) circuit which is another example of the conventional logic gate on the assumption of using ET, and the NOR gate (2 inputs) circuit which is another example.

The principle of operation of the circuits shown in FIGS. 9 and 11 is basically the same as that of the inverter circuit shown in FIG.
Hereinafter, the description of the operation of the circuits shown in FIGS. 9 and 11 is shared, and IN1 = power supply level in the NAND gate circuit shown in FIG. 9, and IN1 = GN in the NOR gate shown in FIG.
The case where the D level is fixed will be described.

The circuits shown in FIG. 9 and FIG.
ET is a single crystal silicon MOSFET with good saturation characteristics
If it consists of, the operation is performed as follows. That is, when IN2 shifts from the GND level to the power supply level, the n-type MOS
FET: Current I1 of N2 increases and p-type MOSFET:
OUT falls to the GND level through a process in which the current I2 of P2 decreases and the OUT voltage decreases. vice versa,
When IN2 shifts from the power supply level to the GND level, OUT falls to the power supply level through the reverse process.

On the other hand, when each of the n-type MOSFETs of the circuits shown in FIGS. 9 and 11 is made of a polycrystalline silicon n-type MOSFET having a poor saturation characteristic, these circuits are:
The following problems are caused, and the input / output gain is reduced.
That is, when IN2 shifts from the GND level to the power supply level, the current I1 of the n-type MOSFET: N2 increases, the current I2 of the p-type MOSFET: P2 decreases, and the OUT voltage decreases. At this time, the voltage between the drain and the source of the n-type MOSFET N2 decreases, and the current I1 of the N2 decreases, thereby suppressing the decrease of the OUT voltage. Conversely, IN2
When the power supply shifts from the power supply level to the GND level, the rise of the OUT voltage is suppressed through the reverse process.

FIGS. 10 and 12 show a case where a polycrystalline silicon MOSFET is used as each MOSFET.
5 is a graph illustrating characteristics of a prototype example in which the illustrated circuit is configured. As shown in FIGS. 10 and 12, the input / output gain of these circuits is about 4 at the maximum. That is, FIG. 1 on the assumption that a single crystal silicon MOSFET is used.
0 and a circuit as shown in FIG.
It can be seen that the input / output gain is low when configured using FETs.

As described above, the polysilicon MOSFE
T, especially an n-type MOSFET having a channel length of 3 μm or less has almost no saturation characteristics. For this reason, the conventional single crystal silicon M
When a polycrystalline silicon MOSFET is used for a comparator circuit or a CMOS logic gate circuit used in an OSFET, the input / output gain is reduced. When the input / output gain decreases, there is a possibility that the threshold value of the comparator circuit shifts or the transmission time is delayed.

An embodiment of the present invention based on such knowledge will be described below with reference to the drawings.

(First Embodiment) FIG. 13 is a circuit diagram showing a comparator circuit according to a first embodiment of the present invention. This comparator circuit is configured using a polycrystalline silicon MOSFET as each MOSFET. The differential amplifier of this comparator circuit has n-type MOSFETs N1 and N2 that receive input signals, p-type MOSFETs P1 and P2 of a current mirror circuit, and an n-type MOSFET N3 of a current source circuit. The output stage has a p-type MOSFET: P3 for transmitting a signal from the differential amplifier to the next stage, and an n-type MOSFET: N4 of the current source circuit.

The differential amplifier further receives n input signals.
N-type MOSFETs N5 and N6 connected in series to the drains of the N-type MOSFETs N1 and N2, respectively. The output stage further includes an n-type MOSFET of a current source circuit:
An n-type MOSFET connected in series to the drain of N4:
N7. A voltage bias circuit is connected to the gates of the n-type MOSFETs N5, N6 and N7. These additional n-type MOSFETs: N5, N6, N7 suppress voltage variations at points Xa, Xb, and OUT due to poor saturation characteristics of the main n-type MOSFETs: N1, N2, N4. Used to This comparator circuit outputs OUT = GND level when IN1> IN2, and outputs OUT = power supply level when IN1 <IN2.

Next, taking the output stage n-type MOSFET: N7 as an example, additional n-type MOSFETs: N5, N6, N
7 will be described. N-type MOSFET: N7
An operation is performed to suppress the fluctuation of the voltage at the point Xf, that is, the drain voltage of the n-type MOSFET: N4. By suppressing the fluctuation of the drain voltage of N4, the dependence on the drain voltage due to the poor saturation characteristic is reduced, and the drain current according to the gate voltage of N4 flows. That is, by connecting an n-type MOSFET N7 having a gate to which a bias voltage is applied in series to a main n-type MOSFET N4, characteristics as in the case of using a single-crystal silicon MOSFET having good saturation characteristics are obtained. Will be obtained.

The principle that the additional n-type MOSFET N7 suppresses the voltage at the point Xf is as follows. That is, N7
Is supplied with a constant bias voltage: Vbias4 by a voltage bias circuit. Therefore, the source voltage of N7 (voltage at point Xf): Vf
Assuming th (N7), Vf = Vbias4-Vth
(N7). Vth (N7) has a dependency on the drain current (I5), but acts to reduce the fluctuation of the voltage Vf at the point Xf for the following reason. For example, when the voltage at the point Xf increases and the drain current I5 of the N4 increases, the drain current of the N7 also increases, so that Vth (N7) also increases and acts to decrease the voltage at the point Xf. Similarly, when the voltage at the point Xf: Vf decreases, the voltage Vf at the point Xf acts to increase.

The drain voltage of N7, that is, OUT
When the voltage fluctuates, the current capability of N7 changes due to the drain-source voltage dependency. However, the MOSFET size and the like are set so as to satisfy the relationship of (Drain current capability of N7)> (Drain current capability of N4),
If the current capability of the FET itself is adjusted, the finally flowing current I5 is limited to the drain current capability of N4. Such adjustment can reduce the adverse effect of N7 generated when the OUT voltage fluctuates.

Next, the operation of the additional n-type MOSFETs N5, N6 and N7 in the entire comparator circuit shown in FIG. 13 will be described. When IN1> IN2, in the differential amplifier, the current of I1 increases and the current of I2 decreases. P
When the current I1 flows to the point Xa of the current mirror circuit of P1, P2, the current I3 equal to the current I1 flows to the point Xb. When the current I3 flows, the voltage at the point Xb starts to increase. At this time, the influence of the dependency of N2 on the voltage between the drain and the source is reduced by N6, and the increase of the current I2 is suppressed. Therefore, the voltage at the point Xb tends to increase. Similarly,
The influence of the dependency of N1 on the voltage between the drain and source is N
5, and the decrease of the current I1 is suppressed.

When the voltage at the point Xb rises, the output stage P3
Drain current I6 decreases, and the OUT voltage decreases.
At this time, the influence of the voltage dependence between the drain and the source of N4 is reduced by N7, and the decrease of the current I5 is suppressed. Therefore, the OUT voltage tends to decrease. IN1 <I
In the case of N2, a phenomenon in which the relationship between the current and the voltage is reversed occurs, and the main n-type MOSFETs having poor saturation characteristics: N1, N2, N4
, The influence of the drain-source voltage dependency is reduced by the additional n-type MOSFETs: N5, N6 and N7.

FIG. 14 is a graph showing the characteristics of the embodiment in which the comparator circuit shown in FIG. 13 is constituted by using a polycrystalline silicon MOSFET as each MOSFET. FIG.
As shown in FIG. 4, the input / output gain of this circuit is about 13 at the maximum, and it can be seen that the input / output gain is greatly improved as compared with the input / output gain (the maximum of 4) shown in FIG. That is, even if a polycrystalline silicon n-type MOSFET having almost no saturation characteristics is used, the n-type MOSFET is not used in the differential amplifier circuit and the current source circuit.
Are added in series, the input / output gain of the entire comparator circuit can be improved.

(Second Embodiment) FIG. 15 is a circuit diagram showing a comparator circuit according to a second embodiment of the present invention. This comparator circuit is configured using a polycrystalline silicon MOSFET as each MOSFET. While the comparator circuit of FIG. 13 receives an input signal by an n-type MOSFET, the comparator circuit of FIG. 15 receives an input signal by a p-type MOSFET. The differential amplifier of this comparator circuit is a p-type MOSFET receiving an input signal.
T: P1, P2, n-type MOSFE of current mirror circuit
T: N1, N2 and p-type MOSFET of current source circuit:
It has P3. The output stage has an n-type MOSFET: N3 for transmitting a signal from the differential amplifier to the next stage, and a p-type MOSFET: P4 of the current source circuit.

The differential amplifier further has n-type MOSFETs N4 and N5 connected in series to the drains of the n-type MOSFETs N1 and N2 of the current mirror circuit, respectively.
The output stage further includes an n-type MOSFE of the signal transmission circuit.
T: n-type MOSFE connected in series to the drain of N3
T: has N6. n-type MOSFET: N4, N5, N
A voltage bias circuit is connected to the gate of No. 6. These additional n-type MOSFETs N4, N5, N6 suppress voltage fluctuations at points Xa, Xb, and OUT due to poor saturation characteristics of the main n-type MOSFETs N1, N2, N3. Used to This comparator circuit outputs OUT = GND level when IN1> IN2, and outputs OUT = power supply level when IN1 <IN2.

Next, the operation of the additional n-type MOSFETs N4, N5 and N6 in the entire comparator circuit shown in FIG. 15 will be described. When IN1 <IN2, in the differential amplifier, the current of I1 increases and the current of I2 decreases. N
When a current I1 flows through a point Xa of the current mirror circuit of 1, N2, N4, and N5, a current I3 equal to the current I1 flows through a point Xb.
Flows. Therefore, the current at point Xb is I3> I2
And the voltage at the point Xb starts decreasing. At this time, the influence of the dependency of N2 on the voltage between the drain and the source is reduced by N5, and the decrease of the current I3 is suppressed. Therefore, the voltage at point Xb tends to decrease. Similarly,
The influence of the dependency of N1 on the voltage between the drain and source is N
4, and the decrease of the current I1 is suppressed.

When the voltage at the point Xb falls, the output stage N3
Drain current I6 decreases, and the OUT voltage decreases.
At this time, the influence of the dependency of N3 on the voltage between the drain and the source is reduced by N6, and the increase of the current I6 is suppressed. Therefore, the OUT voltage tends to increase. IN1> I
In the case of N2, the phenomenon that the relationship between the current and the voltage is reversed occurs, and the main n-type MOSFETs with poor saturation characteristics: N1, N2, N3
, The influence of the drain-source voltage dependency is reduced by additional n-type MOSFETs: N4, N5 and N6.

FIG. 16 is a graph showing the characteristics of an embodiment in which the comparator circuit shown in FIG. 15 is constituted by using a polycrystalline silicon MOSFET as each MOSFET. FIG.
As shown in FIG. 6, the input / output gain of this circuit is about 12 at the maximum, and it can be seen that it is greatly improved as compared with the input / output gain (the maximum of 5) shown in FIG. That is, even if a polycrystalline silicon n-type MOSFET having almost no saturation characteristics is used, the n-type MOSFET is not used in the current mirror circuit and the signal transmission circuit.
By additionally connecting SFETs in series, the input / output gain of the entire comparator circuit can be improved.

(Third Embodiment) FIG. 17 is a circuit diagram showing an inverter circuit according to a third embodiment of the present invention. This inverter circuit is configured using a polycrystalline silicon MOSFET as each MOSFET. In this inverter circuit, n-type MOSFETs: N1 and p
Type MOSFET: P1 gate is IN, drain is OU
T is commonly connected. n-type MOSFET: N1 and p
The source of the type MOSFET: P1 is connected to GND and a power source, respectively.

This inverter circuit further comprises an n-type MOS
FET: N1 and p-type MOSFET: n-type MOSFET connected in series between the drain of P1 and OUT
T: has N2 and p-type MOSFET: P2. n-type M
Voltage bias circuits are connected to the gates of the OSFET: N2 and the p-type MOSFET: P2, respectively. These additional n-type MOSFETs: N2 and p-type MOSFETs: P2
Is the main n-type MOSFET: N1 and p-type MOSF
ET: Used to suppress voltage fluctuations at OUT due to poor saturation characteristics of P1. This inverter circuit is connected to OUT when the logic input is at IN = power supply level.
= GND level, and when IN = GND level,
UT = output power supply level. That is, a logic inverted from the input logic is output.

Next, additional n-type MOSFETs: N2 and p-type MOSFETs in the entire inverter circuit shown in FIG.
The operation of ET: P2 will be described. When IN shifts from the GND level to the power supply level, the current I1 of the n-type MOSFET: N1 increases, the current I2 of the p-type MOSFET: P1 decreases, and the OUT voltage decreases. At this time, the decrease in current capability due to the dependency of N1 on the voltage between the drain and the source is reduced by N2, and the increase in current I1 is facilitated. Also,
The increase in current capability due to the dependency of P1 on the voltage between the drain and the source is reduced by P2, and the reduction of current I2 is facilitated. Therefore, the OUT voltage tends to decrease. Conversely, I
When N shifts from the power supply level to the GND level, the OUT voltage easily rises through the reverse process.

FIG. 18 is a graph showing the characteristics of an embodiment in which a polycrystalline silicon MOSFET is used as each MOSFET to constitute the inverter circuit shown in FIG. FIG.
As shown in the figure, the input / output gain of this circuit is about 10 at the maximum, and it is understood that the input / output gain is greatly improved as compared with the input / output gain (4 at the maximum) shown in FIG. That is, even if a polycrystalline silicon MOSFET having poor saturation characteristics is used, the n-type and p-type
By adding additional MOSFETs in series,
The input / output gain of the entire inverter circuit can be improved.

(Fourth Embodiment) FIG. 19 is a circuit diagram showing a NAND gate (two-input) circuit according to a fourth embodiment of the present invention. This NAND gate circuit has
The SFET is configured using a polycrystalline silicon MOSFET. This NAND gate circuit includes two n-type MOSFETs N1 and N2 connected in series with each other and two p-type MOSFETs P1 connected in parallel with each other.
P2. IN1 is commonly connected to the gates of an n-type MOSFET: N1 and a p-type MOSFET: P1,
IN2 is an n-type MOSFET: N2 and p-type MOSFET
T: Commonly connected to the gate of P2. OUT is n-type M
OSFET: drain of N2 and p-type MOSFET: P
1, are commonly connected to the drains of P2. p-type MOSF
ET: The sources of P1 and P2 are the power supply and n-type MOSFET
The sources of T: N1 are respectively connected to GND.

This NAND gate circuit further includes an n-type M
OSFET: N2 and p-type MOSFETs: n-type M connected in series between the drains of P1, P2 and OUT, respectively.
It has an OSFET: N3 and a p-type MOSFET: P3. n-type MOSFET: N3 and p-type MOSFET: P
A voltage bias circuit is connected to each of the gates 3. These additional n-type MOSFETs: N3 and p-type MOSFET
ET: P3 is the main n-type MOSFET: N2 and p
Type MOSFET: used to suppress voltage fluctuations at OUT due to poor saturation characteristics of P1, P2. This NAND gate circuit has a logic input IN1 =
OUT = G only when power supply level and IN2 = power supply level
ND level logic is output, and when the logic input is other than this, OUT = power level logic is output.

Next, additional n-type MOSFETs: N3 and p-type MOs in the entire NAND gate circuit shown in FIG.
The operation of the SFET: P3 will be described. When IN2 shifts from the GND level to the power supply level while IN1 is at the power supply level, the current I1 of N2 increases and the p-type MOSFET increases.
T: The current I2 of P2 decreases, and the OUT voltage decreases.
At this time, the decrease in current capability due to the dependency of N2 on the voltage between the drain and the source is reduced by N3, and the increase in current I1 is facilitated. Further, the increase in current capability due to the dependency of P1 and P2 on the voltage between the drain and the source is reduced by P3, and the reduction of the current I2 is facilitated. Therefore, the OUT voltage tends to decrease. Conversely, IN2 changes from power supply level to G
When transitioning to the ND level, the O
The UT voltage tends to increase.

FIG. 20 is a graph showing the characteristics of the embodiment in which the NAND gate circuit shown in FIG. 19 is constituted by using a polycrystalline silicon MOSFET as each MOSFET. As shown in FIG. 20, the input / output gain of this circuit is about 8 at the maximum, compared with the input / output gain (4 at the maximum) shown in FIG.
It can be seen that it is greatly improved. That is, even if a polycrystalline silicon MOSFET having a poor saturation characteristic is used, the input / output gain of the entire NAND gate circuit can be improved by additionally connecting the n-type and p-type MOSFETs in series.

(Fifth Embodiment) FIG. 21 is a circuit diagram showing a NOR gate (two-input) circuit according to a fifth embodiment of the present invention. This NOR gate circuit is composed of each MOSF
The ET is configured using a polycrystalline silicon MOSFET. This NOR gate circuit includes two n-type MOSFETs: N1 and N2 connected in parallel with each other and two p-type MOSFETs: P1 and P2 connected in series with each other.
And IN1 is an n-type MOSFET: N1 and p
Type MOSFET: commonly connected to the gate of P1. I
N2 is an n-type MOSFET: N2 and a p-type MOSFET:
Commonly connected to the gate of P2. OUT is a p-type MOS
FET: drain of P2 and n-type MOSFET: N1,
Commonly connected to the drain of N2. p-type MOSFE
T: The source of P1 is a power supply, and an n-type MOSFET: N1,
The sources of N2 are each connected to GND.

This NOR gate circuit further includes an n-type MO
SFET: N1, N2 and p-type MOSFET: n-type MO connected in series between the drain of P2 and OUT
It has an SFET: N3 and a p-type MOSFET: P3.
Voltage bias circuits are respectively connected to the gates of the n-type MOSFET: N3 and the p-type MOSFET: P3. These additional n-type MOSFETs: N3 and p-type MOSFET
T: P3 is used to suppress voltage fluctuations at OUT due to poor saturation characteristics of the main n-type MOSFETs: N1, N2 and p-type MOSFET: P2. This NOR gate circuit has a logic input IN1 = G
OUT = only when ND level and IN2 = GND level
The logic of the power supply level is output, and when the logic input is other than this, the logic of OUT = GND level is output.

Next, additional n-type MOSFETs: N3 and p-type MOSs in the entire NOR gate circuit shown in FIG.
The operation of the FET: P3 will be described. When IN2 shifts from the GND level to the power supply level while IN1 is at the GND level, the current I1 of N2 increases and the p-type MOSFET
T: The current I2 of P2 decreases, and the OUT voltage decreases.
At this time, the current capability decrease due to the voltage dependence between the drain and the source of N1 and N2 is reduced by N3, and the increase of the current I1 is facilitated. Further, the increase in current capability due to the dependency of P2 on the voltage between the drain and the source is reduced by P3, and the current I2 is more likely to decrease. Therefore, the OUT voltage tends to decrease. Conversely, IN2 changes from power supply level to G
When transitioning to the ND level, the O
The UT voltage tends to increase.

FIG. 22 is a graph showing the characteristics of the embodiment in which the NOR gate circuit shown in FIG. 21 is constituted by using a polycrystalline silicon MOSFET as each MOSFET. FIG.
As shown in FIG. 2, the input / output gain of this circuit is about 8 at the maximum, and it can be seen that it is greatly improved as compared with the input / output gain (4 at the maximum) shown in FIG. That is, even if a polycrystalline silicon MOSFET having poor saturation characteristics is used, the input / output gain of the entire NOR gate circuit can be improved by additionally connecting the n-type and p-type MOSFETs in series.

In each of the above embodiments, each F
The insulating film of the gate structure of the ET is not limited to the oxide film, and a so-called MIS structure (that is, MISFET) can be used.

Although the preferred embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited to such configurations. Within the scope of the technical idea described in the claims, those skilled in the art
Various changes and modifications can be conceived, and it is understood that these changes and modifications also belong to the technical scope of the present invention.

[0062]

According to the present invention, a polycrystalline silicon n-type MISFET having a gate to which a bias voltage is applied is connected in series to the drain of a main polycrystalline silicon n-type MISFET. MISFET
Can be provided, such as a comparator circuit and a CMOS logic gate circuit, which can obtain characteristics as in the case of using a semiconductor device.

[Brief description of the drawings]

FIG. 1 is a graph showing static characteristics of a polycrystalline silicon n-type MOSFET.

FIG. 2 is a graph showing static characteristics of a polycrystalline silicon p-type MOSFET.

FIG. 3 is a circuit diagram showing a conventional comparator circuit (n-type MOSFET input type).

FIG. 4 shows a polycrystalline silicon MOSF as each MOSFET.
4 is a graph showing characteristics of a prototype example in which the comparator circuit shown in FIG. 3 is configured using ET.

FIG. 5 is a circuit diagram showing a conventional comparator circuit (p-type MOSFET input type).

FIG. 6 shows a polycrystalline silicon MOSF as each MOSFET.
6 is a graph showing characteristics of a prototype example in which the comparator circuit shown in FIG. 5 is configured using ET.

FIG. 7 is a circuit diagram showing a conventional inverter circuit.

FIG. 8 shows a polycrystalline silicon MOSF as each MOSFET.
8 is a graph showing characteristics of a prototype example in which the inverter circuit shown in FIG. 7 is configured using ET.

FIG. 9 is a circuit diagram showing a conventional NAND gate (two-input) circuit.

FIG. 10 shows a polycrystalline silicon MOS as each MOSFET.
10 is a graph showing characteristics of a prototype example in which the NAND gate circuit shown in FIG. 9 is configured using FETs.

FIG. 11 is a circuit diagram showing a conventional NOR gate circuit (two-input) circuit.

FIG. 12 shows a polycrystalline silicon MOS as each MOSFET.
12 is a graph illustrating characteristics of a prototype example in which the NOR gate circuit illustrated in FIG. 11 is configured using FETs.

FIG. 13 is a circuit diagram showing a comparator circuit (n-type MOSFET input type) according to the first embodiment of the present invention.

FIG. 14 shows a polycrystalline silicon MOS as each MOSFET.
14 is a graph showing characteristics of an embodiment in which the comparator circuit shown in FIG. 13 is configured using FETs.

FIG. 15 is a circuit diagram showing a comparator circuit (p-type MOSFET input type) according to a second embodiment of the present invention.

FIG. 16 shows a polycrystalline silicon MOS as each MOSFET.
FIG. 16 is a graph showing characteristics of an example in which the comparator circuit shown in FIG. 15 is configured using FETs.

FIG. 17 is a circuit diagram showing an inverter circuit according to a third embodiment of the present invention.

FIG. 18 shows a polycrystalline silicon MOS as each MOSFET.
FIG. 18 is a graph showing characteristics of an example in which the inverter circuit shown in FIG. 17 is configured using FETs.

FIG. 19 is a circuit diagram showing a NAND gate (two-input) circuit according to a fourth embodiment of the present invention.

FIG. 20 shows a polycrystalline silicon MOS as each MOSFET.
FIG. 20 is a graph showing characteristics of the embodiment in which the NAND gate (two-input) circuit shown in FIG. 19 is configured using FETs.

FIG. 21 is a circuit diagram showing a NOR gate (two-input) circuit according to a fifth embodiment of the present invention.

FIG. 22 shows a polycrystalline silicon MOS as each MOSFET.
Using a FET, the NOR gate shown in FIG. 21 (two inputs)
4 is a graph illustrating characteristics of an example in which a circuit is configured.

[Explanation of symbols]

 N1 to N7 n-type MOSFETs P1 to P4 p-type MOSFETs Vbias1 to Vbias1 Bias power supply I1 to I6 Current

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) // H03F 3/16 H03K 19/094 A (72) Inventor Akio Nakagawa Toshiba Komukai, Saiwai-ku, Kawasaki-shi No. 1 Town Toshiba R & D Center F-term (reference) AA12 CA11 FA20 HA10 HA17 KA06 KA09 KA12 MA21 TA02

Claims (7)

[Claims] 1. An n-type first MISFET having a polycrystalline silicon layer as an active region, connected between a node of a signal transmission line and a low potential source, and connected between the node and the first MISFET. In addition, an n-type second MI using the polycrystalline silicon layer as an active region
An SFET; and means for applying a bias voltage to the gate of the second MISFET, wherein the second MISFET suppresses voltage fluctuations at the node due to poor saturation characteristics of the first MISFET. Polycrystalline silicon circuit. 2. The polycrystalline silicon circuit according to claim 1, further comprising means for applying a bias voltage to the gate of said first MISFET, to constitute a current source circuit. 3. The semiconductor device according to claim 1, wherein a polycrystalline silicon layer connected to said low potential source in parallel with said first MISFET is used as an active region.
A third MISFET of the type, and connected in series to the drain of the third MISFET;
N-type fourth MISF having a polycrystalline silicon layer as an active region
ET; first and second input means for inputting a differential signal to the gates of the first and third MISFETs, respectively; and means for applying a bias voltage to the gate of the fourth MISFET. 2. The polycrystalline silicon circuit according to claim 1, wherein said polycrystalline silicon circuit constitutes a differential amplifier. 4. A polycrystalline silicon layer connected to the low potential source in parallel with the first MISFET and having a polycrystalline silicon layer as an active region.
A third MISFET of the type, and connected in series to the drain of the third MISFET;
N-type fourth MISF having a polycrystalline silicon layer as an active region
ET, and the gate of the first MISFET is connected to the third MISFET.
And a means for applying a bias voltage to the gate of the fourth MISFET, and a current mirror circuit of the differential amplifier. 2. The polycrystalline silicon circuit according to 1. 5. A p-type third MI connected between the node and a high potential source and having a polycrystalline silicon layer as an active region.
An SFET; and input means for inputting a logic signal to the gates of the first and third MISFETs, wherein a CMOS logic gate circuit that outputs a logic signal from the node is configured. Item 2. The polycrystalline silicon circuit according to Item 1. 6. A p-type fourth MISFET having a polycrystalline silicon layer as an active region, connected between the node and the third MISFET, and means for applying a bias voltage to a gate of the fourth MISFET. And the third MISFET.
6. The polycrystalline silicon circuit according to claim 5, wherein the fourth MISFET suppresses a voltage change at the node due to a poor saturation characteristic of the polycrystalline silicon. 7. A p-type main MIS connected between said node and a high-potential source and having a polycrystalline silicon layer as an active region.
FET, connected between the node and the main MISFET;
P-type sub-MISFE having polycrystalline silicon layer as active region
T; and means for applying a bias voltage to the gate of the sub MISFET, wherein the sub MISFET suppresses voltage fluctuations at the node due to poor saturation characteristics of the main MISFET. The polycrystalline silicon circuit according to any one of claims 1 to 6, wherein: