JP2001092648A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which a flash ROM in different types are available. SOLUTION: This semiconductor memory using the flash(F) ROM being non-volatile and programmable semiconductor storage elements is provided with an interface means for forming an interface circuit between the storage elements and outside circuits by using an FPGA capable of loading of a program on a substrate and a program loading means for loading the program corresponding to the FROM to the FPGA at the time of power supply. Thus, it is possible to generalize the FPGA for control by loading a control program to the FPGA. Moreover, it is possible to generalize the substrate by changing a loading position of the FROM for each type, and providing a means for identifying the loaded FROM.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device that can use different types of flash ROMs.

[0002]

2. Description of the Related Art Conventionally, a flash ROM (FRO) which is a nonvolatile and programmable semiconductor memory element is used.
Various types of silicon (flash) disk drive devices using M) have been proposed. As the flash ROM used in the device, there are two types of circuit configurations, an AND type and a NAND type. But,
The ROMs of the respective systems are not compatible, and the terminal functions and arrangements of the ROMs of the same system differ depending on the manufacturer. Therefore, when manufacturing a flash disk drive device, a dedicated substrate and a gate array chip for interface control have been developed according to the flash ROM to be used.

[0003]

As described above, flash ROMs have various specifications and are not standardized. Therefore, when flash ROMs are purchased from a plurality of manufacturers to manufacture a flash disk drive, In such a case, it is necessary to develop a plurality of types of substrates and control gate arrays, which increases the development cost, or cannot be used for other types, so that there is a problem that inventory is required and inventory increases. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art and to provide a semiconductor memory device that can use different types of flash ROMs.

[0004]

According to the present invention, there is provided a semiconductor memory device using a nonvolatile and programmable semiconductor memory element, wherein a gate array element capable of loading a program on a substrate is used. Interface means for forming an interface circuit between the storage element and an external circuit, and program loading means including a ROM storing a CPU and a program to be loaded, and loading a program corresponding to the semiconductor storage element into a gate array element when power is turned on. And characterized in that:

According to the present invention, a gate array element (FPGA: field-effect matrix array) capable of loading a program on a substrate is used, and when the power is turned on, the FP is used.
By loading the control program into the GA, the control gate array can be generalized. Also, Flash RO
By changing the mounting position for each type of M and by providing a means for identifying the mounted flash ROM, it is possible to generalize the substrate. Furthermore, terminals having functions unique to each type of flash ROM are individually housed in the FPGA,
By driving all the terminals of A, it is possible to share the FPGA program.

[0006]

Embodiments of the present invention will be described below in detail. FIG. 1 is a block diagram showing a configuration of a first embodiment of a semiconductor memory device to which the present invention is applied. The semiconductor storage device 10 of the present invention has the same IDE interface function as a well-known hard disk device when viewed from the outside,
This is a device that can read / write files as well as a hard disk device. Also, the flash RO used
Since M is nonvolatile, the stored contents are preserved even when the power is turned off.

The FPGA 11, which is a gate array element capable of loading a program on a substrate, includes a connection line 20 from a hard disk interface circuit of a computer and a connection line 1 to a plurality of FROMs 15 to 17, for example.
9. Connected to the CPU bus 18 inside the device, and loaded with a control program under the control of the CPU 12, as described later, to function as an IDE controller.

The FPGA used in the present invention is, for example, a commercially available Xilinx (registered trademark) Spa.
rtan® series FPGAs can be used. Since the internal configuration and operation of the FPGA are well known, a detailed description thereof will be omitted. However, a plurality of programmable logic circuit blocks (CLBs) and a programmable input / output block (IOBs) are used. The O-block is configured to be arbitrarily connectable by a plurality of programmable switch matrices, PSMs (block-map switch matrices). Then, by inputting configuration data, which is program data for determining the configuration in the chip, from outside as a serial signal, the configuration can be programmed any number of times. CP
The U12, the ROM 13, and the SRAM 14 function as program loading means for loading a program corresponding to the semiconductor memory element into the gate array element when power is turned on. After the loading, the entire semiconductor memory device is controlled.

FIG. 2 is an explanatory diagram showing terminal functions of various flash ROMs. There are two types of circuit configurations of FROM, which are non-volatile and programmable semiconductor storage elements, of an AND type and a NAND type. However, the FROM types are not compatible and the FROM type is the same. Even so, the terminal functions and arrangements differ depending on the manufacturer. FIG. 2A is an explanatory diagram showing an example of a terminal function of a NAND-type FROM. I / O1 to I / O8 are address data command input / output ports, CE is chip enable, W
E is a write enable, RE is a REIT enable, CLE is a COMMAND latch enable, ALE address latch enable, WP is a write protect, and RDY is a ready output.

FIG. 2B is an explanatory diagram showing an example of the terminal function of the AND-type FROM. . I / O1 to I / O8 are input / output ports, CE is a chip enable, WE is a write enable, OE is an output enable, SC is a serial clock, CDE is a command line, RE
S is reset and RDY is ready output. Some of these terminals, such as CE and WE, have a function common to each FROM, but some terminals have a function specific to each FROM, such as ALE, RES, SC.

Further, the types and positions of the power supply terminals are different in each FROM. Each power supply terminal needs to be directly connected to the power supply layer or the ground layer of the substrate. Therefore, it is impossible to mount different types of FROMs at the same position (through hole) on the board. Therefore, in the first embodiment, a board corresponding to each type of FROM is used.

FIG. 3 is a functional block diagram showing functions when a program is loaded on the FPGA. IDE interface circuit 21, CPU interface circuit 2
2. The SRAM interface circuit 23 and the FROM interface circuit 24 have interface functions for respective data, address, and control lines, and are connected to other circuits via the internal bus of the FPGA 11.

The IDE interface circuit 21 has an ID
It holds the contents of each register of the E specification and generates an interrupt signal to the CPU 12 when a command is written from an external IDE control circuit. The CPU interface circuit 22 provides an interface function corresponding to the type of the CPU 12 mounted. The SRAM interface circuit 23 generates a control bus signal for the SRAM 14, and the address and data buses are shared with the CPU bus. During the DMA transfer, the FPGA 11 outputs an address signal.

The FROM interface circuit 24 has a C
On the basis of the control from the PU 12, on / off of various control signals of the FROMs 15 to 17, writing of commands and addresses to the FROM, and reading of status are controlled. The DMA controller 25 is used for reading / writing data.

The DMA controller 25 is a control circuit for directly transferring data between the SRAM 14 and an external hard disk interface circuit and between the SRAM 14 and the FROMs 15 to 17 without the intervention of the CPU 22 under the control of the CPU 22. . ECC calculation circuit 26
Generates and adds an ECC code (for example, a 24-bit ECC that can correct 1 bit for 512-byte data) to data to be written to the FROMs 15 to 17,
The ECC code of the data read from the OMs 15 to 17 is checked and error detection / correction is performed. In the present invention, the function (program) of the FROM interface circuit 24 differs depending on the type of FROM, and the functions of the other circuits are the same as those of the conventional individual gate array.

FIG. 4 is a flowchart showing the contents of the processing when the power is turned on in the CPU. For example, when the power of the personal computer on which the semiconductor memory device 10 of the present invention is mounted is turned on, the CPU 12 reads out the FPGA program data (configuration data) stored in the ROM 13 in S10. In S11, the read FP
The GA program data is loaded into the FPGA by a predetermined method according to the specifications of each FPGA.

The FPGA 11 loaded with the FPGA program data functions as a circuit that performs a predetermined interface function, and the CPU 12 executes data read and write processing based on commands from an external hard disk interface circuit. Specifically, for example, upon receiving a command to read data of a predetermined track or sector from an external hard disk interface circuit, the CPU 12 reads the track or sector from the FROM.
The data is converted into addresses 15 to 17, and the corresponding data is once read to the SRAM 14. Thereafter, the data is sequentially output to an external hard disk interface circuit. (Actually D
MA transfer is performed. )

In the first embodiment disclosed above,
It is no longer necessary to design a gate array for each FROM, but programs for printed circuit boards and FPGAs are
It is necessary to design and manufacture for each M. A second embodiment is:
In this embodiment, the printed circuit board can be shared, and the FPGA program can be shared.

FIG. 5 is an explanatory view showing a configuration example of a substrate according to a second embodiment of the present invention. As described above, each FR
Since the position of the power supply terminal differs for each OM, different types of FROM cannot be mounted at the same position. Therefore, the mounting position is changed for each FROM. For example, FROM
(Type A) is mounted at the mounting position 30, and FROM (Type B) is mounted at the mounting position 31.

The terminals having the same function in each FROM are connected to the same terminal of the FPGA 11. For example, when the terminal 32 of the FROM (type A) and the terminal 33 of the FROM (type B) have the same function (waveform, timing), they are connected to the same terminal of the FPGA 11 as illustrated. At this time, it is not necessary for both terminals to have exactly the same waveform and timing, and it is possible to adjust the waveform and timing of the terminals according to the mounted FROM by a program inside the connected FPGA 11.

A terminal having a different function for each FROM is independently connected to a terminal of the FPGA 11. For example, when the FROM (type A) terminal 34 and the FROM (type B) terminal 35 have different functions (waveforms, timings), they are connected to different terminals of the FPGA 11 as shown. In the FPGA 11, the mounted FROM is recognized by a method described later, and the corresponding terminal is driven. With the above configuration, the printed circuit board can be shared.

FIG. 6 is a flow chart showing the contents of processing at the time of power-on in the second embodiment of the present invention. Second
In the embodiment of the present invention, the FROM
And loads the corresponding FPGA program. In S20, an initial value of the FROM type is set. In S21, an ID check program corresponding to the set type is loaded into the FPGA 11.

Each FPGA 11 has an ID read mode,
Or FROM such as product identification code read mode
Mode for reading the identification information (ID) of
By reading the ID, the mounted FROM
Type is found. However, the ID read mode itself is different for each FROM. Therefore, in S22, a read operation corresponding to each FROM is performed, and in S23
In, it is determined whether or not the ID was correctly read,
If the data can be read correctly, the type is determined to be the mounted type, and the process proceeds to S25. If NG, the process proceeds to S24, the FROM type is changed, and the process is repeated from S21. In S25, F corresponding to the recognized type
FP interface control program for PGA11
Load to GA11.

With the above configuration, the substrates can be shared. However, the program to be loaded into the FPGA 11 needs to be designed for each FROM. Therefore, a method for sharing a program will be described next. FIG.
As shown in (1), terminals having different functions of the FROM are individually connected to the FPGA. Therefore, a FROM-compatible program is loaded into the FPGA and the loaded FR
Instead of driving only the terminal to which the OM is connected,
Loading a common program and loading multiple types of FROM
Are simultaneously driven.

For example, since the terminal 34 and the terminal 35 in FIG. 5 are individually housed in the FPGA, each terminal of the FPGA is driven by a signal corresponding to each FPGA. In this way, what type of FRO
M, the program for the FPGA can be shared, and the FR disclosed in the second embodiment can be used.
The OM type identification operation is not required.

Although the embodiments of the present invention have been disclosed above, the present invention may have the following modifications. In the embodiments, the semiconductor disk device providing the same interface function as the hard disk device from the outside is disclosed. However, the present invention is applicable to any storage device using FROM.

[0027]

As described above, in the present invention,
The semiconductor memory device includes an interface unit that forms an interface circuit between the storage element and an external circuit using an FPGA, and a program load unit that loads a program corresponding to the semiconductor storage element into the FPGA when power is turned on. Therefore, there is an effect that the gate array for control can be generalized. Further, by changing the mounting position for each type of flash ROM and providing the identification means for the mounted flash ROM, it is possible to generalize the substrate. In addition, terminals having different functions depending on the type of FROM are individually accommodated in the FPGA, so that
There is an effect that a program for GA can be shared.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a semiconductor memory device to which the present invention is applied.

FIG. 2 is an explanatory diagram showing terminal functions of various flash ROMs.

FIG. 3 is a functional block diagram illustrating functions when a program is loaded into an FPGA.

FIG. 4 is a flowchart showing the contents of processing when the power is turned on in the CPU.

FIG. 5 is an explanatory diagram showing a configuration example of a substrate according to a second embodiment of the present invention.

FIG. 6 is a flowchart showing the contents of processing at the time of power-on in the second embodiment of the present invention.

[Explanation of symbols]

, 10 semiconductor memory device, 11 FPGA, 12 CP
U, 13 ROM, 14 SRAM, 15-17 FR
OM, 18 CPU bus, 19 FROM bus, 20 ...
IDE interface line, 21 ... IDE interface circuit, 22 ... CPU interface circuit, 23 ...
SRAM interface circuit, 24 FROM interface circuit, 25 DMA controller, 26 E
CC calculation circuit, 30, 31, ... FROM mounting position, 32-
35 ... Terminal

Claims (3)

[Claims] 1. A semiconductor memory device using a nonvolatile and programmable semiconductor memory element, wherein a gate array element capable of loading a program on a substrate is used, and an interface between the semiconductor memory element and an external circuit is provided. Interface means for forming a circuit, ROM storing a CPU and a program to be loaded
And a program loading means for loading a program corresponding to the semiconductor memory element into the gate array element when power is turned on. 2. A printed circuit board having a different mounting position for each of the different types of semiconductor storage elements, and identification means for identifying the mounted semiconductor storage elements, wherein the program load means is identified by the identification means. 2. The semiconductor memory device according to claim 1, wherein a program corresponding to a type of the semiconductor memory element is loaded. 3. A semiconductor device having a different mounting position for each of the different types of semiconductor memory elements, and at least terminals that need to be driven with a waveform specific to the type of the semiconductor memory element are individually connected to terminals of the gate array element. 2. The semiconductor memory device according to claim 1, further comprising a printed circuit board, wherein the program loading means loads a common program for driving all terminals of the gate array element.