JP2001077334A - Semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a semiconductor device capable of reducing the cost by reducing the size of the output cell and the chip area even when different driving capabilities are required for the output cell. . SOLUTION: In order to form a plurality of transistors Qp1 to Qp7 arranged in an output cell 4A, gate electrodes 22A to 22P formed on a semiconductor substrate via a gate insulating film.
22E and diffusion regions 24A to 24F formed on both sides of the gate electrode. The endmost impurity diffusion region 24F is formed in the gate width direction 40 of the gate electrode.
Are divided into a plurality of divided diffusion regions 26A, 26B, 26C. Thus, three transistors Qp5 to Qp7 sharing the gate electrode 22E are formed. The gate width of these transistors Qp5 to Qp7 is Wpd, and is smaller than the gate width Wp of the other transistors Qp1 to Qp4. Therefore, if the transistors Qp5 to Qp7 are used, an output driver with low current driving capability can be configured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to at least two types of output cells, one requiring a large driving capability and the other requiring a small driving capability.
The present invention relates to a semiconductor device including output cells of different types.

[0002]

2. Description of the Related Art In general, in a semiconductor integrated circuit such as a gate array device or an embedded array device, the driving capability required for each input / output cell may be different. In an input / output cell that requires a large driving capability, it is necessary to use a large transistor for the output driver. On the other hand, when such a large-sized transistor is used in an input / output cell that requires a small driving capability, noise such as overshoot and undershoot increases when a signal changes. It is also conceivable to suppress the performance by connecting a diffused resistor or the like in series to the output line of a large-sized transistor. However, in this case, a region for forming a diffused resistor or the like is required, so that the area of the input / output cell becomes large, and the rising and falling characteristics of the output signal deteriorate. Therefore, conventionally, in an input / output cell that requires a small driving capability, a desired driving capability has been realized by using a small-sized transistor for an output driver.

In a full-custom semiconductor device, since the driving capability of each input / output cell is already known at the stage of manufacturing a bulk substrate, only a transistor of a required size is required for each input / output cell.

However, in a master slice type semiconductor device, a large number of transistors are formed on a bulk substrate in advance, and wirings to be connected to the large number of transistors are determined after the logic and capability required by a customer are known. This applies not only to the internal cell region located in the central region of the semiconductor device but also to the input / output cell region formed therearound.

Therefore, in the master slice type semiconductor device, it is necessary to arrange a plurality of transistors having a wide gate width and at least one transistor having a narrow gate width in every input / output cell. If transistors having a wide gate width are connected in parallel, a large current driving capability can be realized. Conversely, if only a transistor with a narrow gate width is used, a smaller current driving capability can be realized than when only one transistor with a wide gate width is used.

[0006]

However, according to the conventional master slice type semiconductor device, it is necessary to form several types of transistors having different gate widths for each driving capability required for each input / output cell. In addition, the area of each input / output cell increases, the design becomes complicated, and the cost increases.

Accordingly, an object of the present invention is to reduce the cost by reducing the size of the input / output cells and the chip area even when different driving capabilities are required for the input / output cells. It is to provide a device.

[0008]

One embodiment of the present invention is a master slice type semiconductor in which a large number of transistors are formed in advance on a semiconductor substrate, and transistors selected from the large number of transistors are connected by wiring. The device has an input / output cell area provided in a peripheral area, and an internal cell area provided inside the input / output cell area, wherein a plurality of output cells are arranged in the input / output cell area. In each of the output cells, an output terminal and a plurality of transistors are arranged, a transistor selected from the plurality of transistors is connected to the output terminal, and each of the plurality of transistors is connected to the semiconductor substrate. A gate electrode formed on the semiconductor substrate via a gate insulating film, and two diffusion regions formed on the semiconductor substrate on both sides of the gate electrode. , At least one of said transistors, said the one of the two diffusion regions, characterized in that it is divided into a plurality of divided diffusion region with a gate width direction of the gate electrode.

According to one embodiment of the present invention, the transistor can be divided for each divided diffusion region by dividing the impurity diffusion region into a plurality of divided diffusion regions.
The gate width of the transistor including the divided diffusion region is shorter than the gate width of another transistor whose impurity diffusion region is not divided. Therefore, by using the transistor having the short gate width, an output driver having a small current driving capability can be configured. On the other hand, in a transistor in which an impurity diffusion region is divided, a current driving capability equivalent to that of another transistor in which the impurity diffusion region is not divided can be obtained by using the plurality of divided diffusion regions as a common drain. Therefore, if a plurality of transistors are connected in parallel, an output driver having higher current driving capability can be configured.

As described above, by dividing the impurity diffusion region, a transistor having a short gate width and a transistor having a reference gate width can be selectively used, and it is not necessary to separately arrange a transistor having a short gate width. It is possible to reduce the area of the input / output cell, and thus the chip area.

Here, an element isolation region is arranged between two adjacent divided diffusion regions. Thus, it can be divided into a plurality of divided diffusion regions.

In the other of the two diffusion regions sandwiching the gate electrode, a region close to the gate electrode can be a region divided by an element isolation region. The region other than the divided region is continuous along the gate width direction. This can prevent the movement of charges between adjacent divided diffusion regions. Further, a continuous region along the gate width direction can be left in the other diffusion region. This is because this region is used as a common source by the wiring, and it is not necessary to completely separate the region. This element isolation region can be formed by an element isolation insulating film.

It is preferable that the gate electrodes of the plurality of transistors are arranged in parallel so that the impurity diffusion region between the two gate electrodes serves as a common source or a common drain of the two transistors. In this case, a plurality of transistors can be densely arranged, and the area of the output cell can be reduced. At this time, the plurality of divided diffusion regions are preferably formed in the impurity diffusion region at the outermost end. This is because only the transistor having the shortest gate electrode can be divided into a plurality. However, the impurity diffusion region between the two parallel gate electrodes may be divided instead of the shortest impurity diffusion region. In this case, two transistors each composed of two gate electrodes and impurity diffusion regions on both sides thereof are separated.

The divided diffusion region having the minimum width, together with the gate electrode and the other diffusion region, can constitute a transistor having the minimum current driving capability. Therefore, if only this transistor is used, an output transistor having the minimum driving capability can be configured.

At this time, each width of the plurality of divided diffusion regions is
They may be set equal or may be set differently.

In at least one of the plurality of output cells, at least one of the plurality of divided diffusion regions can be a drain region connected to an output terminal by a wiring. By using the divided diffusion region as a drain, it can be used as an output driver.

Each of the plurality of output cells has an output terminal and VD
The semiconductor device may include a first output driver arranged between the D potential supply line and a second output driver arranged between the output terminal and the VSS potential supply line. The first output driver is configured by wiring a transistor selected from a plurality of P-type transistors. The second output driver is configured by wiring a transistor selected from a plurality of N-type transistors.

Another aspect of the present invention is a master slice type semiconductor device in which a large number of transistors are previously formed on a semiconductor substrate and transistors selected from the large number of transistors are connected by wiring. Each of the transistors has a gate electrode formed on the semiconductor substrate via a gate insulating film, and two diffusion regions formed on the semiconductor substrate on both sides of the gate electrode, At least one of the transistors is characterized in that one of the two diffusion regions is divided into a plurality of divided diffusion regions in a gate width direction of the gate electrode.

In another embodiment of the present invention, the transistor having the divided diffusion region is not limited to the transistor arranged in the input / output cell, but may be arranged in the internal cell or the like.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a plan view of the semiconductor device of the present embodiment, in which an input / output cell region 4 is arranged around a central internal cell region 2. Each cell 4A in the input / output cell area 4
Can be selectively used as input cells, output cells, or input / output cells having both functions by wiring to a plurality of transistors disposed therein.

FIG. 6 shows an output cell 10 which is one of the plurality of cells 4A shown in FIG.

The output cell 10 has an output terminal 12 and
P-type output driver 14 composed of a P-type transistor connected between output terminal 12 and VDD potential supply line
And an N-type output driver 16 composed of an N-type transistor connected between the output terminal 12 and the VSS potential supply line.
And In FIG. 6, an electrostatic protection circuit and the like are omitted.

When outputting a logic HIGH from the output terminal 12, the P-type output driver 14 is turned on, and when outputting a logic LOW from the output terminal 12, the N-type output driver 16 is turned on. Then, the abilities of the P-type and N-type output drivers 14 and 16 are set to the abilities that meet the requirements of the customer. For this purpose, each of the P-type and N-type output drivers 14 and 16 is configured by connecting a plurality of transistors in parallel or wiring only one transistor according to the current driving capability required by the customer.

FIG. 1 shows a group of MOS transistors on a semiconductor substrate in a region of each cell 4A shown in FIG. 5, and shows a state of a bulk substrate not yet wired. In FIG. 1, a plurality of, for example, five gate electrodes 22A to 22E are provided in an N-type well region 20 of a semiconductor substrate via a gate insulating film (not shown). In the semiconductor substrate on both sides of each of the gate electrodes 22A to 22E, for example, impurity diffusion regions 24A to 24F self-aligned by the gate electrodes 22A to 22E are provided. The impurity diffusion regions 24A to 24F form the source S or the drain D by the subsequent wiring. The five gate electrodes 22A to 22E have a reference size width Wp.

On the other hand, similarly, for example, five gate electrodes 32A to 32E are formed in the P-type well region 30 of the semiconductor substrate.
Impurity diffusion regions 34A to 34F provided in the semiconductor substrate on both sides of each of the gate electrodes 32A to 32E are provided. Since the N-type transistor has higher performance than the P-type transistor, the width Wn of the reference size of the gate electrodes 32A to 32E is equal to the width W of the gate electrodes 22A to 22E.
It is formed narrower than p.

In FIG. 1, the direction indicated by reference numeral 40 is defined as the gate width direction, and the direction indicated by reference numeral 42 is defined as the gate length direction. As a feature of this embodiment, the endmost impurity diffusion region 24F located on the right side of the gate electrode 22E has a plurality of, for example, three divided diffusion regions 26 in the gate width direction 40.
A, 26B and 26C. These three divided diffusion regions 26A, 26B, and 26C are separated by forming an element isolation insulating film 28 therebetween. Note that the element isolation insulating film 28 is also formed in the impurity diffusion region 24E on the left side of the gate electrode 22E. However, in the impurity diffusion region 24E, the element isolation insulating film 28 is not formed over the length in the gate length direction 42, and is not formed in the gate width direction 40E.
A continuous region along the line remains.

Similarly, the impurity diffusion region 34F on the right side of the gate electrode 32E is also divided into a plurality of, for example, three divided diffusion regions 36 in the gate width direction 40 by the element isolation insulating film 38.
A, 36B and 36C. Gate electrode 32
A part of the impurity diffusion region 34E on the left side of E is also separated by the element isolation insulating film 38.

Here, the divided diffusion areas 26A, 26B, 2
The width of each part of the gate electrode 22E corresponding to 6C is Wpd. Similarly, the divided diffusion areas 36A, 36B,
The width of each part of the gate electrode 32E corresponding to 36C is Wnd
And

As shown in FIG. 1, the gate electrodes 22A to 22A
2E and impurity diffusion regions on both sides thereof constitute P-type transistors Qp1 to Qp4. The gate width of these P-type transistors Qp1 to Qp4 is Wp, and the width of the impurity diffusion regions serving as the source and drain is wide as in the gate width, so that a large output current can flow. Therefore, the P-type transistors Qp1 to Qp4 can be used when configuring an output driver having a large current driving capability.

The gate electrode 22E and the impurity diffusion regions on both sides thereof form three P-type transistors Qp5 to Qp.
7 is configured. Each of P-type transistors Qp5 to Qp7 has a gate width of Wpd, and can flow a small current. Therefore, the P-type transistors Qp5 to Qp
7 can be used when configuring an output driver having a small current driving capability.

Similarly, the gate electrodes 32A to 32A shown in FIG.
N-type transistors Qn1 to Qn4 are composed of 2E and impurity diffusion regions on both sides thereof. The gate width of these N-type transistors Qn1 to Qpn is Wn, and the width of the impurity diffusion regions serving as the source and drain is wide as in the gate width, so that a large output current can flow. Therefore, the N-type transistors Qn1 to Qn4 can be used when configuring an output driver having a large current driving capability.

The gate electrode 32E and the impurity diffusion regions on both sides thereof form three N-type transistors Qn5 to Qn.
7 is configured. Each of N-type transistors Qn5 to Qn7 has a gate width of Wnd and can flow a small current. Therefore, the N-type transistors Qn5 to Qn
7 can be used when configuring an output driver having a small current driving capability.

As described above, most of the area of the input / output cell is occupied by the transistors constituting the output driver. Therefore, the reference size of each transistor constituting the output driver is determined, and this is prepared in a library. If an output driver having a higher driving capability than the individual transistors is required, a plurality of reference size transistors may be connected in parallel. On the other hand, there is a case where a transistor having a smaller driving capacity than a transistor of the reference size is required. For this reason, the widths Wp and Wn of the gate electrodes are set to a reference size, and a slit having an element isolation insulating film is inserted into the impurity diffusion region to divide the gate electrode, thereby forming a transistor having a smaller driving capability.

Next, FIG. 2 shows an example of wiring which configures the output driver 14 shown in FIG. 6 by connecting all the P-type transistors Qp1 to Qp7 shown in FIG. 1 in parallel, and FIG. 3 shows an equivalent circuit diagram thereof. Show.

As shown in FIGS. 2 and 3, the sources of the P-type transistors Qp1 to Qp7 are commonly connected to the VDD potential supply line, the drain is commonly connected to the output terminal 12, and the gate is common to the gate terminal 18. It is connected. At this time, the P-type transistor Qp1 connected in parallel
Qp7 is equivalent to one P-type transistor having a gate width of (4 × Wp + 3 × Wpd), and the current driving capability is maximized.

FIG. 4 shows the P-type transistor Qp shown in FIG.
5 shows an example in which only 5 is connected. In this case, since the gate width of P-type transistor Qp5 is Wpd, the current driving capability is minimized.

Here, in FIGS. 1, 2 and 4, the width Wi of the element isolation insulating films 28 and 38 is drawn wide for convenience of explanation, but actually, with respect to the reference gate widths Wp and Wn. The width Wi of the element isolation insulating films 28 and 38 can be reduced to a negligible extent. In fact, the gate width Wp is 72 μm
Then, the width Wi of the element isolation insulating film 28 can be reduced to about 1 μm. Under such conditions, 3 × Wpd ≒ Wp
It can be.

Here, the P-type transistor Qp shown in FIG.
The following table shows the current driving capability of the P-type output driver 14 configured by changing the connection target selected from 1 to Qp7. In the following table, the current driving capability ratio of another connection example with respect to the connection example shown in FIG. 2 is shown.

[0040]

[Table 1]

As described above, the three divided diffusion regions 26A to 26A
If the width of 26C is set to be equal, the P-type output driver 14 having various current driving capabilities as shown in the above table can be constituted by wiring. The N-type output driver 16 can be similarly configured.

Next, the point that the above embodiment can reduce the chip area will be described with reference to a comparative example shown in FIG. In FIG. 7, members having the same functions as in FIG. 1 are denoted by the same reference numerals as in FIG. FIG. 7 shows only a transistor group forming the P-type output driver 14 shown in FIG.

FIG. 7 is the same as FIG. 1 in that P-type transistors Qp1 to Qp4 are constituted by four gate electrodes 22A to 22D each having a gate width Wp and impurity diffusion regions on both sides thereof. It is. Further, in FIG.
Two P-type transistors Qp having gate width Wpd
5, Qp6. However, these two P-type transistors Qp5 and Qp6 do not use a divided diffusion region obtained by dividing an impurity diffusion region as shown in FIG.
As shown in FIG. 7, they are formed in separate regions 50.

Even in the structure shown in FIG. 7, there is no difference in that the P-type output driver 14 having various driving capabilities can be configured by changing the combination of transistors connected in parallel. However, as is clear from the comparison of the area of each PMOS region between FIG. 1 and FIG.
The structure shown in (1) requires less area.

[Brief description of the drawings]

FIG. 1 is a plan view showing a part of a master slice type semiconductor device according to an embodiment of the present invention in a state of a bulk substrate before wiring.

FIG. 2 is a plan view showing a wiring example in which the transistors shown in FIG. 1 are connected to form an output driver having a high current driving capability.

FIG. 3 is an equivalent circuit diagram of the configuration shown in FIG.

FIG. 4 is a plan view showing a wiring example in which the transistors shown in FIG. 1 are connected to form an output driver having a low current driving capability.

FIG. 5 is a plan view of a semiconductor device according to one embodiment of the present invention.

6 is an equivalent circuit diagram of an output driver in one output cell shown in FIG.

FIG. 7 is a plan view of a part of a semiconductor device according to a comparative example of the present invention.

[Explanation of symbols]

2 Internal cell area 4 Input / output cell area 12 Output terminal 14 P-type output driver 16 N-type output driver 18 Gate terminal 20 N-type well area 22A to 22E Gate electrode 24A to 24F Impurity diffusion area 26A to 26C Split diffusion area 28 Element isolation Insulating film 30 P-type well region 32A-32E Gate electrode 34A-34F Impurity diffusion region 36A-36C Divided diffusion region 38 Element isolation insulating film 40 Gate width direction 42 Gate length direction 50 Impurity diffusion region Qp1-Qp4 P with large current driving capability -Type transistors Qp5 to Qp7 P-type transistors with small current driving capability Qn1 to Qn4 N-type transistors with large current driving capability Qn5 to Qn7 N-type transistors with small current driving capability

Claims (14)

[Claims] In a master slice type semiconductor device in which a large number of transistors are previously formed on a semiconductor substrate and transistors selected from the large number of transistors are connected by wiring, an input / output provided in a peripheral region is provided. A cell region and an internal cell region provided inside the input / output cell region, a plurality of output cells are arranged in the input / output cell region, and each of the plurality of output cells has an output terminal and A plurality of transistors are arranged, a transistor selected from the plurality of transistors is connected to the output terminal, and each of the plurality of transistors is formed on the semiconductor substrate via a gate insulating film. A gate electrode and two diffusion regions formed on the semiconductor substrate on both sides of the gate electrode. Also one to a semiconductor device wherein the one of the two diffusion regions, characterized in that it is divided into a plurality of divided diffusion region with a gate width direction of the gate electrode. 2. The semiconductor device according to claim 1, wherein an element isolation region is disposed between two adjacent divided diffusion regions. 3. The device according to claim 2, wherein the other of the two diffusion regions sandwiching the gate electrode is:
A semiconductor device, wherein a region near the gate electrode is a region divided by the element isolation region, and a region other than the divided region is continuous along the gate width direction. 4. The semiconductor device according to claim 2, wherein the element isolation region is formed of an element isolation insulating film. 5. The transistor according to claim 1, wherein gate electrodes of the plurality of transistors are arranged in parallel, and an impurity diffusion region between the two gate electrodes is a common source or a common source of the two transistors. A semiconductor device comprising a drain. 6. The semiconductor device according to claim 5, wherein the plurality of divided diffusion regions are formed in an endmost impurity diffusion region. 7. The transistor according to claim 1, wherein the divided diffusion region having a minimum width, together with the gate electrode and the other diffusion region, constitutes a transistor having a minimum current driving capability. Semiconductor device. 8. The semiconductor device according to claim 7, wherein each of the plurality of divided diffusion regions has an equal width. 9. The semiconductor device according to claim 7, wherein each of the plurality of divided diffusion regions has a different width. 10. The at least one of the plurality of output cells according to claim 1, wherein at least one of the plurality of divided diffusion regions is a drain region connected to the output terminal by the wiring. A semiconductor device, comprising: 11. The device according to claim 1, wherein each of the plurality of output cells includes: a first output driver disposed between the output terminal and a VDD potential supply line; A second output driver disposed between the first and second output drivers and a VSS potential supply line, wherein each of the first and second output drivers includes the plurality of transistors. 12. The semiconductor device according to claim 11, wherein the first output driver is configured by wiring a transistor selected from a plurality of P-type transistors. 13. The semiconductor device according to claim 11, wherein the second output driver is configured by wiring a transistor selected from a plurality of N-type transistors. 14. A master slice type semiconductor device in which a number of transistors are formed in advance on a semiconductor substrate, and transistors selected from the number of transistors are connected by wiring, wherein each of the number of transistors is: A gate electrode formed on the semiconductor substrate via a gate insulating film, and two diffusion regions formed on the semiconductor substrate on both sides of the gate electrode, and at least one of the transistors A semiconductor device, wherein one of the two diffusion regions is divided into a plurality of divided diffusion regions in a gate width direction of the gate electrode.