JP2001077372A - Thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a top gate stagger type thin film transistor (TF) capable of reducing leakage current with a simple structure.
T). A source electrode disposed on a substrate is provided.
02 and the drain electrode 103, a semiconductor layer 100, insulating layers 106 and 106A, and a gate electrode 107 are sequentially formed, and the semiconductor layer 100 is disposed on the amorphous silicon layer 104 and the amorphous silicon layer 104. A stacked structure including the polycrystalline silicon layer 105 is employed. Further, the thickness of the amorphous silicon layer 104 is
The thickness is specified for the polycrystalline silicon layer 105.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a thin film transistor (TFT), and more particularly to a thin film transistor using polycrystalline silicon as a semiconductor layer.

[0002]

2. Description of the Related Art Conventionally, a large number of thin film transistors (hereinafter, referred to as TFTs) have been used for driving circuits of liquid crystal display elements, EL display elements, image sensors, and the like. And
A polycrystalline silicon layer is formed on the TFT, and such a polycrystalline silicon layer can be formed by a solid phase growth method, a laser annealing method, a vapor phase growth method, or the like. Here, in the solid phase growth method, after depositing amorphous silicon on a substrate, annealing is carried out for a long time to form a polycrystalline silicon layer by a solid phase reaction. In the laser annealing method, high-power laser is used to perform annealing in a short time.

On the other hand, in the vapor phase growth method, plasma or light energy is added to a source gas such as SiH ₄ (in some cases, an etching gas containing F or Cl is added) to cause a decomposition reaction. A polycrystalline silicon layer is directly deposited on a substrate. This vapor phase growth method is advantageous in terms of cost and throughput because no annealing step is used.

Incidentally, a TFT having such a polycrystalline silicon layer includes a planar type polycrystalline silicon TF.
T and a top gate stagger type polycrystalline silicon TFT. Here, the planar type polycrystalline silicon TFT is:
A source / drain, an insulating film, and a gate electrode are formed on an upper surface of polycrystalline silicon deposited on a substrate.
In addition, top gate stagger type polycrystalline silicon TFT
Is the n ⁺ Si on the metal source / drain electrodes on the substrate.
Are stacked, and a polycrystalline silicon semiconductor layer is formed thereon.

[0005]

However, in such a conventional TFT, the planar type TFT has a polycrystalline silicon layer because a source / drain and a gate electrode are formed on the upper surface of the polycrystalline silicon film. Leakage current flowing through it cannot be ignored. Therefore, an LDD (lightly doped drain) is formed using ion implantation,
The double gate method in which two gate electrodes are provided in series is adopted, but these have disadvantages such as an increase in cost and element size.

On the other hand, there is a similar problem in a top gate stagger type TFT, and a bottom gate inverted stagger type TF having a structure opposite to that of the top gate stagger type TFT.
T has the same problem.

By the way, as a method of solving this,
In a bottom-gate inverted stagger type TFT, an attempt to reduce the leak current by laminating SiC on a polycrystalline silicon layer has been made by K. Kobayashi et al. S. Choi (Proceedings of the Japan Society of Applied Physics 19
96. Spring p. 801). However, this has a problem that it is difficult to obtain a good quality SiC film with few defects.

[0008] H. Kakinuma (JAP)
70 (12) 15, Dec., 1991, p. 7374)
Are polycrystalline silicon films formed by the plasma CVD method.
It is reported that the lower part of the film is amorphous or microcrystalline and the upper part of the film is polycrystalline, but there is no concept of controlling the thickness and band gap of the amorphous layer. Not optimized.

Therefore, even if this is applied to a top gate stagger type TFT, no special effect is obtained.

Accordingly, the present invention has been made in view of such circumstances, and it is an object of the present invention to provide a top gate stagger type TFT (thin film transistor) capable of reducing leakage current with a simple structure. Things.

[0011]

According to the present invention, there is provided a top gate stagger type thin film transistor in which a source electrode and a drain electrode are arranged on a substrate, and a semiconductor layer, an insulating layer and a gate electrode are sequentially formed on the electrodes. And
The semiconductor layer may have a laminated structure including an amorphous silicon layer and a polycrystalline silicon layer disposed on the amorphous silicon layer.

Further, the present invention is characterized in that the thickness of the amorphous silicon layer is equal to or greater than the thickness of the polycrystalline silicon layer.

Further, the present invention is characterized in that the layer thickness of the amorphous silicon layer is 1 to 4 times the layer thickness of the polycrystalline silicon layer.

Further, according to the present invention, B is mixed with the amorphous silicon layer and the concentration of B is 5 × 10
It is characterized by being ¹⁸ or less.

According to the present invention, a semiconductor layer, an insulating layer and a gate electrode are sequentially formed on a source electrode and a drain electrode disposed on a substrate, and the semiconductor layer is formed of an amorphous silicon layer and an amorphous silicon layer. It has a laminated structure including a polycrystalline silicon layer disposed on the silicon layer.
Further, the thickness of the amorphous silicon layer is set to a thickness specified for the polycrystalline silicon layer.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of a top gate stagger type TFT according to an embodiment of the present invention. In FIG. 1, reference numeral 101 denotes a glass substrate, and 102 and 103 denote Ta and n on the glass substrate 101. A source electrode and a drain electrode formed by laminating ⁺ Si.

Further, 100 is an amorphous silicon layer 1
04 and a polycrystalline silicon layer 105. The semiconductor layer 100 has a plasma C
It is formed by continuously depositing amorphous silicon and polycrystalline silicon by VD and then etching the amorphous silicon and polycrystalline silicon into islands by photolithography.

Reference numeral 106 denotes a SiN layer on the semiconductor layer 100.
x, a first gate insulating film formed by laminating x, 106A
Is a second gate insulating film formed by stacking SiNx to insulate the side walls of the semiconductor layer 100 and the first gate insulating film 106, and 107 is a gate electrode formed on the second gate insulating film 106A. It is.

When forming the semiconductor layer 100,
As described above, when polycrystalline silicon is deposited on amorphous silicon by plasma CVD, the particle size of polycrystalline silicon increases continuously with an increase in layer thickness. Becomes Therefore, in the TFT according to the present embodiment,
The semiconductor layer 100 has a structure in which the band gap continuously increases toward the interface on the opposite side from the channel.

Therefore, in the present embodiment, an amorphous silicon layer 104 having a wide band gap is deposited on the n ⁺ Si of the source / drain electrodes to a thickness equal to or greater than a certain specified thickness. The leakage current flowing through the outer semiconductor layer 100 is reduced, and the electrical characteristics of the TFT can be improved. This also simplifies the structure of the TFT and improves the yield.

Next, a method of manufacturing a TFT having such a structure will be described.

First, as shown in FIG. 2A, Mo, Ni, Ta, Cu, and A are formed on a substrate 101 made of high-melting glass, quartz, ceramic, or the like by sputtering or vacuum evaporation.
is deposited at 1000 to 3000 °. Further, an n ⁺ Si film having a thickness of 1000 to 1000
3000Å is deposited. Then, after forming a pattern with a resist thereon, etching is performed by a combination of RIE and wet etching, so that a source electrode 102 and a drain electrode 103 are formed.

Next, an amorphous silicon layer 104 is formed again by the CVD method as shown in FIG. The thickness of the amorphous silicon layer 104 is generally 50
It is 0 to 3000 °, preferably 1000 to 2000 °.

Here, the conditions for forming the amorphous silicon layer 104 are a relatively low power density, a high reaction pressure, and a low hydrogen dilution.
01-1 W / cm ² , desirably 0.05-0.3 W /
cm ² , and the reaction pressure is generally 0.5-2 to
rr, preferably 0.8 to 1.5 torr. In addition, SiH ₄ , SiH ₂ Cl ₂ , Si
F ₄ , SiH ₂ F ₂ , and H ₂ or an inert gas are used as a diluting gas. The H ₂ dilution ratio of the silicon source gas is
Generally, it is 0 to 30%, preferably 0 to 10%.

The amorphous silicon layer 104 may be mixed with B as a dopant, and BF ₃ and B ₂ H ₆ can be used as a doping gas. The doping amount is generally 1 × 10 ⁻¹⁹ atm / cm ³ or less, preferably 1 × 10 ⁻¹⁷ to 2 × 10 ⁻¹⁸ atm / c.
m is ^3.

Next, a polycrystalline silicon layer 105 is formed by the CVD method as shown in FIG. The thickness of the polycrystalline silicon layer 105 is generally 200 to 2000 Å,
Desirably, it is 400 to 1000 °.

Here, the conditions for forming the polycrystalline silicon layer 105 are relatively high power density, low reaction pressure and high hydrogen dilution, and the RF power density is generally 0.1.
１1 W / cm ² , desirably 0.2 to 0.8 W / cm <sup>2
2. The</sup> reaction pressure is generally 0.2 to 1.5 to
rr, desirably 0.3 to 1.2 torr. The source gas is SiH ₄ , SiH ₂ Cl ₂ , SiF ₄ ,
SiH ₂ F ₂ , H ₂ or an inert gas is used as a diluting gas. The H ₂ dilution ratio of the silicon-based source gas is generally 0 to 95%, preferably 50 to 80%.

Next, as shown in FIG. 3A, the first layer is formed on the semiconductor layer 100 including the amorphous silicon layer 104 and the polycrystalline silicon layer 105 by the CVD method.
Is formed. Note that the thickness of the first gate insulating film 106 is 500 to 3000 °. Here, as the first gate insulating film 106,
SiO ₂ or SiN is used. The SiO ₂ and SiN are mixed gas of TEOS and O ₂ , SiH ₄ , NH ₃
Then, the first gate insulating film 106 is formed by patterning by a photolithography technique and isolating by RIE from a mixed gas of N ₂ and N ₂ .

Next, as shown in FIG. 2B, after depositing SiO ₂ or SiN so as to cover the amorphous silicon layer 104, the polycrystalline silicon layer 105, and the first gate insulating film 106, the thickness is 500 to 3000 °. Of the second gate insulating film 106A is formed. Note that such an insulating film 10
In the case of forming the first and second gate insulating films 106A and 106A, the first gate insulating film 106 of the first layer may be omitted and only the second gate insulating film 106A may be formed as shown in FIG.

Finally, Al, Cr, Ti, Mo,
Thickness of 3000 to 600 depending on Ta or their laminated films
The gate electrode 107 shown in FIG. 1 (or FIG. 4) at 0 ° is formed.

FIG. 5 shows a TF having the structure shown in FIG.
4 shows the relationship between the thickness of the amorphous silicon and the OFF current of the TFT when the polycrystalline silicon 105 is laminated on the amorphous silicon layer 104 in T.

It should be noted that the TFT shown in FIG.
After forming a source electrode 102 and a drain electrode 103 by laminating Ta and n ⁺ Si on the semiconductor layer 01, a semiconductor layer 100 including an amorphous silicon layer 104 and a polycrystalline silicon layer 105 is formed, and then a second layer is formed by SiNx. A gate insulating film 106A is formed, and finally, a gate electrode 107 is formed of a Ta / Al laminated film.

Here, the thickness of the polycrystalline silicon layer 105 used for the semiconductor layer 100 was 1000 °, and the average grain size measured by X-ray diffraction was 120 °. The TFT had a gate width of 50 μm and a channel length of 5 μm. And
As is clear from FIG. 5, the amorphous silicon layer 104
Is more than a certain level (1000 mm or more)
It turns out that OFF current falls.

FIG. 6 shows an amorphous silicon layer 10.
4 shows the relationship between the thickness of the amorphous silicon layer 4 and the ON current. As is clear from the figure, it can be seen that the current value tends to sharply decrease when the thickness of the amorphous silicon layer 104 is around 4000 °.

FIG. 7 shows a case where the thickness of the polycrystalline silicon layer 105 is 1000 ° and the thickness of the amorphous silicon layer 104 is 1500 °, and the amount of B doped in the amorphous silicon layer (quantified by SIMS) is changed. O
It is a plot of the ratio between the N current and the OFF current. As is clear from the figure, the ratio of the ON current to the OFF current is
It can be seen that the maximum is obtained when the doping amount of B is 5 × 10 ¹⁸ .

It is known that doped B has an effect of improving the crystallinity of polycrystal. On the other hand, excess B increases the carrier density, so that the resistivity is considered to decrease.

As apparent from these experiments, when the thickness of the polycrystalline silicon layer 105 is 1000 Å, the thickness of the amorphous silicon layer 104 is 1000 Å.
As described above, when the thickness is 4000 ° or less, the layer thickness of the amorphous silicon layer 104 is one of the layer thickness of the polycrystalline silicon layer 105.
In the case of up to four times, the values of the ON current and the OFF current sharply decrease, and the leak current decreases accordingly. Further, by mixing B as a dopant in the amorphous silicon layer and setting the concentration of B to 5 × 10 ¹⁸ or less, the ratio between the ON current and the OFF current can be maximized.

Next, an example of this embodiment will be described. [Embodiment 1] In the embodiment, Ta of 1000 ° was deposited on a glass substrate 101, and n ⁺ Si was deposited thereon of 1000 ° by plasma CVD, and a source electrode 102 and a drain electrode 103 were formed by photolithography. (See FIG. 2A). The parameters for producing n ⁺ Si at this time were as follows.

Substrate size 300 × 300 mm Substrate temperature 350 ° C. RF power 0.2 W / cm ² Pressure 1.2 torr SiH ₄ 250 sccm PH ₃ 500 sccm H ₂ 1000 sccm Further, the source electrode 102 and the drain electrode 103 are amorphously formed on the source electrode 102 and the drain electrode 103 by plasma CVD. A silicon layer, a polycrystalline silicon layer, and a SiO ₂ layer were successively deposited. The production parameters at this time were as follows.

(Amorphous silicon layer) Substrate temperature 380 ° C. RF power 0.18 W / cm ² Pressure 1.0 torr SiH ₄ 230 sccm H ₂ 2500 sccm BF ₃ (100 ppm) / H ₂ 20 sccm Film thickness 1200 ° (polycrystalline crystal layer) a substrate temperature of 380 ° C. RF power 0.9 W / cm ² pressure _{1.2torr SiH 4 20sccm SiF 4 60sccm H} 2 1000sccm thickness 800 Å (SiO ₂ layer) substrate temperature 400 ° C. RF power 1.1 W / cm ² pressure 0. 8 torr TEOS 180 sccm O ₂ 3500 sccm He 100 sccm film thickness 1000Å This laminated film is etched into an island shape by photolithography and RIE to form an amorphous silicon layer 104.
Semiconductor layer 100 composed of silicon and polycrystalline silicon layer 105
Then, a first gate insulating film 106 is formed (see FIG. 3A).

Next, the island-shaped semiconductor layer 100 and the first
In order to insulate the side wall of the gate insulating film 106, a SiNx film is deposited at 2000 ° by CVD, and then etched to form a second gate insulating film 106A (see FIG. 3B). Finally, Ta / Al , 500/6000 ° metal film is deposited, and the gate electrode 10 is wet-etched.
7 was formed (see FIG. 1).

When the electrical characteristics of the TFT thus formed were measured, the mobility was 16 cm ² / Vs
And ON / OF when the drain current is saturated and at the minimum
The F ratio was 6 digits.

Comparative Example 1 In this comparative example, an amorphous silicon layer 104 was formed as a semiconductor layer with a thickness of 300 ° under the same conditions as the amorphous silicon layer of Example 1. All other configurations were the same as in the first embodiment. In the case of Comparative Example 1, the completed TFT did not operate due to disconnection of the semiconductor layer.

Comparative Example 2 In this comparative example, the amorphous silicon 104 was omitted, and the polycrystalline silicon layer 10 was omitted.
5 under the same conditions as the polycrystalline silicon layer of Example 1 and a film thickness of 200
It was formed at 0 °. All other configurations were the same as in the first embodiment. In the case of Comparative Example 2, the completed TFT
When the electrical characteristics of the sample were measured, the mobility was 8 cm ² / Vs and the ON / OFF ratio was three digits.

[Embodiment 2] In this embodiment, the first gate insulating film 106 is omitted (see FIG. 4). All other configurations were the same as in the first embodiment. Then, in the case of Example 2, when the electrical characteristics of the completed TFT were measured, the mobility was 11 cm ² / Vs and the ON / O
The FF ratio was 4 digits.

[Embodiment 3] In the present embodiment, the first gate insulating film 106 is made of a SiNx film 1000 # under the same conditions as the second insulating film 106A. All other configurations were the same as in the first embodiment. Then, in the case of the third embodiment,
When the electrical characteristics of the completed TFT were measured, the mobility was 15 cm ² / Vs and the ON / OFF ratio was 5 digits.

Embodiment 4 In this embodiment, the thickness of the amorphous silicon film 104 was set to 800 °. All other configurations were the same as those of the third embodiment. In the case of Example 4, when the electrical characteristics of the completed TFT were measured, the mobility was 12 cm ² / Vs and the ON / OFF ratio was four digits.

Embodiment 5 In this embodiment, the thickness of the semiconductor layer 105 is set to 2000 °. All other configurations were the same as in the first embodiment. In the case of Example 5, when the electrical characteristics of the completed TFT were measured, the mobility was 1
At 0 cm ² / Vs, the ON / OFF ratio was 5 digits.

Example 6 In this example, a liquid crystal display device was formed using the TFT of the present invention. FIG. 8 shows a part of a cross section of a liquid crystal display device using such a TFT. In the figure, reference numeral 602 denotes a substrate 601a
The TFT 602 is provided above, and is manufactured by, for example, the same configuration as that of the first embodiment.

Here, in this liquid crystal display element, T
2 μm-thick acrylic planarization film 60 on FT 602
3 (PC403 manufactured by JSR), a contact hole 610 is formed, and thereafter, a layer thickness of 90 is formed by ITO.
A pixel electrode 604 of 0 ° is formed. Note that a polyimide alignment film 605 (CRD6 manufactured by Sumitomo Bakelite) 100% is applied on the pixel electrode 604.

The counter substrate 601 of this liquid crystal display element
b, a common electrode 6 having a thickness of 700.
07, the polyimide alignment film 608 is
Coated.

Then, rubbing is performed on both substrates 601a and 601b so that the rubbing directions are antiparallel to each other, and silica beads 606 having an average particle size of 2 μm are dispersed as spacers, and then bonded together with a sealing material 609. Was prepared and injected at a temperature of an isotropic phase.

[0054]

Embedded image The physical properties of the liquid crystal composition 611 are as follows.

[0055] Spontaneous polarization (30 ° C.): Ps = 1.2 nC / cm ² Cone angle (30 ° C.): Θ = 24.1 ° SmC ^* Spiral pitch in phase (30 ° C.): 20 μm or more And this liquid crystal composition 611 Cooling was performed to a temperature at which a chiral smectic liquid crystal phase was exhibited. At this time, a cooling process was performed by applying an offset voltage of -5 V before and after the Ch-SmC * phase transition.

The pixel size is 300 μm × 100 μm, T
The FT size was L / W = 6 μm / 20 μm. In addition, despite the spontaneous polarization of the liquid crystal composition 611 being 1.2 nC and the cell gap being as narrow as 2 μm, the liquid crystal display element was driven despite the antiferroelectric liquid crystal having a large load capacitance. It worked. Also,
The contrast was 120.

As described above, by applying the TFT according to the present embodiment to a liquid crystal display device, it becomes possible to drive an antiferroelectric liquid crystal having a large load at a high speed.

[0058]

As described above, according to the present invention, the semiconductor layer has a laminated structure composed of an amorphous silicon layer and a polycrystalline silicon layer disposed on the amorphous silicon layer. The leak current can be reduced with a simple structure.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view of a top gate stagger type TFT according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a part of a method of manufacturing the TFT.

FIG. 3 is a diagram illustrating another part of the method for manufacturing the TFT.

FIG. 4 is a diagram showing another configuration of the TFT.

FIG. 5 is a diagram showing the relationship between the thickness of an amorphous silicon layer and the OFF current in a TFT having another configuration.

FIG. 6 is a diagram showing the relationship between the thickness of an amorphous silicon layer and the on-state current in a TFT having another configuration.

FIG. 7 is a diagram showing a relationship between a B concentration in an amorphous silicon layer and an on / off current ratio in a TFT having another configuration.

FIG. 8 is a diagram showing a cross-sectional structure of a liquid crystal display element using the TFT.

[Explanation of symbols]

 Reference Signs List 100 semiconductor layer 101 glass substrate 102 source electrode 103 drain electrode 104 amorphous silicon 105 polycrystalline silicon 106 first insulating film 106A second insulating film 107 gate electrode 602 TFT 611 liquid crystal

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 HA28 JA25 KA04 KA05 MA07 MA13 MA29 MA30 NA25 NA26 PA01 5F110 AA05 AA06 CC05 DD02 DD03 EE03 EE04 FF02 FF03 FF09 FF30 GG02 GG13 GG15 GG19 GG24 GG44 QQ05

Claims (4)

[Claims] 1. A top gate stagger type thin film transistor in which a source electrode and a drain electrode are arranged on a substrate, and a semiconductor layer, an insulating layer, and a gate electrode are sequentially formed on the electrodes. A thin film transistor having a laminated structure comprising an amorphous silicon layer and a polycrystalline silicon layer disposed on the amorphous silicon layer. 2. The thin film transistor according to claim 1, wherein the thickness of the amorphous silicon layer is equal to or greater than the thickness of the polycrystalline silicon layer. 3. The thin film transistor according to claim 1, wherein the thickness of the amorphous silicon layer is set to be 1 to 4 times the thickness of the polycrystalline silicon layer. 4. The thin film transistor according to claim 1, wherein B is mixed with the amorphous silicon layer, and the concentration of B is 5 × 10 ¹⁸ or less.