JP2001068978A - Level shifter circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a through-current without the need for increasing the size of transistors(TRs) and to realize high circuit integration without making the circuit configuration complicated. SOLUTION: The level shifter circuit is provided with 1st and 2nd NMOS TRs N1, N2 in pairs whose gates receive complementary input signals whose level is changed between GND and a VDD1 by a 1st inverter INV 1 and whose sources are connected to GND, 1st and 2nd pair PMOS TRs P1, P2 whose sources are connected to a VDD3 and whose gates are in cross connection to drains of the opposed TR, and 3rd and 4th PMOS pair TRs P3, P4 whose gates are connected to a VDD2, whose drains are connected to drains of the 1st and 2nd NMOS TRs and whose sources are connected to the drains of the 1st and 2nd PMOS TRs P1, P2. A relation of VDD3>VDD 2>VDD 1 holds.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shifter circuit for converting one voltage level signal into a different voltage level signal, and more particularly to a level shifter circuit in which the size of a transistor constituting the circuit is reduced.

[0002]

2. Description of the Related Art In recent LSIs (semiconductor integrated circuits),
In order to reduce the power consumption of the LSI, a voltage regulator is provided inside the LSI to generate a voltage lower than an external voltage, and is used as a power supply for the internal LSI. Therefore, when outputting a signal from the inside of the LSI to the outside, it is necessary to make the level the same as the external power supply voltage, and the signal is raised to a high level using a level shifter circuit and then output. FIG. 3 shows a conventional level shifter circuit of this kind. In the figure, INV1 is the first power supply voltage VD of the internal power supply of the LSI.
D1 is a first inverter driven by a PMOS transistor P11 and an NMOS transistor N11.
The OS connection is made, a signal IN is input from the LSI, and an inverted signal thereof is output to the node S1. Also, INV2
Is a second inverter driven by a third power supply voltage VDD3 having the same voltage as the external power supply, connects the PMOS transistor P21 and the NMOS transistor N22 with CMOS, inverts a signal input to the node S3, and outputs the inverted signal as an output OUT. Output. And the inverter IN
A level shifter unit is connected between the output of V1 and the inverter INV3, and the first and second PMs forming a pair with each other are connected.
OS transistors P1, P2 and first and second NMOS
It is composed of transistors N1 and N2.

[0003] That is, the shifter portion is a pair of first shifters.
The gates and drains of the first and second PMOS transistors P1 and P2 are cross-connected to each other, and the respective drains are connected to the respective drains of the first and second NMOS transistors N1 and N2. Each source of the PMOS transistors P1 and P2 is connected to VDD3,
Each source of the OS transistors N1 and N2 is connected to GND. The NMOS transistors N1 and N2
Are connected to the input IN of the first inverter INV1.
And an output node S1. The NMO
The drain of the S transistor N2 is connected to a node S3 which is an input of the second inverter INV2.

The operation of this conventional level shifter circuit is shown in FIG.
Will be described with reference to waveform diagrams of IN, S2, S3, and OUT. When the signal IN is at the GND level, the NMOS transistor P1 and the PMOS transistor P2 are ON and N
The MOS transistor N2 and the PMOS transistor P1 are off. When the signal IN changes from the GND level to VDD1
When the level changes to the level, the NMOS transistor N2 is turned on.
And the signal from IN is supplied to the first inverter INV
1 changes to the GND level and the NMOS transistor N
1 is turned off. At this time, the NMOS transistor N2,
The PMOS transistors P2 are both ON. Since the NMOS transistor P2 has a higher transistor capability than the PMOS transistor P2 (a through current flows at this time), the potential of the node S3 goes to the GND direction. Node S
When the potential of No. 3 goes to the GND direction, the PMOS transistor P1 turns on, the potential of the node S2 becomes VDD3 level, and the PMOS transistor P2 turns off. PM
When the OS transistor P2 is turned off, the potential of the node S3 goes to the GND level, and the signal OUT goes to the VDD3 level.

[0005]

In the operation of such a conventional level shifter circuit, the potentials of the nodes S2 and S3, which are the gate voltages of the PMOS transistors P2 and P1 shown in FIG. 4, are between VDD3 and GND. Since the signal IN is operating, the signal IN changes from GND level to VDD.
When the level changes to one level, both the NMOS transistor N2 and the PMOS transistor P2 are turned on. At this time, the PMOS transistor P2 is placed between VDD3 and GND.
This causes a problem that a large through current flows through the NMOS transistor N2. Such a through current is caused by the NMO
S transistor N1, N2 and PMOS transistor P
This can be suppressed by increasing the capacity ratio between P1 and P2, but this would unnecessarily increase the transistor size, which is not desirable for achieving high integration of LSI. In particular, when the potential difference between VDD1 and VDD3 is large, it is necessary to increase the capability ratio, and the transistor size is further increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a level shifter circuit capable of suppressing a through current without increasing the size of a transistor constituting a shifter portion and suitable for high integration.

[0007]

A level shifter circuit according to the present invention forms a pair in which input signals composed of complementary signals varying between GND and a first power supply voltage VDD1 are respectively input to the gate and the source is connected to GND. The first and second one-conductivity-type MOS transistors and a source connected to a third power supply voltage V
A pair of first and second opposite conductivity type MOS transistors connected to DD3 and having a gate cross-connected to the drain of the opposing transistor, and a gate connected to a second power supply voltage VD
A third pair connected to D2 and having a drain connected to each drain of the first and second one conductivity type MOS transistors and a source connected to each drain of the first and second opposite conductivity type MOS transistors. And a fourth opposite conductivity type MOS transistor, wherein VDD3, VDD
2, VDD1 has an absolute level of VDD3>VDD2> V
DD1 and the first or second one conductivity type M
A level shifter unit that outputs an output signal from the drain of the OS transistor is provided.

For the level shifter, GND and V
A first inverter operating between DD1 and GND and VD
And a second inverter operating between D3 and D3.
The input signal is input to the input terminal of the first inverter, and the input terminal of the first inverter is connected to the first one conductivity type MOS.
An output terminal is connected to a gate of the transistor, and an output terminal is connected to a gate of the second one conductivity type MOS transistor, and a drain of the second one conductivity type MOS transistor is connected to an input terminal of the second inverter. An output signal is output from an output terminal of the second inverter. In addition, the first and second one-conductivity-type MOS transistors and the opposite-conductivity-type MOS transistor are designed to have small capacity ratios.

In the present invention, when the one conductivity type MOS transistor is an NMOS transistor and the opposite conductivity type MOS transistor is a PMOS transistor, the third and fourth PMOS transistors are provided, and VDD2 is applied as the gate voltage of the third and fourth PMOS transistors. By the first and second P
The gate voltage of the MOS transistor is from VDD3 to (VDD
2 + threshold voltage of the third and fourth PMOS transistors) and the gate-source voltage can be kept low, so that the through current can be reduced. Also, when designing a level shifter circuit having a large potential difference, usually, between the first PMOS transistor and the first NMOS transistor, or between the second PMOS transistor and the second NMOS transistor.
Although it was necessary to increase the capacity ratio between the S transistors, in the present invention, since the voltage between the gate and the source of the first and second PMOS transistors is reduced, the capacity ratio can be reduced and the transistor size can be reduced. There is an advantage that you can.

As a technique close to the present invention, Japanese Patent Application Laid-Open
In the level shifter circuit described in JP-A-318055,
Although a configuration in which third and fourth switching elements corresponding to the third and fourth PMOS transistors of the present invention are connected is described, in this prior art, an input is provided to the gates of the third and fourth switching elements. Since the third and fourth switching elements are turned on and off by inputting a control signal formed according to the signal state of the signal, a circuit for generating the control signal is required. It will be complicated. In this regard, in the present invention, VDD2 only needs to be input to the gates of the third and fourth PMOS transistors, and the circuit configuration does not become complicated.

[0011]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a level shifter circuit according to the present invention. The first inverter INV1 and the second inverter INV2 are the same as those in the related art, and the first inverter INV1 is a first power supply voltage V which is an internal power supply of the LSI.
Driven by DD1, the PMOS transistor P11 and NM
The OS transistor N11 is connected to the CMOS, the signal IN is input from the LSI, and the inverted signal is output to the node S1. Further, the second inverter INV2 is driven by a third power supply voltage VDD3 having the same voltage as the external power supply,
PMOS transistor P21 and NMOS transistor N
21 is connected by CMOS, and the signal input to the node S4 is inverted and output as an output OUT. And
A level shifter unit is connected between the output of the first inverter INV1 and the second inverter INV2.

The level shifter includes a pair of first and second PMOS transistors P1 and P2, and a pair of third and fourth PMOS transistors P3 and P4.
And first and second NMOS transistors N1 and N2. The gates and drains of the first and second PMOS transistors P1 and P2 are cross-connected to each other, and each source is connected to the power supply VDD3.
Further, the respective drains are connected to the nodes S2 and S3, that is, the respective sources of the third and fourth PMOS transistors P3 and P4 connected to the second power supply voltage VDD2 by commonly connecting the gates. And the fourth PMOS
The drains of the transistors P3 and P4 are connected to the drains of the first and second NMOS transistors N1 and N2. The sources of the first and second NMOS transistors N1 and N2 are connected to GND, and the gates of the first and second NMOS transistors N1 and N2 are connected to the input terminal of the input IN of the first inverter INV1. Is connected to a contact S1, which is an output. The N
The drain of the MOS transistor N2 is connected to the inverter I
It is connected to node S4, which is the input of NV2. Here, the conditions of the voltage levels of VDD3, VDD2, VDD1, and GND are as follows: VDD3>VDD2>VDD1> GND
Is set to

The operation of the level shifter circuit having the above configuration will be described with reference to the waveforms of the nodes S1, S2, S3, S4 and the output OUT shown in FIG. In the figure, VT 'is the third
And the threshold voltages of the fourth PMOS transistors P3 and P4. When the signal IN is at the GND level and enters a steady state, the NMOS transistor N2 is turned off because the GND level is input to the gate, and the NMOS transistor N1 is turned on because VDD1 is input to the gate. As a result, the PMOS transistors P1 and P3 are turned off, and the PMOS transistors P2 and P3 are turned off.
The MOS transistor P4 turns on. Signal IN is GND
When the level changes from the level to the VDD1 level, the NMOS transistor N2 turns on, and the node S1 goes to the GND level because the signal from IN passes through the inverter INV1, and the NMOS transistor N1 turns off. At this time, the NMOS transistor N2 and the PMOS transistor P
4. Although the PMOS transistor P2 is in the ON state, the potential of the node S3 goes to the level of (VDD2 + VT ') because the NMOS transistor N2 has higher transistor performance than the PMOS transistor P2, and PM
When the OS transistor P1 is turned ON, the potential of the node S2 becomes VD
The level becomes the D3 level, and the PMOS transistor P2 is turned off. When the PMOS transistor P2 is turned off, the node S4
Is at the GND level and the signal at the output OUT is at the VDD3 level.

As described above, the PMOS transistor P is provided between the NMOS transistor N1 and the PMOS transistor P1.
3 by providing a PMOS transistor P4 between the NMOS transistor N2 and the PMOS transistor P2 and applying the power supply VDD2 as a gate voltage of each of the PMOS transistors P4.
As can be seen from the operation waveforms of FIG. 2, the levels of the nodes S2 and S3 as the gate voltages of the PMOS transistors P1 and P2 operate between "VDD3 and (VDD2 + VT ')". The gate voltage is reduced, and the through current at the time of switching the input signal can be reduced. Further, even when the potential difference between the input and output signals is large, the voltage between the gate and the source of the PMOS transistors P1 and P2 can be kept low. Design becomes possible.

Here, it is also possible to adopt a configuration in which the polarity of the potential level in the above embodiment is inverted. In this case, the PMOS transistor of the present invention is replaced by an NMOS transistor, and the NMOS transistor is replaced by a PMOS transistor. It is possible to

[0016]

As described above, the present invention provides a level shifter circuit comprising first and second one conductivity type MOS transistors and first and second opposite conductivity type MOS transistors. And the third and fourth opposite conductivity type MOS transistors are interposed.
VDD2 (VDD3> VDD) is applied to the gate of the S transistor.
2> VDD1), the gate voltages of the first and second opposite conductivity type MOS transistors are VDD3 to (VDD2 + third and fourth opposite conductivity type MO transistors).
(Threshold voltage of the S transistor), and the gate-source voltage can be kept low, so that the through current can be reduced. When designing a level shifter circuit having a large potential difference, the first and second opposite conductivity type MOs are usually used.
Although it was necessary to increase the capacity ratio between the S transistor and the one conductivity type MOS transistor, in the present invention, since the voltage between the gate and the source of the first and second opposite conductivity type MOS transistors is reduced, the capacity The effect that the ratio can be reduced and the transistor size can be designed to be small can also be obtained.
Further, since it is only necessary to supply a constant voltage level (VDD2) to the third and third opposite conductivity type MOS transistors, the circuit configuration does not become complicated.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a level shifter circuit according to an embodiment of the present invention.

FIG. 2 is a waveform chart showing operation waveforms of respective parts of the level shifter circuit of the present invention.

FIG. 3 is a circuit diagram of an example of a conventional level shifter circuit.

FIG. 4 is a waveform diagram showing operation waveforms of various parts of a conventional level shifter circuit.

[Description of Signs] N1 first NMOS transistor N2 second NMOS transistor P1 first PMOS transistor P2 second PMOS transistor P3 third PMOS transistor P4 fourth PMOS transistor N11, N12 NMOS transistors P11, P12 PMOS Transistor INV1 First inverter INV2 Second inverter VDD1 to VDD3 Power supply voltage

Continued on the front page (72) Inventor Kazuyuki Saruwatari 1-403 Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa 53 53 NEC Icy Microcomputer System Co., Ltd.

Claims (4)

[Claims] An input signal composed of a complementary signal that changes between GND and a first power supply voltage (VDD1) is input to a gate and a source is connected to GND. MOS transistor and source is third
And a pair of first and second opposite-conductivity-type MOS transistors whose gates are connected to the drain of the opposite transistor and whose gates are connected to the second power supply voltage (VDD2). A drain is connected to each drain of the first and second one conductivity type MOS transistors, and a source is connected to the first and second opposite conductivity type MOS transistors.
A third pair connected to each drain of the S transistor;
And a fourth opposite conductivity type MOS transistor, wherein the absolute level of VDD3, VDD2, VDD1 is VDDD
A level shifter circuit, wherein D3>VDD2> VDD1, and an output signal is output from a drain of the first or second one-conductivity type MOS transistor. 2. A first device operating between GND and VDD1.
, And a second inverter operating between the GND and VDD3, wherein the input signal is input to an input terminal of the first inverter, and an input terminal of the first inverter is connected to the first terminal. The output terminal is connected to the gate of the one-conductivity-type MOS transistor, and the output terminal is connected to the gate of the second one-conductivity-type MOS transistor.
2. The level shifter circuit according to claim 1, wherein a drain of the S transistor is connected to an input terminal of the second inverter, and outputs an output signal from an output terminal of the second inverter. 3. The first opposite conductivity type MOS transistor, the first one conductivity type MOS transistor, and the second conductivity type MOS transistor.
MOS transistor of opposite conductivity type and second one conductivity type MO
3. The level shifter circuit according to claim 1, wherein the respective performance ratios of the S transistors are designed to be small. 4. The one-conductivity-type MOS transistor is NM.
4. The level shifter circuit according to claim 1, wherein the level shifter circuit is an OS transistor, and the opposite conductivity type MOS transistor is a PMOS transistor.