JP2000331113A - Reconfigurable pseudo analog electric circuit device - Google Patents

Abstract

(57) [Summary] In a reconfigurable pseudo analog electric circuit 10, a first analog signal a is converted into a PWM signal with a zero offset and a second analog signal is converted into a PWM signal with a variable offset. By inputting the two PWM signals to a field programmable gate array (FPGA) 16 and setting the cells 18 in the FPGA 16 and their connections by the computer 22, the FPGA 16 controls the two P signals.
A logical operation of the WM signal is performed, and the operation result is restored to an analog signal by the integration circuit 20, and an output analog signal x is obtained. [Effect] The mode of processing or operation in the FPGA can be appropriately set, and as a result, a reconfigurable pseudo analog electric circuit device can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a quasi-analog electric circuit device, and more particularly to, for example, converting two or more analog signals into a PWM signal and converting the PWM signal into a field programmable gate array.
Gate Array: Hereinafter simply referred to as “FPGA”. ), A novel, reconfigurable pseudo-analog electrical circuit device.

[0002]

2. Description of the Related Art Reconfigurable hardware capable of meeting various requirements of circuit specifications is known. Particularly, in the case of an electric circuit that handles analog electric signals, analog electric elements are often integrated by reconfigurable connection means in order to configure reconfigurable hardware.

[0003]

However, the size of the analog electric element is large, so that only a small analog electric circuit can be constructed.

[0004] It is, therefore, a primary object of the present invention to provide a larger, reconfigurable pseudo-analog electrical circuit device.

[0005]

A reconfigurable pseudo-analog electric circuit device according to the present invention comprises a first pulse width modulating means for pulse width modulating a first analog signal with a fixed offset to output a first PWM signal. Second pulse width modulating means for pulse width modulating the second analog signal with a variable offset to output a second PWM signal, a first PWM signal and a second PWM signal.
Digital arithmetic means for receiving a PWM signal; and conversion means for converting an arithmetic output from the digital arithmetic means into an analog signal to obtain an output analog signal, wherein the digital arithmetic means is a field programmable gate array (FPGA)
And a reconfigurable pseudo analog electric circuit device.

[0006]

The first pulse width modulating means pulse width modulates the first analog signal with a fixed offset (for example, offset = 0) to output a first PWM signal. In contrast, the second
The pulse width modulation means converts the second analog signal into a second PWM signal with a variable offset so as to give a temporal fluctuation to the second PWM signal. The digital operation means constituted by the FPGA digitally operates or processes the two PWM signals, so that a digital signal equivalent to the analog operation or processing of the two analog signals is obtained at the output of the FPGA. Is converted into an analog signal by the conversion means to obtain an output analog signal.

In a specific embodiment, the second pulse width modulation means changes the offset value until the offset reaches a maximum value, and the digital operation means changes the first PWM signal and the second PWM signal.
Each time the offset value is changed by the second pulse width modulation means, the WM signal is logically operated to obtain a plurality of logical operation results,
An operation output is obtained by processing a plurality of logical operation results by a predetermined method.

If the predetermined method selects the maximum value among a plurality of logical sum operation results, a signal obtained by adding the first analog signal and the second analog signal can be obtained as an output analog signal.

Further, if the predetermined method is to calculate the average value of a plurality of AND operation results, a signal obtained by integrating the first analog signal and the second analog signal can be obtained as an output analog signal.

[0010]

According to the present invention, since the digital operation means is constituted by the FPGA, the mode of operation or processing in the digital operation means can be changed as appropriate, and therefore, the pseudo analog electric circuit device can be reconfigured. It can be configured as possible. Further, since the size of the gate element constituting the FPGA is smaller than that of a conventional analog electric element, a large-scale analog electric circuit can be formed.

[0011] Other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

[0012]

Referring to FIG. 1, a reconfigurable pseudo-analog electric circuit device 10 of this embodiment includes a PWM circuit 12 for pulse width modulation of a first analog signal and a PWM circuit 12 for pulse width modulation of a second analog signal. The circuit 14 is included. Two P
The first PWM signal and the second PWM signal output from the WM circuits 12 and 14 are input to a field programmable gate array (FPGA) 16.

The FPGA 16 has a plurality of cells 18 arranged in a matrix of, for example, n rows and m columns (both n and m are natural numbers). As shown in FIG. And an input / output port for inputting a signal thereto or outputting a signal therefrom. The input / output ports are provided in four directions, Nin and Nout to the north, Ein and Eout to the east, Sin and Sout to the south, and Win and Wo to the west.
ut are provided respectively. The suffix “in” indicates an input port, and the suffix “out” indicates an output port.

In the cell body 24, not shown,
A digital operation circuit is formed, and the digital operation circuit outputs outputs N, E, S, and W for inputs N, E, S, and W, for example, according to a truth table as shown in FIG. The truth table of each cell 18 may be the same, or may be configured as a different truth table so that different processing can be performed.

Gate circuits are individually incorporated in the input / output ports. By turning on / off each gate circuit, only necessary input ports and / or output ports are activated, and unnecessary gate ports are activated. Input ports and / or output ports can be deactivated. Therefore, for example, the computer 2 shown in FIG.
2 enables any variable connection between multiple cells 18 arranged in a matrix by selectively activating (or deactivating) the input / output ports of each cell 18. That is, by changing the connection between the cells 18 by the computer 22, any processing or operation element (digital operation circuit) can be used in any connection or connection state. Alternatively, the mode of processing can be changed.

The first and second PWM circuits 12 shown in FIG.
And 14 each output a PWM signal as shown in FIG. As is well known, the pulse width modulation converts, for example, a voltage value of an input analog signal into a pulse signal having an on-duty correlated with the voltage value. For example, assuming that an input analog signal in the range of 0V-1V is PWM, an analog signal with a voltage of 0.5V is
A PWM signal having an on-tuty of 50% (the ratio between the ON period and the OFF period is 1: 1) is output.

Further, in the example of FIG. 4, "offset" is illustrated, but this offset is a difference in timing at which the above-mentioned PWM signal is output, and is output by changing this offset time. Time fluctuation can be added to the PWM signal. In the embodiment of FIG.
In the PWM circuit 12, the first analog signal is pulse width modulated with a fixed offset (for example, offset = 0). On the other hand, the PWM 14 modulates the pulse width of the second analog signal with a variable offset so that time fluctuation can be given.

The FPGA 16 has two such PWMs.
Receive a signal. The two PWM signals may be provided to the cell 18 at any position in the FPGA 16. This is because the connection state between the cells 18 can be arbitrarily set or changed by the computer 22. In other words, the processing method in the FPGA 16 can be arbitrarily reconfigured by setting the cells 18 used by the computer 22 and the connections between them. That is, the embodiment of FIG. 1 is a reconfigurable pseudo analog electric circuit device.

Then, the final cell, in the embodiment of FIG.
A digital operation output is obtained in the cell in the rightmost column (Column) and the bottom row (Raw), and the digital operation output is obtained by the integration circuit 20.
Is restored to an analog signal. That is, since the input signal is a PWM signal, its digital operation output is also a PWM signal,
By integrating the signal, the PWM signal can be converted to an analog signal. However, instead of the integration circuit of the embodiment, any other analog conversion means may be used.

The flow chart shown in FIG. 5 shows an operation for configuring the reconfigurable pseudo analog electric circuit device 10 of the embodiment of FIG. 1 as an addition circuit of two input analog signals a and b. Can be achieved by the computer 22 arbitrarily selecting and arbitrarily connecting the cells 18 in the FPGA 16.

In order to add the two analog signals a and b, in step S11, the first PWM circuit 1
According to 2, the analog signal a is pulse-width-modulated at the offset i = 0 according to the equation 1 to obtain the first PWM signal A.

[0022]

A = PWM (a, 0) In the following step S12, the second PWM circuit 14
In accordance with Equation 2, the pulse width of the analog signal b is modulated with an offset i to obtain a second PWM signal B.

[0023]

## EQU2 ## In step S13, the two PWM signals A and B are added (logical sum) to obtain an addition result X [i] as shown in Expression 3.

[0024]

X [i] = A + B [i] In step S14, it is determined whether or not the offset value i has reached the maximum value. If the offset value i has not reached the maximum value, the offset value i is incremented (i = i) in step S15. i + 1), and repeat steps S12-S14. Therefore, when the offset value i reaches the maximum value,
"YES" is determined in the step S14, and the step S1 is performed.
Proceed to 6.

In step S16, the previous step S13
Are obtained by executing
The maximum value Xmax is selected from [i]. 1st PWM
Signal A has a zero offset, and the offset of the second PWM signal is variable. As described above, the PWM signal is a pulse signal having an ON period that is correlated with the magnitude (eg, voltage) of the analog signal. To add two PWM signals means to OR the two PWM signals. The on period of the logical sum result is the addition result of the two PWM signals, and when this is the maximum, it means that the offset value i of the second PWM signal was appropriate.
Therefore, in this embodiment, the maximum value Xmax is used as the addition result.

In the last step S17, the output analog signal x is obtained by integrating the maximum value Xmax by the integration circuit 20.

In the experiment of the inventor, the accuracy of the addition result improves as the offset value i of the second PWM signal is set in smaller increments. For example, when imax = 100, the error is about 1% in the experiment. there were.

The flow chart shown in FIG. 6 shows an operation for configuring the reconfigurable pseudo analog electric circuit device 10 of the embodiment of FIG. 1 as an integrating circuit of two input analog signals a and b. Can be achieved by the computer 22 arbitrarily selecting and arbitrarily connecting the cells 18 in the FPGA 16.

In order to add the two analog signals a and b, in step S21, the first PWM circuit 1
2, the analog signal a is pulse-width-modulated at the offset i = 0 according to the above-described equation 1 to perform the first PWM.
Obtain signal A.

In the following step S22, the second PWM circuit 1
In accordance with Equation (4), the analog signal b is pulse-width-modulated at the offset i and the second signal
Obtain the WM signal B.

Then, in step S23, the two PWM signals A and B are integrated (logical product) as shown in Expression 4.
Then, an integration result X [i] is obtained.

[0032]

X [i] = A * B [i] Further, in step S24, it is determined whether or not the offset value i has reached the maximum value, and if not, the offset value i is incremented in step S25 ( i = i + 1), and repeat steps S22-S24. Therefore, when the offset value i reaches the maximum value,
"YES" is determined in the step S24, and the step S2
Proceed to 6.

In step S26, the previous step S23
Of the integration results X obtained by executing
The average value Xavr of [i] is calculated. As described above, the PWM signal is a pulse signal having an ON period that is correlated with the magnitude (eg, voltage) of the analog signal. 2
Integrating two PWM signals means that two PWM signals
This is to take the logical product of the signals. The on period of the logical product result is the integration result of the two PWM signals, and its average value X
This means that the offset value i of the second PWM signal in avr was appropriate. Therefore, in this embodiment, the average value Xavr is used as the integration result.

Then, in the last step S27, the output analog signal x is obtained by integrating the average value Xavr by the integration circuit 20.

The accuracy of the integration result improves as the offset value i of the second PWM signal is set in finer increments. For example, when imax = 100, the error was about 1-2% in the experiment.

In the above description, it has been specifically described that the pseudo analog addition circuit and the pseudo analog integration circuit can be configured using the reconfigurable pseudo analog electric circuit 10. However, the computer 22
By appropriately setting the cells 18 in the PGA 16 and their connections, it can be easily understood that any other type of processing or operation can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a reconfigurable pseudo analog electric circuit device according to an embodiment of the present invention.

FIG. 2 is an illustrative view showing a cell in the embodiment in FIG. 1;

FIG. 3 is an illustrative view showing one example of a truth table of a cell in the embodiment in FIG. 2;

FIG. 4 is an illustrative view showing an example of a PWM signal output from the PWM circuit in the embodiment in FIG. 1;

FIG. 5 is a flowchart showing an operation when two analog signals are added in the embodiment in FIG. 1;

FIG. 6 is a flowchart showing an operation when integrating two analog signals in the embodiment of FIG. 1;

[Description of Signs] 10 ... Reconfigurable pseudo analog electric circuit 12, 14 ... PWM circuit 16 ... FPGA 18 ... Cell 20 ... Integrating circuit 22 ... Computer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hitoshi Henmi 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Nippon Telegraph and Telephone Corporation (72) Inventor Katsunori Shimohara Daizai Inaya, Seika-cho, Soraku-gun, Kyoto Prefecture No. 5 Hiratani Inside ATR Human Information Communication Research Laboratories

Claims (4)

[Claims] 1. A first pulse width modulation means for pulse width modulating a first analog signal with a fixed offset to output a first PWM signal, and a pulse width modulation of a second analog signal with a variable offset to output a second PWM signal. A second pulse width modulation unit, a digital operation unit that receives the first PWM signal and the second PWM signal, and a conversion unit that converts an operation output from the digital operation unit into an analog signal to obtain an output analog signal; , A reconfigurable pseudo-analog electric circuit device configured with a field programmable gate array. 2. The second pulse width modulation means changes an offset value until the offset reaches a maximum value, and the digital operation means converts the first PWM signal and the second PWM signal into offset values by the second pulse width modulation means. The reconfigurable pseudo-analog electric circuit according to claim 1, wherein a logical operation is performed each time the data is changed to obtain a plurality of logical operation results, and the plurality of logical operation results are processed by a predetermined method to obtain the operation output. apparatus. 3. The signal processing method according to claim 1, wherein the predetermined method is to select a maximum value of the plurality of logical sum operation results, and thereby a signal obtained by adding the first analog signal and the second analog signal as the output analog signal. The reconfigurable quasi-analog electric circuit device according to claim 2, wherein: 4. The method according to claim 1, wherein the predetermined method is to calculate an average value of the plurality of logical product operation results, and thereby a signal obtained by integrating the first analog signal and the second analog signal as the output analog signal. The reconfigurable quasi-analog electrical circuit device of claim 2, wherein