JP2000353948A - ECL latch circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enlarge a noise margin by providing an additional current source circuit for normally flowing a current to a latch part in addition to a constant current source. SOLUTION: An additional current source circuit S1 connected to an emitter side of a transistor Q4 on a latch circuit side consists of, for example, a current mirror circuit and constantly flows a current Iadd of several to 10 percent of its operation current Io to transistors Q3 and Q4. Since the current constantly flows to the transistors Q3, Q4 or the like which constitute the latch part from the additional current source circuit S1, the transistors Q3 and Q4 of the latch part are not completely turned off even switched and a distortion of an output waveform is not caused. In this case, actually the transistors Q3 and Q4 are virtually not turned off because the transistors enter a latch operation state earlier than they are turned on from the state in which they are turned off in accordance with an amount of the additional current, and the distortion of the output waveform is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ECL latch circuit. More specifically, the present invention relates to an ECL latch circuit with an improved noise margin for an output waveform.

[0002]

2. Description of the Related Art As a latch circuit for storing and holding 1-bit digital data of "0" or "1", an ECL latch circuit capable of high-speed operation is known. FIG. 3 is a circuit diagram of a conventional ECL latch circuit. The ECL latch circuit includes a pair of transistors Q1 and Q2 arranged in parallel and constituting a differential amplifier, and a pair of transistors Q3 and Q4 arranged in parallel and constituting a latch unit. A switching transistor Q5 is connected to the emitters of the transistors Q1 and Q2 on the differential amplifier side, and a switching transistor Q6 is similarly connected to the emitters of the transistors Q3 and Q4 on the latch section. A switch circuit is configured. Each transistor Q1-Q
6 each have a parasitic capacitance C. A constant current source So for flowing a constant current Io is connected to the emitters of the transistors Q5 and Q6 constituting the switch circuit. VCC indicates a reference voltage, and VEE indicates a ground potential. RL indicates a load resistance.

FIG. 4 is a signal waveform diagram showing the operation of the ECL latch circuit having the above configuration. Data signal D and its inverted waveform signal D are applied to transistors Q1 and Q2 on the differential amplifier side.
x is input. Transistor Q5, Q of switch circuit
6, a latch pulse signal (clock signal) CK and its inverted signal Ckx are input. As a result, the operation signal Q (= VCC) and its inverted waveform signal Qx (= VCC-Io * RL) are output from the transistors Q3 and Q4 of the latch unit.
Is output.

[0004]

However, in the above-mentioned conventional ECL latch circuit, there is a problem that a margin for noise is small and the circuit is easily affected by noise. This is because the waveforms of the outputs Q and Qx are synchronized with the latch pulse signals CK and Ckx due to the charging / discharging of the parasitic capacitance C and the wiring capacitance on the collector side of the transistors Q1 to Q6 and the switching operation of the transistors Q5 and Q6. Due to distortion.

That is, the latch pulse signals CK, Ckx
Momentary switching of Q5 and Q6 at the time of inversion, the transistors Q3 and Q4 of the latch section are completely turned off and the constant current source S
The current Io from o instantaneously becomes substantially completely zero,
According to the time constant of the combination of the load resistance RL and the parasitic capacitance C, as shown in FIG. 4, the output Q of the operation signal decreases to form a dent waveform, and Qx correspondingly changes CK and Ckx. The waveform becomes distorted when inverted. The magnitude of this distortion varies depending on circuit conditions and operating conditions, but depends on the logic amplitude level (I
o * RL) in some cases.

At this time, the noise margin of the circuit is expressed as a voltage difference V = Io * RL between Q and Qx. Therefore, when the latch pulse signals CK and Ckx are inverted, Q and Q
When a distortion occurs in the waveform of x, the voltage difference Vs becomes small as shown in the figure, and the margin for noise is reduced.

In the ECL latch circuit, Io and RL are set according to use conditions. Normally VCC is about 5V,
The signal voltage applied to RL is set to a value around 0.8V. However, especially when high speed is required or VC
When C is low and around 3 V, the voltage to RL is 0.2 to
It is used by lowering to about 0.3V. In particular, in such a case, when noise enters through a power supply line (VCC line), the amplitude of the signal voltage itself is small, and thus the noise is easily affected.

The present invention has been made in consideration of the above-mentioned prior art, and has been described with reference to the prior art which eliminates (or reduces) distortion of an output waveform at the time of switching of a latch circuit and increases a noise margin.
It is intended to provide a CL latch circuit.

[0009]

In order to achieve the above object, the present invention has a differential amplifier and a latch unit, and the differential amplifier and the latch unit are connected to a constant current source via a switch circuit. In the ECL latch circuit,
An ECL latch circuit includes an additional current source circuit for constantly flowing a current to the latch section in addition to the constant current source.

According to this configuration, since current always flows from the additional current source circuit to the transistors constituting the latch section, the transistors in the latch section are not completely turned off even during switching, and the output waveform is distorted. Does not occur. In this case, actually, depending on the magnitude of the additional current,
At the time of switching, when the transistor of the latch unit enters the latch operation state earlier than when the transistor is turned on from the off state, the transistor does not substantially turn off and the distortion of the output waveform is reduced.

In a preferred configuration example, the differential amplifier and the latch unit each include a pair of transistors arranged in parallel, and the changeover switch circuit includes a transistor provided on the emitter side of the transistor of the differential amplifier and a transistor of the latch unit. It is characterized by comprising a transistor provided on the emitter side of the transistor, wherein the additional current source circuit is connected to the emitter side of the transistor in the latch section.

According to this configuration, in the latch circuit in which the differential amplifier and the latch section are constituted by a pair of transistors arranged in parallel, and the switch circuit is constituted by the transistors provided on the differential amplifier side and the latch section side, respectively. By connecting the additional current source circuit to the emitter side of the transistor in the latch section, it is possible to constantly supply current to the transistor in the latch circuit with a simple configuration.

In a preferred configuration example, the additional current source circuit comprises a resistor.

According to this configuration, by connecting a resistor to the emitter side of the transistor in the latch section, a constant current corresponding to VCC can always flow through this transistor.

In another preferred configuration, the additional current source circuit comprises a constant current circuit.

According to this configuration, a constant current circuit such as a current mirror circuit is connected to the emitter side of the transistor in the latch section, so that a constant current can be constantly supplied to this transistor.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an ECL latch circuit according to an embodiment of the present invention.

In this embodiment, an additional constant current source circuit S1 is connected to the emitter side of the transistor Q4 constituting the latch section in the ECL latch circuit of FIG. That is, this ECL latch circuit comprises a pair of transistors Q1 and Q2 arranged in parallel and constituting a differential amplifier.
And a pair of transistors Q3 and Q4 arranged in parallel to form a latch unit.

A switching transistor Q5 is connected to the emitters of the transistors Q1 and Q2 on the differential amplifier side.
Similarly, a switching transistor Q6 is connected to the emitters of the transistors Q3 and Q4 on the latch section side, and these transistors Q5 and Q6 form a switch circuit. Each of the transistors Q1 to Q6 has a parasitic capacitance C. Transistor Q constituting switch circuit
5, a constant current source S for supplying a constant current Io to the emitter side of Q6.
o is connected. VCC indicates a reference voltage, and VEE indicates a ground potential. RL indicates a load resistance.

The additional constant current source circuit S1 connected to the emitter side of the transistor Q4 on the latch circuit side comprises, for example, a current mirror circuit, and supplies a current of several% to several tens% of the operating current Io to the transistors Q3 and Q4. Iadd
Flow constantly.

FIG. 2 is a signal waveform diagram showing the operation of the latch circuit of FIG. 4, the data signal D and its inverted waveform signal Dx are input to the transistors Q1 and Q2 on the differential amplifier side. The latch pulse signal CK and its inverted signal Ckx are input to the transistors Q5 and Q6 of the switch circuit. As a result, the operation signal Q and the inverted signal Qx thereof are output from the transistors Q3 and Q4 of the latch section.

In this embodiment, Iadd is
When it is set to be about 0.01 * Io to (0.2 to 0.3) * Io, the operating point of this latch circuit is Ia
A potential lower than VCC by dd * RL operates as a logic high level (“1”) (this is VCC in the circuit of FIG. 3), and all circuits connected before and after are adjusted to this level. The level difference of 1 "" 0 "is properly maintained.

In this embodiment, the output signal Q = VCC-
Iadd * RL, and Qx = VCC-Io * RL-I
add * RL. Therefore, the voltage difference V = Io * R
L. In this case, due to the influence of the parasitic capacitance of each transistor and the additional current Iadd that constantly flows through Q3 and Q4, the latch operation state is earlier than when Q3 and Qkx are inverted from the state where Q3 and Q4 are completely turned off at the time of inversion. As a result, as shown in FIG. 2, the waveforms of Q and Qx do not substantially become distorted as shown in FIG. Is maintained. Therefore, the voltage difference V serving as a noise margin is always maintained at a substantially constant V = Io * RL, and the noise margin does not decrease due to the distortion as shown in FIG.

As another embodiment of the additional current source circuit,
A resistor may be used instead of the constant current circuit S1 using the current mirror circuit. Connect the resistor to the transistor Q4
, The constant current corresponding to VCC can always flow through Q3 and Q4.

[0025]

As described above, according to the present invention, since the current always flows from the additional current source circuit to the transistor constituting the latch section, the transistor in the latch section is substantially completely turned off even during switching. Not,
Almost no distortion of the output waveform occurs. Therefore, deterioration of the noise margin due to the distortion of the output waveform is prevented,
The effect of noise is reduced and a highly reliable latch operation is achieved.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an ECL latch circuit according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram showing an operation of the latch circuit of FIG.

FIG. 3 is a circuit configuration diagram of a conventional ECL latch circuit.

FIG. 4 is a signal waveform diagram illustrating an operation of the latch circuit of FIG. 3;

[Explanation of symbols]

Q1, Q2, Q3, Q4, Q5, Q6: transistors,
C: parasitic capacitance, So: constant current source, S1: additional current source circuit.

Claims (4)

[Claims] 1. An ECL latch circuit connected to a constant current source via a changeover switch circuit, the differential amplifier and the latch unit having a differential amplifier and a latch unit. An ECL latch circuit comprising an additional current source circuit for constantly flowing a current to a latch unit. 2. The differential amplifier and the latch section each comprise a pair of transistors arranged in parallel. The changeover switch circuit includes a transistor provided on the emitter side of the transistor of the differential amplifier and an emitter of the transistor of the latch section. 2. The ECL latch circuit according to claim 1, wherein the additional current source circuit is connected to an emitter of the transistor of the latch unit. 3. 3. The ECL latch circuit according to claim 2, wherein said additional current source circuit comprises a resistor. 4. The ECL latch circuit according to claim 2, wherein said additional current source circuit comprises a constant current circuit.