JPH04618A - High speed bus circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a bus circuit that can operate at high speed in a semiconductor integrated circuit such as a microcomputer.

BACKGROUND OF THE INVENTION In recent years, increasing the speed of microcomputers has been an important issue, and bus circuits have also been targeted.

FIG. 2 is a block diagram showing an example of the configuration of a high-speed bus circuit in a conventional semiconductor integrated circuit. 200 is a positive logic bus, 201 is a negative logic bus, 202 is a bus output circuit, 203 is a precharge circuit, 204 is a level difference amplifier circuit, and 205 is an input latch. The relationship and operation of each of the above components will be explained.

First, the precharge circuit 203 equalizes the levels of the positive logic bus 200 and the negative logic bus 2010. Next, from the bus output circuit 202, the positive logic bus 200 and the negative logic bus 201
Output each.

Next, the output level is amplified by the level difference amplification path 204, and the data is taken into the input latch 205.

The reason why this bus circuit is so fast is that the bus output circuit 202
This is because the output level of the positive logic and negative logic can be sharpened to shorten the time required to reach that level, and the low level is compensated for by the amplifier 204.

Problems to be Solved by the Invention In such conventional high-speed bus circuits, two buses, a positive logic bus and a negative logic bus, are required, which increases the amount of hardware, especially when built into a semiconductor integrated circuit. This has the problem of increasing the chip area and being disadvantageous in terms of cost. The present invention has been made to solve the above problems, and aims to provide a bus circuit that can operate at high speed and can be implemented without significantly increasing the amount of hardware.

Means for Solving the Problems In order to achieve the above object, the present invention sequentially solves the first and second problems.
and a bus control circuit that generates control signals at third and fourth timings, one bus, and a differential amplifier having first and second input terminals, wherein the differential amplifier has the first and second input terminals. An in-phase output is obtained at the input of the input terminal, and an opposite-phase output is obtained at the input of the second input terminal, and the output terminal of the level setting circuit, the output terminal of the bus output circuit, and the data latch are connected to the bus. an input end of the circuit, an output end of the differential amplifier,
A level holding circuit and a switching circuit are provided, and the switching circuit switches and connects the level holding circuit to the bus and a second input terminal of the amplifier. , the level holding circuit is connected to the bus by the switching circuit in response to a control signal at a first timing of the control circuit, and the level setting circuit connects the level of the bus and the level holding circuit to the high level of the bus. setting the low level to an intermediate level, and connecting the level holding circuit to the second input terminal of the differential amplifier with a control signal at a subsequent second timing to input the intermediate level to the differential amplifier; Data is output from the bus output circuit, the amplifier is operated by the control signal at the third timing, and the data on the bus is input and latched by the data latch circuit, and the data is latched by the control signal at the fourth timing. The high-speed bus circuit is configured such that a level setting circuit sets the bus to zero potential and stops the operation of the amplifier.

Before data is input to the active bus, a level setting circuit sets the bus and a level holding circuit to a level intermediate between the high and low levels of the bus, and the level holding circuit memorizes the intermediate level; When data is input to the bus, the differential amplifier amplifies the level change on the bus, and the data latch circuit captures the data on the bus. The bus level change is the difference between the level of the level holding circuit (that is, the bus level before data input) and the bus level after data input. The level of the level holding circuit is switched and input from the bus to the differential amplifier by a switching circuit.

Embodiment Hereinafter, a high-speed bus circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a high-speed bus circuit according to an embodiment of the present invention. As shown in the figure, one lotus 100 is provided, and the source of the transistor 101 and the drain of the transistor 102 constituting the level setting circuit, one end of the changeover switch (switching circuit) 104, and the bus output circuit 106 are connected to the bus. The output terminal, the input terminal of the data latch circuit 107, the first input terminal 115 (in-phase input terminal) and the output terminal of the differential amplifier 105 are connected, and a bus control circuit 108 is provided. Control signals 109 and 1 are sent to the level setting circuit.
10. It outputs a control signal 111 to the bus output circuit 106, a control signal 112 to the input data latch circuit 107, a control signal 113 to the level-operated amplifier 105, and a control signal 114 to the changeover switch 103. Further, the drain of the transistor 101 is connected to a power source, and the source of the transistor 102 is connected to ground. Further, the other end of the changeover switch 104 is connected to a second input terminal 116 (inverse phase input terminal) of the differential amplifier circuit 105. Further, one end of a capacitor 104 constituting a level holding circuit is connected to the common terminal of the changeover switch 103, and the other end is connected to ground.

The operation of the above configuration will be explained with reference to FIG. FIG. 2 is a timing chart showing the operation of the embodiment. The following description will be made assuming that the high level of data on the bus is 5 volts and the low level is O volts. In the figure, at a first timing, that is, at the rising edge of a control signal 110 (precharge signal), a power supply is connected to a bus 100 via a transistor 101 of the level setting circuit. At this time, capacitor 1 forming the level holding circuit
04 is connected to the bus via a changeover switch. The control signal 109 (discharge signal) at the fourth timing is OFF, and the transistor 102 is OFF. The bus 100 and the capacitor 104 are connected by the above connection.
It is set to a level between the high level and low level of the bus, for example, 3 volts (precharge section A in the timing chart). Subsequently, at the second timing, that is, at the rising edge of the control signal 111 (bus output signal), the bus output circuit 106 outputs data to the bus 100, and the capacitor 104 of the level holding circuit is changed over, and the switch 103 is turned on and off the control signal 114 (switched). signal) to the second input 1 of the differential amplifier 105.
16 to input the bus level before data is input (section B in the timing chart).

At this time, the level of the bus 100 changes to further increase the set level when the data of the bus output is high, as shown in the figure, and to lower it when the data is low, but it changes to 5 volts or 0. The reason why it does not change to volts is because the output capability of bus output circuits is generally low, which is a common problem in circuit configurations such as microcontrollers. Subsequently, when the differential amplifier 105 is operated at a third timing, that is, at the rising timing of the control signal 113 (amplification enable signal), the level difference between the first and second input terminals, that is, the change in the level amplify bus 1
Output to 00. This amplification amplifies the small bus level changes described above and causes the bus level to change by up to 5 volts or O volts. In addition, the control signal 112 (
The bus level is taken into the data latch circuit 107 by the input enable signal). Since the amplification operation performs positive feedback amplification, the gain is very large, so it reaches 5 volts or O volts in a short time and is fixed at that level (section C in the timing chart). At the subsequent fourth timing, that is, the rising edge of the control signal 109 (discharge signal), the capacitor 104 of the level holding circuit is switched to the bus 100 using the switch 103, and the transistor 102 of the level setting circuit is turned on. bus 100
Connect to ground and set by discharging the capacitor and bus to O volts (discharge section D in the timing chart).

Through the above continuous operations, transmission of 1-bit data from the bus output and acquisition by the data latch circuit are completed.

As described above, according to the high-speed bus circuit of one embodiment of the present invention,
By inputting data to a bus set to an intermediate level between the high level and low level of the bus, and amplifying the level change before and after the data input on the bus to obtain the bus level, the bus output circuit has a short rise time ( Even if the bus is driven at a high level, the bus is driven to high or low level with a large change, so the bus operates at high speed, and the circuit is simplified because only one pass line is required.

In the above invention, the bus level setting for data input is 3 volts, but as can be seen from the explanation, the differential amplifier amplifies the bus level setting by data input to generate the data level, and the level setting is 3 volts. It goes without saying that the data may be at any other level as long as it is an intermediate level between high and low data.

Effects of the Invention As is clear from the above embodiments, the present invention sequentially achieves the first
a bus control circuit that generates control signals at second, third, and fourth timings; a bus; and a differential amplifier having first and second input terminals; An in-phase output is obtained from the first input, and an opposite-phase output is obtained from the input of the second input terminal, and the output terminal of the level setting circuit, the output terminal of the bus output circuit, and the data latch are connected to the lotus. An input terminal of the circuit, an output terminal of the differential amplifier, and a first input terminal of the amplifier are connected, and a level holding circuit and a switching circuit are provided, and the switching circuit connects the level holding circuit to the bus and the first input terminal of the amplifier. The switching circuit connects the level holding circuit to the bus according to the first timing control signal of the control circuit, and the level setting circuit connects the level holding circuit to the second input terminal of the amplifier. The level of the bus and the level holding circuit are set to an intermediate level between the high level and the low level of the bus, and the level holding circuit is connected to the second input terminal of the differential amplifier by a control signal at a subsequent second timing. inputting the intermediate value to the differential amplifier, outputting data from the bus output circuit, activating the amplification with a control signal at a subsequent third timing, and inputting bus data to the data latch circuit. By using a high-speed bus circuit, the level setting circuit sets the bus to zero potential and stops the operation of the amplifier using a control signal at the fourth timing. By inputting data to a bus set to an intermediate level between a low level and a low level, and amplifying the level change from before data input to the pass line level, even if the data output level to the bus is small, the bus can be set to a large high level. Alternatively, the fact that it can be driven to a low level and requires a small input level shortens the rise time of the input waveform for high-speed operation.
This has the effect of simplifying the circuit because only one bus is required.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a high-speed bus circuit according to an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the high-speed bus circuit according to an embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of a high-speed bus circuit according to an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a circuit. 100... Bus, 101... Transistor (level setting circuit), 102... Transistor (level setting circuit), 103... Changeover switch (switching circuit) , 104... Capacitor (level holding circuit), 105... Differential amplifier, 106... Bus output circuit, 107...
...Data latch circuit, 108...Bus control circuit, 109...Discharge signal (fourth timing control signal), 110...Precharge signal (first timing control signal) timing control signal), 111...
... bus output signal (second timing control signal),
112...Input enable signal (third timing control signal), 113...Amplification enable signal (third timing control signal), 114...
...Switching signal (second timing control signal), 1
15... First input terminal (in-phase input) of the differential amplifier, 116... Second input terminal (negative phase input) of the differential amplifier. Name of agent: Patent attorney Shigetaka Awano and 1 other person Bus transfer agent (mailed to 11th station) TF+I
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Claims (1)

[Claims] a bus control circuit that sequentially generates control signals at first, second, third, and fourth timings, one bus, and a differential amplifier having first and second input terminals; The dynamic amplifier obtains an in-phase output at the input of the first input terminal and an opposite-phase output at the input of the second input terminal, and the output terminal of the level setting circuit and the bus output circuit are connected to the bus. An output terminal of the data latch circuit, an input terminal of the data latch circuit, an output terminal of the differential amplifier, and a first input terminal of the amplifier are connected, and a level holding circuit and a switching circuit are provided, and the switching circuit is configured to control the level. A holding circuit is switched and connected to the bus and a second input terminal of the amplifier, and the level holding circuit is connected to the bus by the switching circuit according to a control signal at a first timing of the control circuit. ,
The level setting circuit sets the level of the bus and the level holding circuit to an intermediate level between the high level and the low level of the bus, and the subsequent second timing control signal sets the level holding circuit to the level holding circuit of the differential amplifier. 2 and inputs the intermediate level to the differential amplifier, outputs data from the bus output circuit, operates the amplifier with a control signal at a subsequent third timing, and operates the data latch circuit. A high-speed bus circuit that inputs and latches data on a bus, and uses a control signal at a subsequent fourth timing to set the bus to zero potential in the precharge circuit and stop the operation of the amplifier.