JP2000349263A - Resistance regulating device and rc oscillating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resistance regulating device that electrically regulates, so that variation in resistance value of a diffusion layer manufactured in a semiconductor process is contained within a definite range. SOLUTION: A resistor 2 formed of a p-type diffusion layer is formed on an n-type silicon substrate 1. Contact regions 3a, 3b, 3c and 3d are placed with prescribed intervals in a longitudinal direction of the resistor 2. Non-volatile memory transistors MT1, MT2 and MT3 and n-channel type MOS transistors MS1, MS2 and MS3 for selecting them are provided, corresponding to the contact regions 3b, 3c and 3d. The sources of the MOS transistors MS1, MS2 and MS3 are connected to the resistor 2 via the contact regions 3b, 3c and 3d, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistance adjusting device and an RC oscillation circuit using the device. More specifically, the oscillation frequency can be adjusted with high precision by using a resistance adjustment device and an adjustment device capable of adjusting the variation of the resistance value of the diffusion layer manufactured by the semiconductor process to be within a certain range. It relates to an RC oscillation circuit.

[0002]

2. Description of the Related Art FIG.
1 shows an RC oscillation circuit integrated in I. In this RC oscillation circuit, an oscillation loop is formed by a Schmitt inverter 51 having two threshold voltages VTH and VTL, a NAND circuit 52, an inverter 53, and a resistor 54 (resistance value R) composed of a diffusion layer. The oscillation stop control signal * STP is applied to one input of the NAND circuit 52. A capacitor 55 (capacitance value C) is connected to the input of the Schmitt inverter 51, and the oscillation frequency is determined by the RC time constant.

[0003]

The diffusion layer formed on the semiconductor substrate has a relatively high sheet resistance of several KΩ to several hundred KΩ, and is suitable as a resistance element of the RC oscillation circuit. However, when an LSI is manufactured by a semiconductor process, the resistance value of the diffusion layer fluctuates about ± 10% from the center value. For this reason,
In some cases, the oscillation frequency of the RC oscillation circuit fluctuates, and the sound generated by an audio device such as a speaker controlled by a microcomputer sometimes becomes abnormal.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problem, and adjusts a resistance value of a diffusion layer manufactured by a semiconductor process so that the resistance value falls within a certain range even when the resistance value varies. It is an object to provide a possible resistance adjustment device.

Another object of the present invention is to provide an RC oscillation circuit capable of adjusting the oscillation frequency with high accuracy by using the resistance adjusting device.

[0006]

A resistance adjusting device according to the present invention comprises a resistor formed on a semiconductor substrate of one conductivity type and formed of a diffusion layer of the opposite conductivity type, and a predetermined interval in the longitudinal direction of the resistor. A plurality of contact regions, a plurality of nonvolatile memory transistor means, a selecting means for selecting the plurality of nonvolatile memory transistor means, and a nonvolatile memory transistor means selected by the selecting means. It is characterized by comprising programming means for changing from a memory state to a second memory state, and means for connecting the plurality of nonvolatile memory transistor means to the resistor via the contact region.

According to this resistance adjusting device, the nonvolatile memory transistor means is selectively programmed in accordance with the level of the sheet resistance of the diffusion layer obtained by the semiconductor process, and utilizing the change in the memory state. Adjusting the resistance value.

For example, under a predetermined bias, the nonvolatile memory transistor means is in an on state in a first memory state, and is in an off state in a second memory state. Then, only the programmed nonvolatile memory transistor means is turned on.

Since all the nonvolatile memory transistor means are connected to the resistor through the contact area, the corresponding portion of the resistor is used as a resistor through the non-volatile memory transistor means turned on. can do.

Further, an RC oscillation circuit according to the present invention is characterized in that the above-described resistance adjusting device is used as a resistor.
Thereby, even if the resistance value of the diffusion layer varies, the oscillation frequency can be adjusted with high accuracy.

Further, the resistance adjusting apparatus of the present invention comprises a resistor formed on a semiconductor substrate of one conductivity type and formed of a diffusion layer of the opposite conductivity type, and a plurality of resistors arranged at predetermined intervals in the longitudinal direction of the resistor. A plurality of non-volatile memory transistor means having a contact region, a floating gate and a control gate, a selecting means for selecting the plurality of non-volatile memory transistor means, and the floating of the non-volatile memory transistor means selected by the selecting means Programming means for changing from a first memory state to a second memory state by injecting electrons into a gate; and a gate electrode for transferring electrons from a floating gate of the nonvolatile memory transistor means; A plurality of MOs connected to the resistor via
And S transistor means.

In this resistance adjusting device, programming of the nonvolatile memory transistor means is performed by injecting electrons into a floating gate, and an MO having a gate electrode to which electrons are transferred from the floating gate.
An S transistor is provided. As a result, the MOS transistor has different conductive states depending on the first memory state and the second memory state. For example, in the first memory state, the MOS transistor is on and the second transistor is on.
In the memory state, the MOS transistor is off.

That is, this MOS transistor functions as a nonvolatile switch. Therefore, the nonvolatile memory transistor means is selectively programmed according to the sheet resistance of the diffusion layer. And this MOS
The resistance value of the resistor is adjusted by changing the on / off state of the transistor.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is a diagram showing a resistance adjusting device according to the first embodiment. A resistor 2 made of a p-type diffusion layer is formed on an n-type silicon substrate 1. This resistor 2
At predetermined intervals in the longitudinal direction of the contact region 3a,
3b, 3c and 3d are arranged. Here, the resistance between the contact regions 3a and 3b is r1, the resistance between the contact regions 3b and 3c is r2, and the resistance between the contact regions 3c and 3d is r3.

Then, the nonvolatile memory transistor MT
1, MT2, MT3 and n-channel type MOS transistors MS1, MS2, MS3 (selection MOS transistors) for selecting these are contact regions 3b, 3c,
3d is provided. MOS transistor M
The sources of S1, MS2 and MS3 are connected to the resistor 2 via contact regions 3b, 3c and 3d, respectively.
This connection can be made by Al wiring.

The n-channel MOS transistor M
The sources of S1, MS2 and MS3 are connected to the bit line BL. MOS transistors MS1, MS2, MS3
Are connected to word lines WL1, WL2, WL3, respectively. Further, the nonvolatile memory transistor M
The control gates of T1, MT2, and MT3 are commonly connected to a word line WL4. The drains of the non-volatile memory transistors MT1, MT2, MT3 are commonly connected to each other.

The control circuit 4 controls voltages applied to these bit lines BL and word lines WL1 to WL4.
From the contact regions 3a and 3d at both ends of the resistor 2, A
The Al electrodes 5 and 6 are taken out by the l wiring.

Here, it is suitable to use an electrically programmable and erasable non-volatile memory (EEPROM) as the non-volatile memory transistor. In this embodiment, a split gate type EEPROM is used.
Is used.

The structure and operation of this type of nonvolatile memory transistor will be briefly described with reference to FIG. A drain region 102 is formed on a P-type semiconductor substrate 101 at a predetermined interval.
And a source region 103 are formed, and a channel region 104 is formed therebetween. On a region from a part of the channel region 104 to a part of the source region 103, the floating gate 10
6 are formed. On this floating gate 106, a thick oxide film 107 (hereinafter referred to as minilocos) formed by a selective oxidation method is provided.

Then, a tunnel oxide film 108 covering the side surface of the floating gate 106 and a part on the minilocus 107 is formed. In addition, tunnel oxide film 1
A control gate 109 is formed on a portion of the drain region 102 from above the channel region 08 and a portion of the channel region 104.

The operation of this nonvolatile memory transistor is as follows. First, for programming, a predetermined voltage (for example, 2 V to the control gate 109 and 12 V to the source region 103) is applied to the control gate 109 and the source region 103, and a current is caused to flow through the channel region 104. Channel hot electrons (CHE) are injected and accumulated. Thus, the nonvolatile memory transistor enters a high threshold state (second memory state).

On the other hand, when erasing, the drain region 10
2 and the source region 103 are grounded, and a predetermined voltage (for example, 15 V) is applied to the control gate 109, so that the electrons accumulated in the floating gate 106 can be subjected to the Fowler-Nordheim tunneling current (Fowler-Nor
dheim tunneling current, hereinafter referred to as FN current. ), The control gate 109 is pulled out. Thus, the nonvolatile memory transistor enters a low threshold state (first memory state).

At this time, since the sharp edge 106a is provided at the upper edge of the floating gate 106, an electric field concentration occurs in this portion, and an FN tunnel current flows at a lower voltage to efficiently perform an erase operation. ing.

This resistance adjusting device selectively programs the nonvolatile memory transistors MT1 to MT3 according to the level of the sheet resistance of the diffusion layer obtained by the semiconductor process, and utilizes the change in the memory state. The resistance value is adjusted as follows.

First, the control circuit 4 controls the word line WL.
An H level (5 V) is applied to 1, WL2 and WL3. Also, an HV level (15 V) is applied to the word line WL4. Further, the bit line BL and the electrodes 5 and 6 are grounded (0 V). Thereby, the nonvolatile memory transistor M
T1, MT2, and MT3 are erased and enter a low threshold state (first memory state).

Next, the nonvolatile memory transistors MT1 to MT3 are selectively programmed according to the level of the sheet resistance of the diffusion layer obtained by the semiconductor process. For example, when the sheet resistance varies to the higher side, the nonvolatile memory transistors MT2 and MT3 are programmed.

In this case, the word lines WL2 and WL3 are set to the H level and the word line WL1 is set to the L level (0 V) by the control circuit 4. A voltage of 2 V is applied to the word line WL4 and a voltage of 12 V is applied to the bit line BL. As a result, the nonvolatile memory transistors MT2 and MT3 are selectively programmed, and enter a high threshold state (second state).

Next, the control circuit 4 controls the word line WL.
1, WL2 and WL3 are set to H level, and the word line WL4 is set to 2V. The bit line BL is in a floating state.

Then, the programmed nonvolatile memory transistors MT2 and MT3 are turned off, only the nonvolatile memory transistor MT1 is turned on, and the resistance value r1 + r is obtained. Here, r is the nonvolatile memory transistor MT1 and the MOS transistor MS
1 is the on-resistance.

If the sheet resistance varies to the lower side, the nonvolatile memory transistor MT
1, MT2 is programmed, and only the nonvolatile memory transistor MT3 is turned on.

FIG. 3 shows an RC using the above-described resistance adjusting device.
FIG. 3 is a diagram illustrating an oscillation circuit. A portion surrounded by a broken line is the above-described resistance adjustment circuit. Other parts are the same as those of the conventional RC oscillation circuit. The oscillation frequency is adjusted as follows.

First, the oscillation stop signal * STP is set to L level (0 V). Then, the output of the inverter 9 becomes L level, and 0 is applied to the drain of the nonvolatile memory transistor.
V is applied. In this state, the non-volatile memory transistors MT1, MT2, and MT3 are erased (first memory state). Next, the desired non-volatile memory transistor is selectively programmed (eg, MT2 and M2).
T3).

Next, the control circuit 4 controls the word line WL.
1, WL2 and WL3 are set to H level, and the word line WL4 is set to 2V. The bit line BL is in a floating state. As a result, only MT1 is turned on. Then, in this state, when the oscillation stop signal * STP is set to the H level, an oscillation loop is formed and oscillation starts. Thus, the resistance value is adjusted by the resistance adjustment circuit, so that the oscillation frequency of the RC oscillation circuit can be adjusted.

FIG. 4 is a diagram showing a resistance adjusting device and an RC oscillation circuit according to the second embodiment. The difference of the resistance adjusting device from the first embodiment will be described. First, a MOS transistor MW1 having a gate electrode through which electrons are transferred from the floating gate of the nonvolatile memory transistor MT1 is provided. That is, the floating gate of the nonvolatile memory transistor MT1 is
The gate of the S transistor MW1 is connected. The source of the MOS transistor MW1 is connected to the resistor 2 via the contact region 3b. MOS transistors MW2 and MW3 having the same configuration are provided.

The nonvolatile memory transistor MT
The drains of MT1, MT2 and MT3 are grounded. The selection MOS transistors MS1, MS2, MS3 are not directly connected to the contact regions. The nonvolatile memory transistors MT1, MT2, and MT3 use a split gate EEPROM as in the first embodiment.

Next, the adjusting operation of the resistance adjusting device will be described. First, the control circuit 4 causes the word lines WL1 and W
An H level (5 V) is applied to L2 and WL3. Also, an HV level (15 V) is applied to the word line WL4. Further, the bit line BL is grounded (0 V). As a result, the nonvolatile memory transistors MT1, MT2, and MT3 are erased, and enter a low threshold state (first memory state).

Nonvolatile memory transistors MT1, MT
2 and MT3 are connected to the gates of the MOS transistors MW1, MW2 and MW3, respectively, so that the MOS transistors MW1, MW2 and MW
Electrons are also extracted from the third gate. Since these gates have a somewhat high voltage due to capacitive coupling with the control gates, the MOS transistors MW1 and M
W2 and MW3 are turned on.

Next, the nonvolatile memory transistors MT1 to MT3 are selectively programmed according to the level of the sheet resistance of the diffusion layer obtained by the semiconductor process. For example, when the sheet resistance varies to the higher side, the nonvolatile memory transistors MT2 and MT3 are programmed.

In this case, the word lines WL2 and WL3 are set to the H level and the word line WL1 is set to the L level (0 V) by the control circuit 4. A voltage of 2 V is applied to the word line WL4 and a voltage of 12 V is applied to the bit line BL. As a result, the nonvolatile memory transistors MT2 and MT3 are selectively programmed, and enter a high threshold state (second state). At the time of this programming, the floating gates of the nonvolatile memory transistors MT2 and MT3 are
Electrons are transferred to transistors MW2 and MW3. As a result, the MOS transistors MW2 and MW3 are turned off.

That is, the MOS transistor MW
1, MW2 and MW3 function as nonvolatile switches. The selection transistor and the nonvolatile memory transistor are
It functions to selectively turn on and off these nonvolatile switches.

If the sheet resistance varies to a lower side, the nonvolatile memory transistor MT
1, MT2, and MOS transistor M
Only W3 is turned on.

As described above, according to the second embodiment, only one MOS transistor MW1, MW is connected to the resistor 2 through the contact regions 3b, 3c, 3d.
2, MW3, it is possible to reduce the resistance of the transistor portion as compared with the first embodiment, and it is possible to improve the adjustment accuracy of the resistance value. In addition, since the MOS transistors MW1, MW2, and MW3 function as nonvolatile switches by programming, there is no need to subsequently set a bias by the control circuit 4.

The RC oscillation circuit according to the second embodiment uses the above-described resistance adjusting device as a resistor. The adjustment of the oscillation frequency is performed as follows. First, the oscillation stop signal * STP is set to L level. As a result, the sources and drains of the MOS transistors MW1, MW2, MW3 are grounded.

Then, in this state, the non-volatile memory transistors MT1, MT2, MT3 are erased (first memory state). Next, a desired nonvolatile memory transistor is selectively programmed (for example, MT2 and MT3). Thereby, the MOS transistors MW1, M
W2 and MW3 are selectively turned on and off. When the oscillation stop signal * STP is set to the H level in this state,
An oscillation loop is formed, and oscillation starts. In this manner, the resistance value is adjusted by the resistance adjustment circuit, so that R
The oscillation frequency of the C oscillation circuit can be adjusted.

[0046]

As described above, according to the resistance adjusting apparatus of the present invention, the nonvolatile memory transistor means is selectively programmed in accordance with the level of the sheet resistance of the diffusion layer obtained by the semiconductor process. By using the change in the memory state, the resistance value can be electrically adjusted after the semiconductor process is completed.

Further, by using this resistance adjusting device in an RC oscillation circuit, it is possible to electrically adjust the oscillation frequency after an LSI is completed by a semiconductor process.

[Brief description of the drawings]

FIG. 1 is a diagram showing a resistance adjusting device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a split type EEPROM.

FIG. 3 is a diagram illustrating an RC oscillation circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a resistance adjusting device and an RC oscillation circuit according to a second embodiment of the present invention.

FIG. 5 is a diagram showing an RC oscillation circuit according to a conventional example.

Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat II (reference) H03K 3/03 F term (reference) 5B025 AA03 AB01 AC01 AD04 AD08 AD15 AE08 5F001 AA09 AA21 AA22 AA25 AA33 AA63 AB03 AD15 AE02 AE08 AH02 5F083 EP03 EP24 EP53 EP54 EP57 ER02 ER09 ER17 ZA12 5J043 AA14 AA22 EE01 LL04

Claims (4)

[Claims] A resistor formed on a semiconductor substrate of one conductivity type and formed of a diffusion layer of the opposite conductivity type; a plurality of contact regions arranged at predetermined intervals in a longitudinal direction of the resistor; Nonvolatile memory transistor means; selecting means for selecting the plurality of nonvolatile memory transistor means; and programming for changing the nonvolatile memory transistor means selected by the selecting means from a first memory state to a second memory state. Means for connecting the plurality of non-volatile memory transistor means to the resistor via the contact region. 2. An RC oscillator circuit using the resistance adjusting device according to claim 1 as a resistor. 3. A resistor formed on a semiconductor substrate of one conductivity type and formed of a diffusion layer of the opposite conductivity type, a plurality of contact regions arranged at predetermined intervals in a longitudinal direction of the resistor, and a floating gate. A plurality of nonvolatile memory transistor means having a plurality of nonvolatile memory transistor means; a selecting means for selecting the plurality of nonvolatile memory transistor means; and injecting electrons into a floating gate of the nonvolatile memory transistor means selected by the selecting means. Programming means for changing from a first memory state to a second memory state, and a gate electrode through which electrons are transferred from a floating gate of the non-volatile memory transistor means, to the resistor via the contact region. Multiple Ms connected
A resistance adjusting device, comprising: an OS transistor means. 4. An RC oscillation circuit using the resistance adjusting device according to claim 3 as a resistor.