JP2000347861A - Compiler, processor and recording medium - Google Patents

Abstract

(57) [Summary] [PROBLEMS] A classic VLIW processor has a fixed role for each slot, and the degree of parallelism extracted by a compiler is low. In today's VLIW processors, where the role is not fixed for each slot, the length of the operation code is increased and the instruction length is increased in order to be able to specify whether or not flags change for all operation operations, resulting in a longer program size. Is increased. SOLUTION: A compiler generates a machine instruction including a flag control code related to how an operation is reflected on a flag, and a processor reflects an operation result by parallel execution on the flag according to the flag control code. Preferable flag control codes include a code that specifies which operation result of a plurality of slots to be executed in parallel is reflected in the flag, and a code that specifies an order in which the result of the operation is reflected in the flag.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compiler, a processor, and a recording medium, and more particularly to a VLIW (Very Long Instrument).
The present invention relates to a flag control in a processor of a ction word) system, a compiler thereof, and a recording medium storing a machine instruction program thereof.

[0002]

2. Description of the Related Art With the development of electronic technology in recent years, high-performance processors have become widespread and used in all fields.
Such a processor achieves high performance by parallel processing of instructions. An architecture called VLIW is also one form of instruction parallel processing. A processor employing the VLIW architecture (hereinafter, referred to as a “VLIW processor”) includes a plurality of operation units therein and has a slot provided for one instruction. Performs the operations specified in multiple fields simultaneously, in parallel. Such a machine instruction program of the VLIW processor is generated after a parallelism at an operation level in a program described in a high-level language is detected and scheduled by a compiler. The machine instruction program is also called an execution code.

In a classic VLIW processor, the role is fixed for each slot. For example, a first slot for designating an arithmetic operation, a second slot for designating a load store operation, and a third slot for designating a branch operation. Some have an instruction word consisting of In such a VLIW processor, the flag indicating the state of the operation result is reflected only by the operation specified in the first slot.

However, since the role is fixed for each slot, the degree of parallelism extracted by the compiler is reduced. The arithmetic, load store, and branch operations appear on average at a rate of approximately one-third on average, but since their local frequencies vary widely, for example, when arithmetic operations are concentrated, the above-described VL
An IW processor cannot ensure sufficient parallelism.

Therefore, many of today's VLIW processors adopt a system in which the role is not fixed for each slot. FIG. 17 is an instruction configuration diagram of such a VLIW processor according to the related art. The instruction format is shown in Figure (a).
The instruction is 64 bits long as shown in FIG.
The operation consists of three 1-bit slots, and any slot can specify an operation equally. 11
Each bit slot is composed of a 5-bit operation code (op), a 3-bit source operand (src), and a 3-bit destination operand (dst), and the bit string shown in FIG. Here, only one operation in which the flag changes can be specified at the same time, but any slot can be specified.

FIG. 18 is a schematic configuration diagram of a processor in the prior art. This processor executes three operations in parallel, and stores a program consisting of a sequence of instructions consisting of first to third three slots as shown in FIG. 17A in the ROM 41, and writes the program in each slot. The entered operation is performed by the first instruction
After being decoded by the command decoder 47, the first operation unit 58
From the third operation unit 60. One of the source data for flag generation output from each of the first operation unit 58 to the third operation unit 60 is selected by the selector 61, and the flag generation unit 62 selects C,
V, N, and Z flags are generated, and the flag register 63
Each flag is stored. The selection by the selector 61 is achieved by the first instruction decoder 45 to the third instruction decoder 47 specifying the slot in which the operation whose flag changes is specified. Note that the C flag indicates carry,
The V flag indicates overflow, the N flag indicates a negative number, and the Z flag indicates zero.

[0007]

However, in the above-mentioned prior art, the length of the operation code becomes longer because the operation code has two types, one of which is an operation code whose flag changes and the other of which is not. There is a problem that the length is increased, and as a result, the program size is increased.

In the example shown in FIG. 17, five bits of the operation code are required for two types of operation codes for discriminating the presence / absence of a flag change for the four arithmetic operations and the logical operation. On the other hand, one of eight registers is used as an operand.
If one is selected, the length of one slot is 11 bits in total of two bits of 5 bits of an operation code and 3 bits of an operand.
Become a bit. In the case of three parallel operations, three slots cannot be represented by 32 bits, and the instruction word length is usually 64 bits because the instruction word length is represented by a bit length of a power of two.
An unused area of 1 bit (area indicated by reserved in FIG. 17A) is generated, and the code efficiency is significantly reduced. Code efficiency is a measure of how small a sequence of operations can be achieved with a small program size.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a compiler and a processor that achieve both improvement in parallelism and suppression of reduction in code efficiency.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

According to the present invention, in order to solve the above-mentioned problems, a compiler generates a machine instruction including a flag control description on a method of reflecting an operation result on a flag, and a processor controls the flag control. The operation result of the parallel execution is reflected in the flag according to the description.

In other words, in order to solve the above-mentioned problem, a compiler according to the present invention provides a long-language instruction format machine for a processor that executes a plurality of operations simultaneously and in parallel from a high-level language program and reflects the operation results in flags. A compiler for generating an instruction program, wherein one machine instruction includes:
A machine instruction generating means for generating a machine instruction including a plurality of operation descriptions and a flag control description on how to reflect an operation result on the flag is provided.

That is, in order to solve the above-mentioned problems, a processor of the present invention is a processor for executing a long-word instruction format instruction for designating a plurality of operations. Fetch an instruction that also includes a flag control description on how to reflect the result in the flag,
The operation according to the operation description is executed in parallel, and the operation result of the parallel execution is reflected on a flag according to the flag control description.

The processor according to the present invention is a processor for executing instructions in a long-word instruction format for designating a plurality of operations. The number of operation descriptions that can be executed in parallel and the method of reflecting operation results on flags are described. Instruction reading means for extracting an instruction containing the flag control description at the same time, instruction decoding executing means for decoding the operation description, and executing an operation in parallel based on the decoding result, and instruction decoding executing means according to the flag control description. And a flag generation and holding means for reflecting the operation result in the flag to the flag.

That is, in order to solve the above problems, a recording medium according to the present invention is a recording medium that records a machine instruction program executed by a processor that executes a plurality of operations simultaneously and in parallel and reflects an operation result on a flag. One machine instruction is characterized in that it is configured to include a plurality of operation descriptions and a flag control description on how to reflect an operation result on the flag.

Further, the recording medium of the present invention is a recording medium in which a machine instruction program executed by a processor is recorded, wherein a number of operation descriptions that can be executed simultaneously and a flag relating to a method of reflecting the operation result on the flag are provided. A first step of extracting an instruction in a long-word instruction format including a control description at the same time; a second step of executing the operation according to the operation description in parallel; This is a recording medium on which a machine instruction program for causing a processor to execute three steps is recorded.

The flag control description in the compiler, the processor or the recording medium is information for specifying one of the plurality of operation descriptions included in the same machine instruction to reflect an operation result in the flag. May be configured.

The flag control description in the compiler, the processor, or the recording medium is constituted by information for specifying an order in which a result of an operation according to the plurality of operation descriptions included in the same machine instruction is reflected in the flag. It may be.

The above-mentioned flag control description in the compiler, processor or recording medium extracts, from among the plurality of operation descriptions included in the same machine instruction, some of which reflect the operation result in the flag, It may be configured with information for specifying the order in which the results of the operations according to the extracted some operation descriptions are reflected in the flag.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) 1. 1. Compiler 1.1 Configuration of Compiler FIG. 1 is a block diagram showing a configuration of a compiler according to the first embodiment of the present invention.

The compiler 102 has a C
The language program file 101 is translated, and the machine instruction program file 110 is output.

The compiler 102 analyzes the syntax and meaning of the C language program read into the reading buffer 104 by analyzing the syntax and meaning of the C language program read into the reading buffer 104. Generates a code and successively intermediate buffer 1
06, and the sequential intermediate code stored in the sequential intermediate code buffer 106 are input to perform scheduling of instructions for three-parallel execution of instructions, generate a machine instruction program, and generate an output buffer. 1
08 and a machine instruction program stored in the output buffer 108 in the file 1
10 and a file output unit 109 for outputting the data to the file output unit 10. The components other than the machine instruction generation unit 107 may be configured based on a known technique, and a description thereof will not be repeated.

FIG. 2 is a block diagram showing the configuration of the machine instruction generator 107. The machine instruction generation unit 107 includes a dependency extraction unit 120, a parallel intermediate code generation unit 121, and a flag control code generation unit 122. The dependency extracting unit 120 detects a dependency between a plurality of sequential intermediate codes input from the sequential intermediate code buffer 106 and parameterizes the detected dependencies. The parallel intermediate code generation unit 121 generates a parallel execution format intermediate code from the serial execution format intermediate code using the dependency parameter created by the dependency extraction unit 120. Flag control code generator 122
Assigns a parallel intermediate code generated by the parallel intermediate code generation unit 121 to a corresponding machine instruction, and generates a flag control code based on whether or not there is a slot including an operation whose flag changes. The flag control code is a 2-bit code that specifies which operation result of the three slots to be executed in parallel is reflected in the flag, where 01 is the first slot, 10 is the second slot, and 11 is the second slot. Specifies that the result of the operation of the third slot is reflected in the flag, and 0
0 indicates that the result of the operation of any slot is not reflected in the flag.

FIG. 3 is a flowchart showing a flow of generating a flag control code in the flag control code generation unit 122. This generation flow will be described in detail using the following operation example.

1.2 Example of Operation of Compiler FIG. 4 is a program list showing an example of a C language program. In the C language program of FIG. 4, only a loop for performing a so-called multiply-accumulate operation for accumulating a product of an array variable x [i] and an array variable y [i] for i is described.

Hereinafter, the operation of the compiler having the above configuration when the program list of FIG. 4 is input will be described with reference to FIGS.

The file reading unit 103 reads the C language program 101 described by the user, and stores it in the reading buffer 104.

The syntax analysis unit 105 includes the read buffer 10
Then, the C language program stored in C.4 is taken out, the syntax analysis is performed, and the intermediate code in the sequential execution format is output to the sequential intermediate code buffer 106. FIG. 5 is a list showing the sequential intermediate code program stored in the sequential intermediate code buffer 106 at this time. The meaning of each code is as follows. (Sequential intermediate code 1) A value is extracted from the memory area indicated by the pointer X and stored in a variable x. (Sequential intermediate code 2) The value is taken out from the memory area indicated by the pointer Y and stored in the variable y. (Sequential intermediate code 3) The product of variable x and variable y is calculated and stored in temporary variable t1. (Sequential intermediate code 4) The sum of the variable a and the temporary variable t1 is obtained and stored in the variable a. (Sequential intermediate code 5) Decrease pointer X by 4. (Sequential intermediate code 6) Decrease pointer Y by 4. (Sequential intermediate code 7) Decrease the variable i by one. [F] means that this result is reflected in the flag. If the (sequential intermediate code 8) flag satisfies “greater than (>)”, the flow branches to the sequential intermediate code 1.

Next, the dependency extracting section 120 in the machine instruction generating section 107 executes the sequential intermediate code buffer 106
Is extracted, and the dependency between the sequential intermediate codes is analyzed and parameterized. FIG.
FIG. 6 is an explanatory diagram regarding parameterization of a dependency in the sequential intermediate code program shown in FIG. 5. The variable x which is the execution result of the sequential intermediate code 1 is referred to in the sequential intermediate code 3. Also, the sequential intermediate code 5 must not be executed to update the pointer X before the sequential intermediate code 1 is executed. Therefore, the sequential intermediate code 3 and the sequential intermediate code 5 depend on the sequential intermediate code 1. Through the above analysis, the dependency parameter P1 and the parameters a and d of the dependency directed graph of FIG. 6 are determined. Similarly, the sequential intermediate code 3 and the sequential intermediate code 6 depend on the sequential intermediate code 2 (b and e of the dependency directed graph, the dependency parameter P2), and the sequential intermediate code 4 depends on the sequential intermediate code 3 (dependent In the relational directed graph, the dependency parameter P3), the sequential intermediate code 8 depends on the sequential intermediate code 7 (in the dependency directed graph, the dependency parameter P
7). Dependency parameters P4 to P6 and P8 indicate that no other dependencies are given.

Subsequently, the parallel intermediate code generation unit 121
An intermediate code in a parallel execution format is generated from the intermediate code in a sequential execution format using the parameters of the dependency relationship created by the dependency relationship extraction unit 120. FIG. 7 is a list of parallel intermediate code programs obtained by rearranging the sequential intermediate code program of FIG. 5 into a parallel execution format using the dependency relationship parameters P1 to P8 of FIG. Here, the degree of parallelism is a maximum of three. The meaning of each code is generated according to the following procedure. (Parallel intermediate code 1) Although the sequential intermediate code 1 and the sequential intermediate code 2 can be executed in parallel, all the other sequential intermediate codes have a dependency on them, so that the parallel intermediate code 1 is And a sequential intermediate code 2. (Parallel intermediate code 2) Since the sequential intermediate code 3 can be executed in parallel with the sequential intermediate code 5 and the sequential intermediate code 7, which have no dependency on each other, the parallel intermediate code 2 is composed of the sequential intermediate code 3 and the sequential intermediate code 5. And a sequential intermediate code 7. (Parallel intermediate code 3) Since the sequential intermediate code 4 can be executed in parallel with the sequential intermediate code 6 and the sequential intermediate code 8 that have no dependency on each other, the parallel intermediate code 3 is composed of the sequential intermediate code 4 and the sequential intermediate code 6. And a sequential intermediate code 8.

Next, the flag control code generation unit 122
The parallel intermediate code generated by the parallel intermediate code generation unit 121 is assigned to a corresponding machine instruction, and a flag control code is generated based on whether or not there is a slot including an operation whose flag changes, and is output to the output buffer 108. I do. FIG. 8 is a list of machine instruction programs generated based on the parallel intermediate code program of FIG. Note that the machine instruction program is originally a bit string of 0s and 1s, but is represented by a mnemonic in FIG. 8 to represent the meaning. Each instruction is a flag control code, a first slot, a second slot, and a third slot from the left delimited by a semicolon (;). The meaning of each instruction and the procedure of generation are as follows. (Instruction 1) Allocate pointer X and pointer Y to register R0 and register R1, and register variables x and y
Assign to R2 and register R3. The first slot of the instruction corresponds to the sequential intermediate code 1, and is an LD operation for transferring data by indirect reference of R0 to R2. The second slot corresponds to the sequential intermediate code 2 and is an LD operation for transferring data by indirect reference of R1 to R3. Since there is no corresponding intermediate code in the third slot, a NOP operation is performed. The NOP operation is realized by, for example, an operation of transferring the register R7 to the register R7, but is referred to as NOP here for easy understanding. Since the result of the operation of any slot is not reflected in the flag, step S301 in FIG.
S303, step S305, and step S307 are processed to generate 00 as the flag control code. (Instruction 2) Allocate variable i and temporary variable t1 to register R4 and register R3. The first slot of the instruction corresponds to the sequential intermediate code 3, and is a MUL operation for obtaining the product of R2 and R3 and storing the result in R3. The second slot is sequential intermediate code 5
Is a SUB operation of subtracting 4 from R0 and storing the result in R0. The third slot corresponds to the sequential intermediate code 7,
This is a SUB operation of subtracting 1 from R4 and storing the result in R4.
At this time, since the result of the operation of the third slot is reflected in the flag, steps S301, S303, S305, and S306 in FIG. 3 are performed, and 11 is generated as a flag control code. (Instruction 3) Allocate variable a to register R5. The first slot of the instruction corresponds to the sequential intermediate code 4, and is an ADD operation for obtaining the sum of R3 and R5 and storing the result in R5. The second slot corresponds to the sequential intermediate code 6, and subtracts 4 from R1 to obtain the result.
This is a SUB operation stored in R1. The third slot corresponds to the sequential intermediate code 8. If the flag satisfies "greater than (>)", it is a BGT operation two instructions before, that is, a branch to the instruction 1. Then, since the result of the operation of any slot is not reflected in the flag, steps S301 and S3 in FIG.
03, step S305, and step S307 are processed to generate 00 as a flag control code.

Finally, the file output unit 109 outputs the machine instruction program stored in the output buffer 108 to the file 110.

As described above, the C language program in FIG. 4 is converted into the machine instruction program in FIG. Note that in the above operation example, there is an unpassed step in FIG.
When the result of the slot operation is reflected in the flag, FIG.
Is generated as a flag control code by performing steps S301 and S302 in step S301, and when the result of the operation of the second slot is reflected in the flag, the processing is performed in steps S301, S303, and S304 in FIG. 10 is generated as the control code.

2. Processor 2.1 Instruction Configuration FIG. 9 is an instruction configuration diagram of the processor according to the first embodiment of the present invention. The instruction format is a 32-bit instruction format as shown in FIG. 7A, and includes a flag control field for indicating a 2-bit flag control code, and three slots each having 10 bits. Can also specify the operation equally. Each 10-bit slot is composed of a 4-bit opcode (op), a 3-bit source operand (src), and a 3-bit destination operand (dst), and the bit string shown in FIG.
Here, the operation in which the flag changes is 1 at the same time.
Only one can be specified, but any slot can be specified. The flag control code is set to 01 when the result of the operation of the first slot is reflected in the flag, the flag control code is set to 10 when the result of the operation of the second slot is reflected in the flag, and the result of the operation of the third slot is set. The flag control code is set to 11 when reflecting on the flag, and the flag control code is set when the result of any slot operation is not reflected on the flag. Sixteen types of operation codes are allocated from 0000 MOV operations to 1111 ST operations. The operand is 3 bits and selects one of the registers R0 to R7.

2.2 Configuration of Processor FIG. 10 is a schematic configuration diagram of the processor in the embodiment.

This processor includes an instruction fetch stage (hereinafter, IF stage), a decoding and register reading stage (hereinafter, DEC stage), and an execution stage (hereinafter, EX stage).
(Stage) in a three-stage pipeline structure.

In FIG. 10, reference numeral 1 denotes a ROM for storing a machine instruction program, and 2, 3 and 4 store the contents of the first, second, and third slots of a machine instruction (hereinafter abbreviated as an instruction). I1 latch, I2 latch and I
The three latches 5, 5, 6 and 7 decode the contents of the first, second and third slots of the instruction held in the I1 latch 2, the I2 latch 3 and the I3 latch 4, respectively, and control the respective parts of the processor. An instruction decoder, a second instruction decoder, and a third instruction decoder, 8 is a register file for storing operands, 9 and 10, 11 are registers and a part of the contents of I1 latch 2, I2 latch 3, and I3 latch 4, respectively. D1 selector, D2 selector and D3 selector for selecting one from two inputs of the output of file 8; D13 latches and D12 for storing the outputs of D1 selector 9, D2 selector 10 and D3 selector 11; Latch and D
13 latches, 15, 16 and 17 are D21 latches, D22 latches and D23 latches for storing the output of the register file 8, and 18 are D11 latches 12 and D21 latches 15.
1 is a first operation unit for performing all operations such as arithmetic logic operation and load / store using the contents of
2 and a second operation unit for performing all operations such as arithmetic and logical operations and load / store operations using the contents of the D22 latch 16; 20 denotes an arithmetic and logical operation and load / store operations using the contents of the D13 latch 14 and the D23 latch 17; A third operation unit for performing all operations, the first operation unit 18
The outputs of the second operating unit 19 and the third operating unit 20 are both connected to the register file 8. 21 is an I0 latch for storing the contents of the flag control field of the instruction;
22 is a D0 latch for storing the contents of the I0 latch 21;
Reference numeral 3 denotes a selector for selecting and outputting one of source data for flag generation output from each of the first operation unit 18 to the third operation unit 20, and reference numeral 24 denotes a selector 2
3. A flag generation unit that generates each of the flags C, V, N, and Z based on the source data selected in step 3, a flag register 25 that stores the flags generated by the flag generation unit 24, and a first instruction 26. A branch unit that determines whether or not to branch based on the state of each flag in the flag register 25 when any one of the decoder 5 to the third instruction decoder 7 decodes a conditional branch operation. The instruction fetch unit fetches an instruction sequence according to a branch destination when there is a branch instruction, and sequentially fetches a continuous instruction sequence when there is no branch instruction.

The selector 23 sets the value of the D0 latch 22 to 0.
If 1, the source data output from the first operation unit 18 is selected, if 10 the source data output from the second operation unit 19 is selected, and if 11 the source data output from the third operation unit 20 is selected. Is selected and 00 does not work. If the value of the D0 latch 22 is 01, the flag generation unit 24 generates each flag using the source data output from the selector 23 according to the instruction of the first instruction decoder 5, and stores only the generated flag in the flag register 25. Store in the corresponding location. For example, the first command decoder 5
When decoding the ADD operation, all the flags are used. When decoding the AND operation, the N flag and the Z flag are used.
When decoding the T operation, a flag is generated for only the Z flag and the flag register 25 is updated. Similarly, if the value of the D0 latch 22 is 10, the instruction of the second instruction decoder 6 is followed, and if the value of the D0 latch 22 is 11, the instruction of the third instruction decoder 7 is followed. If the value of the D0 latch 22 is 00, none of the flags are updated. The C flag indicates a carry, the V flag indicates an overflow, the N flag indicates a negative number, and the Z flag indicates zero.

2.3 Operation Example of Processor Hereinafter, the operation of the processor having the above configuration when the machine instruction program of FIG. 8 is stored in the ROM 1 will be described with reference to FIG. It is assumed that the NOP operation in instruction 1 of FIG. 8 is realized by MOVs R7 and R7.

FIG. 11 shows that the machine instruction program of FIG.
FIG. 9 is an operation timing chart of the processor when the data is stored in M1. The figure shows the operation of the processor at each timing called a machine cycle, the instructions read from the ROM 1 in the IF stage of the pipeline, the instructions decoded in the DEC stage, and the instructions executed in the EX stage. Hereinafter, the operation will be described for each timing in order of elapse of time.

(Timing t1) IF stage: Instruction 1 Instruction 1 is read from ROM 1, flag control code 00 of instruction 1 and first to third slots are respectively transferred from I0 latch 21 and I1 latch 2 to I3 latch 4 Is stored.

(Timing t2) DEC stage: Instruction 1 The first slot of instruction 1 stored in I1 latch 2 is the first slot.
It is decoded by the instruction decoder 5. As a result of the decryption, it is determined that the operation is the LD operation. Based on this decoding, register R0 is read from register file 8, and the read value is stored in D11 latch 12. At the same time, I2 latch 3
The second slot of the instruction 1 stored in the second instruction decoder 6
Will be decrypted. As a result of the decryption, it is determined that the operation is the LD operation. Based on the decoding, the register R1 is read from the register file 8, and the read value is stored in the D12 latch 13. At the same time, the third slot of the instruction 1 stored in the I3 latch 4 is decoded by the third instruction decoder 7. As a result of the decryption, it is determined that the operation is the NOP operation (MOV R7, R7). Based on this decoding, register R7 is read from register file 8, and the read value is D1.
3 latch 14. At the same time, the value 00 of the I0 latch 21 is stored in the D0 latch 22. Also, the branch unit 26 does not function because none of the first to third instruction decoders 5 to 7 has decoded the branch operation, so the instruction fetch unit 27 continues sequential fetching. IF stage: instruction 2 Instruction 2 is read from ROM 1 and flag control code 11 of instruction 2 and first to third slots are stored in I0 latch 21 and I1 latch 2 to I3 latch 4, respectively.

(Timing t3) EX stage: Instruction 1 An operation of reading data from the memory using the value of the register R0 stored in the D11 latch 12 as an address is performed by the first operation unit 18, and the read data is stored in the register file 8 Is stored in the register R2. At the same time, the operation of reading data from the memory using the value of the register R1 stored in the D12 latch 13 as an address is performed by the second operation unit 19.
The read data is stored in the register R3 of the register file 8. At the same time, D13 latch 1
The operation of outputting the value of the register R7 stored in the register 4 as it is is performed by the third operation unit 20, and the output data is stored in the register R7 of the register file 8. At the same time, the selector 23 does not function due to the value 00 of the D0 latch 22, and the flag generation unit 24
Do not update any of the flags. • DEC stage: instruction 2 The first slot of instruction 2 stored in I1 latch 2 is the first slot
It is decoded by the instruction decoder 5. MUL as decrypted result
It turns out to be an operation. Based on this decoding, the registers R2 and R3 are read from the register file 8, and the read values are stored in the D11 latch 12 and the D21 latch 15, respectively.
And stored in At the same time, the second slot of the instruction 2 stored in the I2 latch 3 is decoded by the second instruction decoder 6.
As a result of the decryption, it is determined that the operation is a SUB operation.
Based on this decoding, the immediate value 4 in the instruction is changed to the D2 selector 10
, The register R0 is read from the register file 8, and the read value is stored in the D22 latch 16. At the same time,
The third slot of the instruction 2 stored in the I3 latch 4 is the third slot.
The command is decoded by the command decoder 7. SUB as decrypted result
It turns out to be an operation. Based on this decoding, the immediate value 1 in the instruction is transferred to the D13 latch 1 via the D3 selector 11.
4, the register R4 is read from the register file 8, and the read value is stored in the D23 latch 17. At the same time, the value 11
Are stored in the D0 latch 22. The branch unit 26
Does not work because none of the first to third instruction decoders 5 to 7 has decoded the branch operation, so the instruction fetch unit 27 will continue to fetch sequentially. IF stage: instruction 3 Instruction 3 is read from ROM 1 and flag control code 00 of instruction 2 and first to third slots are stored in I0 latch 21 and I1 latch 2 to I3 latch 4, respectively.

(Timing t4) EX stage: instruction 2 The value of register R2 stored in D11 latch 12 and D21
A multiplication operation is performed by the first operation unit 18 with the value of the register R3 stored in the latch 15, and the operation result is stored in the register R3 of the register file 8. At the same time, D
A subtraction operation is performed between the value 4 stored in the 12 latch 13 and the value of the register R0 stored in the D22 latch 16 (from R0 to 4).
Is performed in the second operation unit 19, and the operation result is stored in the register R0 of the register file 8. At the same time, the value 1 stored in D13 latch 14 and D23
The third operation unit 20 performs a subtraction operation (subtract 1 from R4) with the value of the register R4 stored in the latch 17, and the operation result is stored in the register R4 of the register file 8. At the same time, the value 23 of the D0 latch 22 causes the selector 23 to determine the source data from the third operation unit 20 (in this case, the carry of the most significant bit and the bit following it, the most significant bit of the result and the total of the result). (Information on whether the bit is zero) is selected, and the flag generation unit 24
Generates the C, V, N, and Z flags based on the instruction to update all the flags from the third instruction decoder 7, and updates the flag register 25. The C flag indicates the carry from the most significant bit, the V flag indicates the exclusive OR of the carry of the most significant bit and the bit following it, the N flag indicates the most significant bit of the result,
The flag uses information in which all bits of the result are zero as a flag. DEC stage: Instruction 3 The first slot of instruction 3 stored in I1 latch 2 is the first
It is decoded by the instruction decoder 5. ADD as decrypted result
It turns out to be an operation. Based on the decoding, registers R3 and R5 are read from register file 8, and the read values are stored in D11 latch 12 and D21 latch 15, respectively.
And stored in At the same time, the second slot of the instruction 3 stored in the I2 latch 3 is decoded by the second instruction decoder 6.
As a result of the decryption, it is determined that the operation is a SUB operation.
Based on this decoding, the immediate value 4 in the instruction is changed to the D2 selector 10
, Is stored in the D12 latch 13, the register R1 is read from the register file 8, and the read value is stored in the D22 latch 16. At the same time,
The third slot of the instruction 2 stored in the I3 latch 4 is the third slot.
The command is decoded by the command decoder 7. BGT as a result of decryption
It turns out to be an operation. At the same time, the value 00 of the I0 latch 21 is stored in the D0 latch 22. Further, the branch unit 26 satisfies the branch condition, that is, “greater than (>)” by referring to the flag register 25 updated at the same timing based on the fact that the third instruction decoder 7 is decoding the BGT operation. It is determined whether or not the instruction is fetched. If the condition is satisfied, an instruction is given to the instruction fetch unit 27 so that the instruction is fetched two instructions before by the immediate value -2 in the third slot. Therefore, the instruction fetch unit 27 continues the sequential fetch. The determination of the branch condition in the BGT operation is performed if the logical product of the C flag and the negation of the Z flag is true, and the condition is not satisfied if the logical product is false. It is assumed that the condition is satisfied at this timing.

(Timing t5) EX stage: instruction 3 D11 The value of the register R3 stored in the latch 12 and D21
An addition operation is performed by the first operation unit 18 with the value of the register R5 stored in the latch 15, and the operation result is stored in the register R5 of the register file 8. At the same time, D
A subtraction operation (from R1 to 4) is performed between the value 4 stored in the 12 latch 13 and the value of the register R1 stored in the D22 latch 16.
Is performed in the second operation unit 19, and the operation result is stored in the register R1 of the register file 8. Further, at the same time, a branch operation is performed in the third operation unit 20 based on the value-2 stored in the D13 latch 14. At the same time, the selector 00 is set by the value 00 of the D0 latch 22.
3 does not work, and the flag generation unit 24 does not update any flags in the flag register 25. IF stage: instruction 1 When the branch condition in the branch unit 26 at the timing t4 is satisfied, the instruction fetch unit 27 reads the instruction 1 again from the ROM 1, and reads the instruction 1 from the flag control code 00 and the first slot to the third slot. Slots are stored in I0 latch 21 and I1 latch 2 through I3 latch 4, respectively.

Thereafter, the operations described at timings t2 to t5 are repeated until the branch condition in instruction 3 is not satisfied.

In the above-described operation example, only the case where the flag control code is 11 has been described. That is, the flag control code is 01 or 10
In the case of, each of the selectors 23 is the first operation unit 1
8 or the source data from the second operation unit 19, and the flag generation unit 24 generates each flag based on the flag update instruction from the first instruction decoder 5 or the second instruction decoder 6, and generates a flag register 25. To update.
Which flag is generated and updated is determined by the content of the operation specified by the operation code.

3. Recording Medium As an embodiment of the recording medium of the present invention, a magnetic disk (floppy disk, hard disk, etc.), an optical disk (CD-ROM, PD, etc.), a magneto-optical disk, a semiconductor memory (ROM) storing the machine instruction program of FIG. And flash memory).

As described above, according to the present embodiment, the flag control code generation unit 122 of the compiler includes the operation of changing the flag while the operation that can be specified for the slot is not restricted and the degree of parallelism is maintained. The length of the operation code for identifying the slot and generating the flag control code is shortened, thereby improving the code efficiency. 17 and FIG. 18, one instruction is 64 bits, whereas in the present embodiment, one instruction can specify the same function with 32 bits, which means that the code efficiency is twice as high. .

In the processor of this embodiment, three instruction decoders and three operation units are provided to achieve a maximum of three parallel executions. However, four of these units may be provided and four parallel executions may be performed. Or more.
In the case of four-parallel execution, the flag control code may be set to 3 bits to specify that the operation of the first to fourth slots is to be reflected in the flag and that none of the slots is to be reflected. Is set to 2 bits and any one of the first to fourth slots is reflected in the flag. If the flag is not changed, the operation without flag change is performed in the slot for which flag reflection is specified. May be designated, and the flag control code may be left at 2 bits to designate that the operation of the first to third slots is reflected in the flag and that none of the slots is reflected. Thus, the operation of the fourth slot may not be reflected on the flag.

(Embodiment 2) In Embodiment 2, the flag control code of Embodiment 1 is used to reflect the result of the operation of the first slot in the flag, or the result of the operation of the first and second slots. In this order, the flag is reflected, or the first to third
Instead of designating whether the result of the slot operation is reflected on the flag in this order or whether any slot operation is not reflected on the flag.

1. Compiler The configuration and operation of the compiler are the same as those described in the first embodiment except for the operation of the flag control code generation unit 122. The flag control code generator 122 operates based on the following principle.

When the flag control code generation unit 122 determines that the result of the operation of the first slot is reflected in the flag, the flag control code is set to 01, and the result of the operation of the first and second slots is reflected on the flag in this order. When it is determined that the flag control code is set to 10, and when it is determined that the operation results of the first to third slots are reflected in this order in the flag, the flag control code is set to 11 and when it is determined that the operation of any slot is not reflected in the flag. Set the flag control code to 00.

2. Processor 2.1 Instruction Configuration FIG. 12 is an instruction configuration diagram of the processor according to the second embodiment of the present invention. The instruction format is the same as the instruction format of the processor in the first embodiment shown in FIG. 9A, as shown in FIG.
Are different only in the bit assignment of the flag control code. That is, any number of operations that change the flag can be specified at the same time, but the number of slots that can be specified is limited by the number of operations that reflect the flag. The flag control code is set to 01 when the result of the operation of the first slot is reflected on the flag, and the flag control code is set to 10 when the result of the operation of the first and second slots is reflected on the flag in this order. When the result of the operation of the third slot is reflected on the flag in this order, the flag control code is set to 11, and when the result of the operation of any slot is not reflected on the flag, the flag control code is set to 00.

2.2 Configuration of Processor FIG. 13 is a schematic configuration diagram of the processor in the embodiment.

In FIG. 13, the same components as those of the processor according to the first embodiment are denoted by the same reference numerals.
31, 32 and 33 are the first instruction decoder 5, the second instruction decoder 6 and the third instruction decoder 6 in the processor of the first embodiment, respectively.
In addition to the function of the instruction decoder 7, a first instruction decoder, a second instruction decoder, and a third instruction decoder which output 2-bit information for identifying the type of the flag to be changed. Indicates that none of the flags change when the value is 00, that only the Z flag changes when the value is 01, that the N flag and the Z flag change when the value is 10, and that when the value is 11, Indicates that the flag changes.
34 is a D3 latch for holding the 2-bit information from the first instruction decoder 31, 35 is a D4 latch for holding the 2-bit information from the second instruction decoder 32, and 36 is a third instruction decoder. 33 is a D5 latch that holds the 2-bit information from 33. 37 is the value of the D3 latch 34 (this is G1), the value of the D4 latch 35 (this is G2), the value of the D5 latch 36 (this is G3), and D
A flag generation reorder unit that generates C, V, N, and Z flags from the first operation unit 18 using source data from the third operation unit 20 based on the contents of the 0 latch 22 (this is FC). is there. Other configurations are the same as those of the processor in the first embodiment.

FIG. 14 shows the flag generation reorder unit 37.
Is a truth table showing the generation logic of each flag of G1, G
2, G3 and FC determine the C flag generation logic SC, V flag generation logic SV, N flag generation logic SN and Z flag generation logic SZ. "1" in the column of SC to SZ indicates that each flag is generated using the original data from the first operating unit 18, and "2" indicates that each flag is generated using the original data from the second operating unit 19. "3" indicates that each flag is generated using the original data from the third operation unit 20, and "0" indicates that the flag is not changed. "*" In the column of G1 to G3
“*” Means “don't care”. The source data is
The carry of the most significant bit and the bit following it, the most significant bit of the result and information indicating whether all bits of the result are zero or not. The C flag indicates the carry from the most significant bit.
The V flag uses the exclusive OR of the carry of the most significant bit and the next bit, the N flag uses the most significant bit of the result, and the Z flag uses the information that all bits of the result are zero as flags. , Is the same as the processor of the first embodiment.

2.3 Operation Example of Processor The operation of the processor when the instruction A in FIG. 16 is executed will be described below.

The flag control code of the instruction A is 11, the first slot is an ADD operation for obtaining the sum of R0 and R1, and storing the result in R1, and the second slot is for calculating the logical sum of R2 and R3 and storing the result in R3. SUB operation, third slot T comparing R4 with zero
ST operation. IF stage Instruction A is read from ROM 1, and flag control code 11 of instruction A and first to third slots are stored in I0 latch 21 and I1 latch 2 to I3 latch 4, respectively. • DEC stage (machine cycle of operation of IF stage) The first slot of instruction A stored in I1 latch 2 is the first slot
The instruction is decoded by the instruction decoder 31. AD as a result of decryption
It turns out to be a D operation. Based on the decoding, registers R0 and R1 are read from register file 8, and the read values are stored in D11 latch 12 and D21 latch 1, respectively.
5 is stored. At the same time, the second slot of the instruction A stored in the I2 latch 3 is decoded by the second instruction decoder 32. As a result of the decryption, it is determined that the operation is an OR operation. Based on this decoding, registers R2 and R3 are read from register file 8, and the read values are
The data is stored in the latch 13 and the D22 latch 16. At the same time, the third slot of the instruction A stored in the I3 latch 4 is decoded by the third instruction decoder 33. As a result of the decryption, it is determined that the operation is the TST operation. Based on the decoding, the register R4 is read from the register file 8, and the read value is stored in the D23 latch 17. At the same time, the value 11 of the I0 latch 21 is stored in the D0 latch 22, and the value 11 (all flags change in the ADD operation) is changed to D by the first instruction decoder 31 decoding the ADD operation.
3 is stored in the latch 34 and the OR operation is decoded by the second instruction decoder 32 to obtain a value of 10 (OR operation is performed by the N flag and the Z flag).
The flag change is stored in the D4 latch 35, and the third instruction decoder 33 decodes the TST operation so that the value 01 (T
(Only the Z flag changes in the ST operation) is stored in the D5 latch 36. Also, the branch unit 26 does not function because none of the first to third instruction decoders 5 to 7 has decoded the branch operation, and accordingly, the instruction fetch unit 27 does not function.
Will continue a sequential fetch. EX stage (machine cycle of operation of the DEC stage) The value of the register R0 stored in the D11 latch 12 and D21
An addition operation is performed on the value of the register R1 stored in the latch 15 by the first operation unit 18, and the operation result is stored in the register R1 of the register file 8. At the same time, D
The second operation unit 19 performs an OR operation between the value of the register R2 stored in the 12 latch 13 and the value of the register R3 stored in the D22 latch 16, and the operation result is stored in the register R3 of the register file 8. Is stored in At the same time, a comparison operation (subtracting 0 from R4) is performed in the third operation unit 20 between the value of the register R4 stored in the D23 latch 17 and zero, and the operation result is not stored anywhere. At the same time, the value of FC
= 11, G1 = 11 by the value 11 of the D3 latch 34, G2 = 10 by the value 10 of the D4 latch 35, and G3 = 01 by the value 01 of the D5 latch 36, respectively, to the flag generation reorder unit 37. As shown in the seventh column from the bottom of FIG. 15, the carry from the most significant bit of the first operation unit 18 is set to the C flag based on SC = 1, and the first flag is set based on SV = 1.
The exclusive OR of the carry of the most significant bit of the operation unit 18 and the bit following it is set as a V flag, the most significant bit of the result of the second operation unit 19 is set as an N flag based on SN = 2, and SZ = 3, information that all bits of the result of the third operation unit 20 are zero is set as a Z flag as C, V,
The N and Z flags are generated and the flag register 25 is updated.
As described above, the flag generation reorder unit 37 generates a flag as if the ADD operation, the SUB operation, and the TST operation were sequentially executed in this order.

In the above operation example, only the case where FC = 11, G1 = 11, G2 = 10, and G3 = 01 has been described, but the other cases are exactly the same. That is, each of the C, V, N, and Z flags may be generated using the source data of the first operation unit 18 to the third operation unit 20 according to the truth tables of FIGS.

3. Recording Medium As an embodiment of the recording medium of the present invention, a magnetic disk (floppy disk, hard disk, etc.), an optical disk (CD-ROM, PD, etc.), a magneto-optical disk, a semiconductor memory (ROM, flash, Memory etc.).

As described above, according to the present embodiment, the first
In addition to improving the code efficiency as in the first embodiment, by generating a flag control code for specifying the position of the operation for changing the flag and the order of the flag change,
An operation in which the flag changes in a plurality of slots can be specified, and further improvement in the degree of parallelism is expected. This is due, for example, to the presence or absence of overflow in the ADD operation and SUB
In the case where the sign of the result of the operation and the comparison result of the TST operation are branched in multiple directions, the V flag of the ADD operation, the N flag of the SUB operation, and the Z flag of the TST operation are all in the flag register. This is because three operations can be executed in parallel by one instruction as in instruction A of FIG.

In the processor of this embodiment, one operation can be designated for each of the case where one operation is reflected on the flag, the case where two operations are reflected on the flag, and the case where three operations are reflected on the flag. Although a two-bit flag control code is provided, the number of bits is increased to select one of three types of operation when one operation is reflected on the flag, and three types of operation when two operations are reflected on the flag. All or a part of the six orders of the selection and the order and the six orders in the case where the three operations are reflected on the flag may be designated.

Although three instruction decoders and three operation units are provided to achieve a maximum of three parallel executions, four of them may be provided for four parallel executions, or more. You may.

As described above, the compiler and the processor according to the present invention have been described based on the above two embodiments. However, it is needless to say that the present invention is not limited to these embodiments. That is, (1) In the above two embodiments, in the compiler, the flag control code generation unit 122 generates the flag control code when generating the machine instruction, but the parallel intermediate code generation unit 121 uses the flag when generating the parallel intermediate code. A control code may be generated. (2) The processors of the above two embodiments are configured by a three-stage pipeline of instruction fetch, decoding, and execution. However, the number of stages of the pipeline may be any, and It is not necessary.

[0067]

As is clear from the above description, the compiler, processor and recording medium according to the present invention do not need to have two types of operation descriptions, one in which the flag changes and the other in which the flag does not change. Since the length of the operation description is not lengthened and the operation description that can be included in the machine instruction is not limited, the code efficiency and instruction parallelism are improved at the same time, especially in the development of multimedia-related products. It is very useful and makes a great contribution to the advancement and development of the multimedia related industry.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a compiler according to an embodiment.

FIG. 2 is an exemplary block diagram showing a configuration of a machine instruction generation unit 107 of the compiler according to the embodiment.

FIG. 3 is a flowchart showing a flow of generating a flag control code in a flag control code generation unit 122 of the compiler according to the embodiment;

FIG. 4 is a diagram showing a program list showing an example of a C language program;

FIG. 5 is a diagram showing a list showing a sequential intermediate code program stored in a sequential intermediate code buffer 106 of the compiler according to the embodiment when the C language program shown in FIG. 4 is given as an input;

FIG. 6 is an explanatory diagram relating to parameterization of dependencies in the sequential intermediate code program shown in FIG. 5;

FIG. 7 is a view showing a list showing parallel intermediate code programs generated by a parallel intermediate code generation unit 121 of the compiler according to the embodiment when the C language program shown in FIG. 4 is given as an input;

FIG. 8 is a diagram showing a list showing machine instruction programs generated by the compiler according to the embodiment when the C language program shown in FIG. 4 is given as an input;

FIG. 9 is an instruction configuration diagram of a processor according to the first embodiment.

FIG. 10 is a schematic configuration diagram of a processor according to the embodiment;

FIG. 11 is an operation timing chart corresponding to the machine instruction program of FIG. 8 of the processor according to the embodiment;

FIG. 12 is an instruction configuration diagram of a processor according to a second embodiment.

FIG. 13 is a schematic configuration diagram of a processor according to the embodiment;

FIG. 14 is a truth table showing the generation logic of each flag of the flag generation reorder unit of the processor according to the embodiment;

FIG. 15 is an exemplary diagram of machine instructions of the processor according to the embodiment;

FIG. 16 is an exemplary diagram of machine instructions of the processor according to the embodiment;

FIG. 17 is an instruction configuration diagram of a processor according to the related art.

FIG. 18 is a schematic configuration diagram of a processor according to the related art.

[Explanation of symbols]

 1 ROM 2 I1 latch 3 I2 latch 4 I3 latch 5 First instruction decoder 6 Second instruction decoder 7 Third instruction decoder 8 Register file 9 D1 selector 10 D2 selector 11 D3 selector 12 D11 latch 13 D12 latch 14 D13 latch 15 D21 latch 16 D22 latch 17 D23 latch 18 First operation unit 19 Second operation unit 20 Third operation unit 21 I0 latch 22 D0 latch 23 Selector 24 Flag generation unit 25 Flag register 26 Branch unit 27 Instruction fetch unit 31 First instruction Decryptor 32 Second instruction decoder 33 Third instruction decoder 34 D3 latch 35 D4 latch 36 D5 latch 37 Flag generation reorder unit 101 C language program 102 Compiler 103 File reading unit 10 Read buffer 105 parser 106 sequentially for the intermediate code buffer 107 machine instruction generation unit 108 output buffer 109 File output unit 110 machine instructions programs 120 dependency extracting unit 121 parallel intermediate code generating unit 122 flag control code generation unit

Claims (21)

[Claims] 1. A compiler for generating, from a high-level language program, a machine instruction program in a long-word instruction format for a processor that executes a plurality of operations in parallel and reflects an operation result on a flag, the machine comprising: A compiler comprising: machine instruction generating means for generating a machine instruction including, in an instruction, a plurality of operation descriptions and a flag control description regarding how to reflect an operation result on the flag. 2. The method according to claim 1, wherein the flag control description includes information for specifying one of the plurality of operation descriptions included in the same machine instruction that reflects an operation result in the flag. The compiler according to claim 1, wherein 3. The flag control description includes information for specifying an order in which results of operations performed by the plurality of operation descriptions included in the same machine instruction are reflected on the flag. The compiler according to item 1. 4. The flag control description includes, from among the plurality of operation descriptions included in the same machine instruction, extracting some of the plurality of operation descriptions reflecting the operation result in the flag, 2. The compiler according to claim 1, further comprising information for specifying an order in which the result of the operation according to the operation description is reflected in the flag. 5. The method according to claim 1, wherein a number of the operation descriptions included in one word of the machine instruction is equal to a maximum number of operations executed in parallel by the processor. Compiler as described in section. 6. A processor for executing an instruction in a long-word instruction format for designating a plurality of operations, comprising: a description of the number of operations that can be executed in parallel; and a flag control description relating to a method of reflecting operation results on a flag. A processor that fetches an instruction that includes the following at the same time, executes the operation according to the operation description in parallel, and reflects an operation result of the parallel execution in a flag according to the flag control description. 7. The flag control description is configured to include information for specifying one of the plurality of operation descriptions included in the same machine instruction that reflects an operation result in the flag. The processor of claim 6, wherein: 8. The flag control description is configured by information for specifying an order in which results of operations performed by the plurality of operation descriptions included in the same machine instruction are reflected in the flag. Item 7. The processor according to Item 6. 9. The flag control description includes, from among the plurality of operation descriptions included in the same machine instruction, extracting some of the plurality of operation descriptions reflecting the operation result in the flag, and extracting the extracted some. 7. The processor according to claim 6, comprising information for specifying an order in which the result of the operation according to the operation description is reflected in the flag. 10. A processor for executing a long-word instruction format instruction for designating a plurality of operations, comprising: a description of the number of operations that can be executed in parallel; and a flag control description relating to a method of reflecting operation results on flags. Instruction reading means for retrieving an instruction which simultaneously includes: an instruction decoding means for decoding the operation description and executing an operation in parallel based on the decoding result; and a flag for the operation result in the instruction decoding execution means according to the flag control description. And a flag generation / holding unit for reflecting the result to a processor. 11. The flag control description is configured to include information for specifying one of the plurality of operation descriptions included in the same machine instruction that reflects an operation result in the flag. The processor of claim 10, wherein: 12. The command decoding and executing means outputs a set of source data each of which is a source data for generating a flag and which is equal to a number which can be executed in parallel. A selector for selecting one from the set of source data output by the instruction decoding and executing unit according to the description; a flag generating unit for generating flag data using the source data output by the selector; 12. A flag register for holding flag data to be generated.
Processor as described. 13. The flag control description includes information for specifying an order in which results of operations performed by the plurality of operation descriptions included in the same machine instruction are reflected in the flag. Item 11. The processor according to item 10. 14. The flag control description extracts, from among the plurality of operation descriptions included in the same machine instruction, some that reflect the result of the operation on the flag, and extracts the some 11. The processor according to claim 10, comprising information for specifying an order in which the result of the operation according to the operation description is reflected in the flag. 15. The instruction decoding and executing means comprises: a set of information each of which is information on which flag changes and which is equal to the number which can be executed in parallel; and each is source data for generating a flag. Outputting a set of source data equal to the number that can be executed in parallel, the flag generation and holding means, for each flag, according to the flag control description and the information, the source data set output by the instruction decoding execution means And a flag register for holding the flag data generated by the flag generating unit. The flag generating unit generates flag data using the determined source data. Item 13
Or a processor according to 14. 16. The processor according to claim 15, wherein said flag generating means generates flag data relating to the operation with priority given to an operation specified later by said flag control description. 17. A recording medium recording a machine instruction program executed by a processor that executes a plurality of operations simultaneously and in parallel and reflects an operation result on a flag, wherein one machine instruction includes a plurality of operation descriptions, And a flag control description relating to how the operation result is reflected in the flag. 18. A recording medium on which a machine instruction program to be executed by a processor is recorded, the medium including a number of operation descriptions that can be executed simultaneously in parallel and a flag control description on how to reflect operation results on flags. A first step of fetching an instruction in a long-word instruction format, a second step of executing the operation according to the operation description in parallel, and a third step of reflecting an operation result of the parallel execution in a flag according to the flag control description to a processor A recording medium that stores a machine instruction program to be executed. 19. The flag control description is configured to include information for specifying one of the plurality of operation descriptions included in the same machine instruction that reflects an operation result in the flag. 19. The recording medium according to claim 17, wherein: 20. The flag control description comprises information for specifying an order in which results of operations performed by the plurality of operation descriptions included in the same machine instruction are reflected in the flag. Item 17 or 1
8. The recording medium according to 8. 21. The flag control description includes: extracting, from the plurality of operation descriptions included in the same machine instruction, some of the plurality of operation descriptions that reflect the operation result in the flag; 19. The recording medium according to claim 17, comprising information for specifying an order in which an operation result according to the operation description is reflected in the flag.