JP2000081982A - Compiler, processor and recording medium - Google Patents

Abstract

(57) [Summary] [Problem] An operation corresponding to a plurality of arithmetic units provided in a processor is specified in each slot of an instruction of a VLIW processor.
Since it is not always possible to schedule as many operations as the number of slots that can be executed in parallel, the nop code placed in the instruction increases the program size. Furthermore, nop is inserted as the parallelism of instructions increases.
The number of codes increases, and the code efficiency further deteriorates. SOLUTION: A compiler divides and fills an effective operation into a nop code position as necessary, and a processor accumulates and executes the effective operation. Further, the n-parallel execution operation is embedded in n nop codes of the instruction of m (m <n) slots, or the (n-m) of the n-parallel execution operation is (nm) instructions of the m-slot. Nop
Embed in code.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compiler, a processor, and a storage medium.
Includes technologies related to improving the execution code efficiency of IW (Very Long Instruction Word) type processors.

[0002]

2. Description of the Related Art With the recent development of electronic technology, high-performance processors have become widespread and used in all fields.
Such a processor achieves high performance by parallel processing of instructions. An architecture called VLIW is also one form of instruction parallel processing. A processor employing the VLIW architecture (hereinafter referred to as a “VLIW processor”) has a plurality of arithmetic units inside and a slot provided for one instruction. Performs the operations specified in multiple fields, called, concurrently and in parallel. Such a VL
The machine instruction program of the IW processor is generated after the parallelism at the operation level in a program described in a high-level language is detected and scheduled by a compiler. The machine instruction program is also called an execution code.

(First Prior Art) FIG. 21 is a block diagram of a processor according to the first prior art.

A processor according to the first prior art executes two operations in parallel, and a program composed of an instruction sequence composed of first and second two slots as shown in FIG. After the operation written in each slot is decoded by the first instruction decoder 4 and the second instruction decoder 5, it is executed by the first operator 13 and the second operator 14.

(Second Prior Art) FIG. 22 is a block diagram of a processor according to a second prior art.

The processor according to the second prior art executes three operations in parallel, but the basic concept is the same as that of the processor according to the first prior art, and the first to third processors as shown in FIG. A program composed of an instruction sequence consisting of three slots is stored in the ROM 41, and the operations written in the respective slots are decoded by the first instruction decoder 45 to the third instruction decoder 47. The processing is executed by the third computing unit 60 from 58. That is, the number of slots constituting one instruction merely increases.

[0007]

However, any of the above prior arts has a problem that the program size is increased by a no operation code (nop code) placed in an instruction. Note that an increase in program size is also expressed as a decrease in code efficiency. Each slot of the VLIW processor instruction specifies an operation corresponding to multiple operation units of the processor.However, due to the dependence of operations, it is not always possible to schedule as many operations as the number of slots that can be executed in parallel. Because there is no. If a valid operation cannot be placed, the compiler generates nop code in that slot.

In the above-mentioned first prior art, for example, as shown in FIG. 5, two valid operations B and C can be designated by an instruction 2, but an effective operation is stored in a second slot by an instruction 1. Can not be specified without
p. In the second prior art, as shown in FIG. 14, for example, a valid operation cannot be designated to the second and third slots in the instruction 1 and to the third slot in the instruction 2, and the operation becomes nop. ing. As described above, in general, the VLIW processor has a problem that the number of nop codes to be inserted increases as the parallelism of instructions increases, and the code efficiency further deteriorates. This is because the probability that a valid operation can be scheduled for all slots in the compiler is inversely proportional to the degree of parallelism.

Accordingly, it is a first object of the present invention to provide a compiler and a processor that reduce a useless area in an instruction.

A second object of the present invention is to provide a compiler and a processor for reducing an increase in nop code due to an improvement in the degree of instruction parallelism in a VLIW processor.

[0011]

The compiler according to the present invention generates a long-language instruction format instruction from a high-level language program for a plurality of operations that can be simultaneously executed by a processor, and then sets the nop included in the instruction after the nop. The method is characterized in that the operation is replaced with a valid operation to be executed, the valid operation is deleted, and information indicating that the operation has been replaced is added. As a result, nop can be replaced with a valid operation, and the code size can be reduced.

A processor for executing such an instruction temporarily stores the instruction in an accumulation buffer based on the value of an accumulation bit in the instruction, and then executes the instruction stored in the accumulation buffer. Processor.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) In Embodiment 1, the nop
Instead of this, an instruction in which a valid operation is arranged is temporarily stored and then executed, thereby reducing the code size.

1. Compiler FIG. 1 is a block diagram showing a configuration of the compiler.

The compiler 102 executes the C
Translates the language program 101 into the machine instruction program 1
12 is output.

The compiler 102 executes the C language program 1
01 into the read buffer 104, and a syntax analyzer 10 that analyzes the syntax and meaning of the C language program read into the read buffer 104, generates intermediate code, and writes the intermediate code into the intermediate code buffer 106.
5, an intermediate code stored in the intermediate code buffer 106 is input, an instruction for the purpose of two-parallel execution of the instruction is scheduled, an uncompressed machine instruction program is generated, and a machine instruction to be written to the provisional output buffer 108 A generation unit 107, a machine instruction compression unit 109 that compresses the uncompressed machine instruction program stored in the provisional output buffer 108 to generate a target machine instruction program and writes it to the output buffer 110, And a file output unit 111 that outputs the stored machine instruction program to a file. Here, "compression of the machine instruction program" means to replace the nop code included in each instruction of the machine instruction program with a valid operation. The components other than the machine instruction compression unit 109 that performs this compression may be configured based on a known technique, and thus description thereof is omitted here. The machine instruction compression unit 109 operates based on the following principle, which will be described in detail below.

An uncompressed machine instruction program is searched in the order of instructions to extract a pair of the first slot nop code and the second slot nop code in the same order, and the first slot and the second slot of the nop code pair are extracted. The two slots are replaced with the operations of the first slot and the second slot of the pair of valid operations that appear first after the pair, respectively, and the replacement is marked, and the pair of valid operations used for replacement is deleted. This places an instruction containing two valid operations in place of the earlier nop, and nop
Is to reduce.

FIGS. 2 to 4 are flowcharts showing the processing flow of the machine instruction compression unit 109.

The processing flow of the machine instruction compression unit 109 will be described in detail using the following operation example.

1.1 Example of Operation of Machine Instruction Compression Unit 109 FIG. 5 is a view showing an example of an uncompressed machine instruction program.
This is generated by the machine instruction generation unit 107 according to the above-described first related art.

The instruction consists of two slots, first and second, where the symbols A through J indicate a valid operation, while nop indicates n.
Indicates that an op code has been generated.

FIG. 6 is a view showing an example of a compressed machine instruction program. The machine instruction compression unit 109 compresses the uncompressed machine instruction program of FIG. 5 in the following procedure.

The instruction is composed of first and second two slots, each of which consists of one accumulated bit and an operation (OP) field. The symbols from A to J are shown in Fig. 5.
Indicates a valid operation as in.

The operation of the machine instruction compression unit 109 when the program shown in FIG. 5 is input will be described below with reference to FIGS.

As shown in FIG. 2, first, initialization is performed. Initialization is performed by setting the instruction pointer N to the first instruction, that is, the instruction 1 in FIG. 5, setting the instruction prefetch counter m to 1, the first slot nop counter C1 and the second slot nop.
Setting the counter C2 to 0, setting the first slot buffer counter B1 to 0, the second slot buffer counter
B2 is set to 0 (step S201). here,
N, m, C1, C2, B1, and B2 are parameters created internally by the machine instruction compression unit 109.

Next, the instruction indicated by N, that is, the type of the instruction 1 in FIG. 5 is evaluated. Instruction 1 is operation A where the first slot is valid and the second slot is a nop code.
(1): nop (2) type ”and jumps to process A (step S20
2). (1) and (2) mean the first slot and the second slot.

In the process A shown in FIG. 3, first, the second slot nop counter C2 is incremented to C2 = 1, and the second slot buffer counter B2 is incremented to B2 = 1 (step S301). Next, the first slot nop counter is added to the internally generated parameter C1X of the machine instruction compression unit 109.
The value of C1 is substituted, and C1X = 0 (step S302). Next, the instruction indicated by (N + m), that is, the type of the instruction 2 in FIG. 5 is evaluated. The instruction 2 is an operation A or B in which the first and second slots are respectively valid, so that “OP (1): OP (2) type” is applicable, and the process jumps to step S312 (step S303). Now, B2 = 1 and B2 ≦
2, but does not satisfy C1X ≧ 1 in step S307 (C1 = 0), and then jumps to step S305. Here, the condition of C1X ≧ 1 is that a replacement target is newly obtained by replacing only the second slot, such as replacing OP (1): OP (2) with OP (1): NOP (2). Is to be prevented from being generated. That is, by adding this condition, OP (1): OP (2) is eventually replaced with NOP (1): NOP (2) and deleted. The condition that B2 ≦ 2 is satisfied is that the processor shown in FIG.
Two sets of buffers are provided for each slot to prevent replacement beyond this. Here, since the instruction indicated by (N + m), that is, the instruction 2 in FIG. 5, is not the last instruction, the process proceeds to step S306 (step S305).
The instruction prefetch counter m is set to 2 to proceed to the next instruction, and the process returns to step S303 (step S306).

Next, the type of the instruction indicated by (N + m), this time, the type of the instruction 3 in FIG. 5 is evaluated. Instruction 3 is operation D where the first slot is valid and the second slot is a nop code.
“OP (1): nop (2) type” is applicable, and the process jumps to step S305 (step S303). Instruction indicated by (N + m), that is, instruction 3 in FIG.
Is not the last instruction, so the process proceeds to step S306.
(S305), the instruction prefetch counter m is set to 3, the process proceeds to the next instruction, and the process returns to step S303 (step S306).

Next, the type of the instruction indicated by (N + m), this time, the type of the instruction 4 in FIG. 5 is evaluated. Instruction 4 is operation E where the first slot is nop code and the second slot is valid.
“Nop (1): OP (2) type” is applicable, and the process jumps to step S304 (step S303). Here, 1 is added to C1X, and C1X = 1 (step S304). Since the instruction indicated by (N + m), that is, the instruction 4 in FIG. 5 is not the last instruction, the process proceeds to step S306 (step S305), the instruction prefetch counter m is set to 4, the process proceeds to the next instruction, and the process returns to step S303. Step S306).

Next, the instruction indicated by (N + m), that is, the type of the instruction 5 in FIG. 5 is evaluated. Since instruction 5 is an operation F or G in which the first and second slots are respectively valid, "OP (1): OP
(2) type "and jumps to step S312 (step S30
3). Now, B2 = 1 and B2 ≦ 2 are satisfied, and step S3
The process satisfies C1X ≧ 1 (C1X = 1) of 07 and jumps to step S308. Here, since OP (2) remains valid, the process jumps to step S309 (step S308), and sets the accumulation bit of the first slot of the instruction indicated by N, that is, the instruction 1 of FIG. Set the accumulation bit of the slot to “1” and OP
Fill fields with operation G instead of nop.
In this way, the fact that OP (2) is valid is determined by the fact that even if OP (2) is present, it is already placed in place of nop, and is an instruction that does not substantially exist. Because there is. Thus, the instruction 1 of FIG. 6 is generated. continue
The instruction indicated by (N + m), that is, OP (2) of instruction 5 in FIG. 5 is invalidated (step S309). At this time, since OP (1) is still valid, the process A is terminated, and the process jumps to step S206 (step S310). As will be described later, when OP (1) is invalid (when already replaced), the instruction is deleted in step S311.

Returning from the process A, the instruction indicated by N, that is, the instruction 1 in FIG. 5 is not the last instruction, and proceeds to step S207 (step S206), and the instruction pointer N is set to the next instruction, that is, the instruction in FIG. Step 2 returns the instruction prefetch counter m to 1,
The process returns to step S202 (step S207).

Subsequently, the type of the instruction indicated by N, that is, the type of the instruction 2 in FIG. 5 is evaluated. Instruction 2 is "OP (1): OP"
(2) type ”and moves to step S205 (step S20
2). Here, the instruction indicated by N, that is, the first instruction of instruction 2 in FIG.
And the accumulation bit of the second slot is set to “0”. Thus, the instruction 2 of FIG. 6 is generated. Subsequently, the instruction indicated by N, that is, the instruction 2 in FIG. 5, moves to step S207 where the instruction is not the last instruction (step S206),
To the next instruction, that is, instruction 3 in FIG. 5, resets the instruction prefetch counter m to 1, and returns to step S202 (step S20).
7).

Subsequently, the type of the instruction indicated by N, that is, the type of the instruction 3 in FIG. 5 is evaluated. Instruction 3 is "OP (1): no"
The “p (2) type” is applicable, and the processing jumps to processing A (step S202).

In the process A, first, the second slot nop counter C2 is incremented to C2 = 2, and the second slot buffer counter B2 is incremented to B2 = 2 (step S3).
01). Next, the first slot nop counter is set to the parameter C1X.
The value of C1 is substituted, and C1X = 0 (step S302). Next, the instruction indicated by (N + m), that is, the type of the instruction 4 in FIG. 5 is evaluated. Instruction 4 corresponds to "nop (1): OP (2) type" as described above, and jumps to step S304 (step S303). Where C1X is 1
Are added and C1X = 1 (step S304). Since the instruction indicated by (N + m), that is, the instruction 4 in FIG. 5, is not the last instruction, the process proceeds to step S306 (step S305), and the instruction prefetch counter
The process proceeds to the next instruction by setting m to 2, and returns to step S303 (step S306).

Next, the instruction indicated by (N + m), that is, the type of the instruction 5 in FIG. 5 is evaluated. Instruction 5 is "OP (1): OP"
(2) type "and jumps to step S307 (step S30
3). Since C1X = 1 now, C1X ≧ 1 is satisfied, and the routine jumps to step S308. Here, since OP (2) has been invalidated before, the process jumps to step S305 (step S308). The instruction indicated by (N + m), that is, instruction 5 in FIG.
Move to S306 (step S305), and set the instruction prefetch counter m to 3
And proceed to the next instruction, and return to step S303 (step
S306).

Next, the type of the instruction indicated by (N + m), that is, the type of the instruction 6 in FIG. 5 is evaluated. Instruction 6 is operation H in which the first slot is a nop code and the second slot is valid.
op (1): OP (2) type "and jumps to step S304 (step S303). Here, 1 is added to C1X, and C1X = 2 (step S304). Instruction indicated by (N + m), that is, instruction 6 in FIG.
Is not the last instruction, so the process proceeds to step S306.
(S305), the instruction prefetch counter m is set to 4, the process proceeds to the next instruction, and the process returns to step S303 (step S306).

Next, the instruction indicated by (N + m), that is, the type of the instruction 7 in FIG. 5 is evaluated. Since instruction 7 is an operation I or J in which the first and second slots are valid, respectively, "OP (1): OP
(2) type "and jumps to step S312 (step S30
3). Now, when B2 = 2, B2 ≦ 2 is satisfied, and step S3
The process satisfies C1X ≧ 1 (C1X = 2) of 07 and jumps to step S308. Here, since OP (2) remains valid, the process jumps to step S309 (step S308), and sets the accumulation bit of the first slot of the instruction indicated by N, that is, the instruction 3 of FIG. Set the accumulation bit of the slot to “1” and OP
Fill fields with operation J instead of nop.
Thus, the instruction 3 in FIG. 6 is generated. Subsequently, the instruction indicated by (N + m), that is, the OP (2) of the instruction 7 in FIG. 5 is invalidated (step S309). At this time, since OP (1) is still valid, the process A ends, and the process jumps to step S206 (step S31).
0).

Returning from the processing A, the instruction indicated by N, that is, the instruction 3 in FIG. 5 is not the last instruction, and proceeds to step S207 (step S206), and the instruction pointer N is set to the next instruction, that is, the instruction in FIG. 4 and return the instruction prefetch counter m to 1.
The process returns to step S202 (step S207).

Subsequently, the type of the instruction indicated by N, that is, the instruction 4 in FIG. 5 is evaluated. Instruction 4 is "nop (1): O"
P (2) type ", and the process jumps to process B (step S202).

In the process B, first, the first slot nop counter C1 is incremented to C1 = 1, and the first slot buffer counter B1 is incremented to B1 = 1 (step S4).
01). Next, the value of the second slot nop counter C2 is substituted into the parameter C2X generated internally by the machine instruction compression unit 109, and C2X = 2 (step S402). Next, the instruction indicated by (N + m), that is, the type of the instruction 5 in FIG. 5 is evaluated. Instruction 5 corresponds to “OP (1): OP (2) type” as described above, and jumps to step S412 (step S403). Now, B1 = 1 and B1 ≦ 2 are satisfied, and C2X ≧ 1 (C2X = 2) in step S407 is satisfied, and the process jumps to step S408. Here, since OP (1) remains valid, the process jumps to step S409 (step S408), and the instruction indicated by N
That is, the storage bit of the second slot of the instruction 4 of FIG.
And set the accumulation bit of the first slot to "
The operation field is set to 1 "and the OP field is filled with operation F instead of nop. Thus, the instruction 4 of FIG. 6 is generated. Subsequently, the instruction indicated by (N + m), that is, the O of the instruction 5 of FIG.
P (1) is invalidated (step S409). Next, since OP (2) has been previously invalidated, the process jumps to step S411 (step
S410). Here, the instruction indicated by (N + m), that is, the instruction 5 in FIG. 5 is deleted, the first slot nop counter C1 and the second slot nop counter C2 are decremented, and C1 = 0, C2 = 1,
The first slot buffer counter B1 and the second slot buffer counter B2 are decremented to B1 = 0 and B2 = 1 (step S411). This ends the processing B, and the step S20
Fly to 6.

Returning from the process B, the instruction indicated by N, that is, the instruction 4 in FIG. 5 is not the last instruction, and proceeds to step S207 (step S206), and the instruction pointer N is set to the next instruction, that is, the instruction in FIG. 6 (the instruction 5 has been deleted), return the instruction prefetch counter m to 1, and return to step S202 (step S202).
207).

Subsequently, the type of the instruction indicated by N, that is, the type of the instruction 6 in FIG. 5 is evaluated. Instruction 6 is "nop (1): O"
P (2) type ", and the process jumps to process B (step S202).

In the process B, first, the first slot nop counter C1 is incremented to C1 = 1, and the first slot buffer counter B1 is incremented to B1 = 1 (step S4).
01). Next, the second slot nop counter is added to the parameter C2X.
The value of C2 is substituted, and C2X = 1 (step S402). Next, the instruction indicated by (N + m), that is, the type of the instruction 7 in FIG. 5 is evaluated. The instruction 7 corresponds to “OP (1): OP (2) type” as described above, and jumps to step S412 (step S403). Now, B1 = 1 and B1 ≦
2 and C2X ≧ 1 in step S407 (C2X = 1)
And jumps to step S408. Here, since OP (1) remains valid, the process jumps to step S409 (step S408), sets the accumulation bit of the second slot of the instruction indicated by N, that is, the instruction 6 of FIG. The storage bit of the slot is set to "1" and the OP field is filled with operation I instead of nop. Thus, the instruction 5 of FIG. 6 is generated. Subsequently, the instruction indicated by (N + m), that is, the OP (1) of the instruction 7 in FIG. 5 is invalidated (step S409).
Next, since OP (2) has been previously invalidated, step S411 is performed.
Jump to (step S410). Here, the instruction indicated by (N + m), that is, the instruction 7 in FIG. 5 is deleted, the first slot nop counter C1 and the second slot nop counter C2 are decremented, and C1 = 0, C2 = 0, Buffer counter B1,
Decrement the second slot buffer counter B2 and B1 =
0 and B2 = 0 (step S411). Thus, the process B ends, and the process jumps to step S206.

Returning from the process B, since the instruction indicated by N, that is, the instruction 6 in FIG. 5, is the last instruction (the instruction 7 has been deleted), all the processing ends (step S206).

As described above, the uncompressed machine instruction program of FIG. 5 is converted into the compressed machine instruction program shown in FIG. Although there is a step in FIGS. 3 and 4 that has not been passed in the above operation example, the description of FIGS. 3 and 4 is omitted because the two slots are complementary.

2. Processor FIG. 7 is a schematic configuration diagram of a processor.

This processor includes an instruction fetch stage (hereinafter, IF stage), a decoding and register reading stage (hereinafter, DEC stage), and an execution stage (hereinafter, EX stage).
(Stage) in a three-stage pipeline structure.

In FIG. 7, 1 is a ROM for storing a machine language program, and 2 and 3 are machine language instructions (hereinafter abbreviated as instructions).
I1 latch and I2 latch for storing the contents of the first slot and the second slot, respectively, and 4 and 5 decode the contents of the first slot and the second slot of the instruction held in the I1 latch 2 and the I2 latch 3, respectively. A first instruction decoder and a second instruction decoder which control each part of the processor, 6 is a register file for storing operands, and 7 and 8 are I1 latches 2
D1 selector and D2 selector for selecting one of two inputs, ie, a part of the contents of the I2 latch 3 and the output of the register file 6, and D11 latches for storing the outputs of the D1 selector 7 and the D2 selector 8, respectively. And D12 latch,
11 and 12 are D2 for storing the output of the register file 6
1 latch and D22 latch, 13 is a first arithmetic unit for performing an arithmetic and logic operation using the contents of the D11 latch 9 and D21 latch 11, and 14 is a first arithmetic unit for performing an arithmetic and logic operation using the contents of the D12 latch 10 and the D22 latch 12. With two arithmetic units,
Outputs of the first computing unit 13 and the second computing unit 14 are both connected to the register file 6. 15 and 16 are I1
The IB11 buffer and the IB12 buffer that hold the contents of the first slot and the second slot of the instruction held in the latch 2 and the I2 latch 3 are collectively referred to as an IB1 buffer. Reference numerals 17 and 18 denote an IB21 buffer and an IB22 buffer which hold the contents of the first and second slots of the instruction held in the I1 latch 2 and the I2 latch 3, respectively.
Both are collectively referred to as an IB2 buffer. The IB1 buffer and the IB2 buffer receive the accumulated bit of each slot as "
The contents are fetched at the time of "1". Reference numerals 23 and 24 are selectors for selecting and outputting either the IB1 buffer or the IB2 buffer, and 19 is one of the contents of the first slot of the instruction read from the ROM 1 and the selector 23. Select the I2 latch 2 and output it to the I1 latch 2. The I2 selector 20 selects either the content of the second slot of the instruction read from the ROM 1 or the selector 24 and outputs it to the I2 latch 3.
When the storage bits of the data stored in the I1 latch 2 and the I2 latch 3 are “1”, the selectors 21 and 22 are nop.
The nop generators 25 and 26 which output (No Operation), when the storage bit becomes "1", invert the write signal to "0" or "1" and output it. At this time, a write signal generator for outputting "0", 27 and 28 are AND circuits for detecting the completion of the storage of the instruction, and 29 generate a signal for stopping the instruction fetch when decoding and executing the stored instruction. OR circuit,
30 and 31 are clocked buffers. In addition, nop
The generators 21 and 22 are constituted by AND circuits for calculating the logical product of the output bits of the I1 latch 2 and the I2 latch 3 and the inverted bit of the storage bit. Means nop (00 ...
0) Output ₂ Also, the write signal generators 25, 2
Reference numeral 6 denotes a T-type flip-flop and an AND circuit, which performs a logical AND operation on the non-inverting output and the trigger input of the T-type flip-flop (accumulated bits of the I1 latch 2 and the I2 latch 3).
The output of the D circuit is used as a write signal to the IB11 buffer 15 and the IB12 buffer 16, and the output of the AND circuit that takes the logical product of the inverted output and the trigger input of the T-type flip-flop is used as the write signal to the IB21 buffer 17 and the IB22 buffer 18. And

The register file 6 contains registers R0 to R7.
And four ports for reading and two ports for writing. That is, four registers at the same time (duplication is allowed)
And writing of two registers (duplication is not allowed). The D1 selector 7 and the D2 selector 8 are controlled by the first instruction decoder 4 and the second instruction decoder 5, respectively.
Select this when the instruction involves a constant value such as an immediate value.

This processor is a so-called VLIW (Very Lon)
g Instruction Word) format, and one operation defines two operations such as operations. The operation of the first slot is stored in the I1 latch 2 and
The instruction is decoded by the instruction decoder 4 and executed by the first calculator 13.
The operation of the second slot is stored in the I2 latch 3, decoded by the second instruction decoder 5, and executed by the second calculator 14. Since two operations are performed simultaneously in this manner, the VLIW type processor is highly efficient.

2.1 Example of Operation of Processor Hereinafter, the operation of the processor having the above configuration when the machine instruction program of FIG. 6 is stored in the ROM 1 will be described with reference to FIG.

FIG. 8 shows that the machine instruction program of FIG.
FIG. 7 is an operation timing chart of the processor when the value is stored in the “1”. The figure shows the operation of the processor, the instruction read from the ROM 1 in the IF stage of the pipeline, the instruction decoded in the DEC stage, the instruction executed in the EX stage,
Instructions held by the B1 buffer and the IB2 buffer are shown at each timing called a machine cycle. Hereinafter, the operation will be described for each timing in order of elapse of time. In the figure, “:” indicates a slot division, the left indicates the first slot, the right indicates the second slot, and “−” indicates that a valid operation is not held or does not operate.

The IB11 buffer 15, IB12 buffer 16, IB21 buffer 17,
It is assumed that the IB22 buffer 18 has been reset.

(Timing t1) IF stage: Instruction 1 Instruction 1 is read from ROM1, the first slot (accumulation bit is "0" and operation A) is in I1 latch 2, and the second slot (accumulation bit is "1"). Operation G)
Are stored in the I2 latch 3. That is, since the operation has not yet been accumulated in the IB buffer (the accumulation bit is not "1"), I1SEL19, I2SEL
20 selects and outputs the output from the ROM 1.

(Timing t2) DEC stage: instruction 1 The contents of the I2 latch 3 whose accumulation bit is "1" (operation G when the accumulation bit is "1") are taken into the IB12 buffer 16. Specifically, since the accumulation bit is "1", the write signal of the IB12 buffer 16 is enabled by the write signal generator 26, and the contents of the I2 latch 3 are accumulated in the IB12 buffer 16. Also, since the accumulation bit of the second slot of the instruction 1 stored in the I2 latch 3 is “1”, the nop generator 22 outputs nop (00... 0) ₂ and the second instruction decoder 5 Outputs a decoding result that does not substantially perform any operation in the EX stage.

On the other hand, the first slot of the instruction 1 stored in the I1 latch 2 is decoded by the first instruction decoder 4. As a result of the decryption, operation A is determined. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is stored in the D11 latch 9 and the D21 latch 11. • IF stage: Instruction 2 Instruction 2 is read from ROM1, the first slot (operation B when the accumulation bit is "0") is stored in the I1 latch 2, and the second slot (operation C when the accumulation bit is "0").
Are stored in the I2 latch 3.

(Timing t3) EX stage: Instruction 1 Operands stored in the D11 latch 9 and the D21 latch 11 are input to the first computing unit 13 to perform the operation A. The calculation result is stored in the register file 6 if necessary.
In a general-purpose register. On the other hand, in the operation G, since the accumulated bit is “1” and is invalidated to “nop” by the nop generator 22, the second computing unit 14 does not operate. • DEC stage: instruction 2 The first slot of instruction 2 stored in I1 latch 2 is the first slot
The instruction is decoded by the instruction decoder 4. As a result of the decryption, operation B is determined. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is stored in the D11 latch 9 and the D11 latch.
21 are stored in the latch 11. On the other hand, the second slot of the instruction 2 stored in the I2 latch 3 is decoded by the second instruction decoder 5. As a result of the decryption, operation C is determined. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is stored in the D12 latch 10 and the D22 latch 12.
Is stored in At this time, since the accumulation bits of both the operations B and C are “0”, the write signal of any of the IB buffers is not enabled, and no write is performed. • IF stage: Instruction 3 Instruction 3 is read from ROM1, the first slot (operation D when the accumulation bit is "0") is stored in the I1 latch 2, and the second slot (operation J when the accumulation bit is "1").
Are stored in the I2 latch 3.

(Timing t4) EX stage: instruction 2 Operands stored in the D11 latch 9 and the D21 latch 11 are input to the first computing unit 13 to perform the operation B. The calculation result is stored in the register file 6 if necessary.
In a general-purpose register. On the other hand, the operands stored in the D12 latch 10 and the D22 latch 12 are input to the second computing unit 14 to perform the operation C. The calculation result is stored in a general-purpose register of the register file 6 as needed. DEC stage: instruction 3 The contents of the I2 latch 3 whose accumulation bit is "1" (operation J when the accumulation bit is "1") are taken into the IB22 buffer 18. Specifically, since the accumulation bit is “1”, an attempt is made to write data to the IB12 buffer 16 or the IB22 buffer 18,
Since the data has been written to the B12 buffer 16, the write signal of the IB22 buffer 18 is enabled by the write signal generator 26. Further, since the accumulation bit of the second slot of the instruction 3 stored in the I2 latch 3 is “1”, the nop generator 22 outputs nop, and the second instruction decoder 5 performs substantially no EX stage. And outputs a decoding result that does not perform the above operation.

On the other hand, the first slot of the instruction 3 stored in the I1 latch 2 is decoded by the first instruction decoder 4. As a result of the decryption, operation D is determined. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is stored in the D11 latch 9 and the D21 latch 11. • IF stage: Instruction 4 Instruction 4 is read from ROM1, the first slot (accumulation bit is “1” and operation F) is in I1 latch 2, and the second slot (accumulation bit is “0” and operation E).
Are stored in the I2 latch 3.

(Timing t5) EX stage: instruction 3 Operands stored in the D11 latch 9 and the D21 latch 11 are input to the first computing unit 13 to perform the operation D. The calculation result is stored in the register file 6 if necessary.
In a general-purpose register. On the other hand, in the operation J, the second arithmetic unit 14 does not operate because the accumulated bit is “1” and is invalidated to “nop” by the nop generator 22. DEC stage: instruction 4 The contents of the I1 latch 2 whose accumulation bit is "1" (operation F when the accumulation bit is "1") are taken into the IB11 buffer 15. Specifically, since the accumulation bit is “1”, the write signal of the IB11 buffer 15 is enabled by the write signal generator 25, and the contents of the I1 latch 2 are accumulated in the IB11 buffer 15. Further, since the accumulation bit of the first slot of the instruction 4 stored in the I2 latch 2 is “1”, the nop generator 21 outputs nop, and the first instruction decoder 4 outputs substantially no data in the EX stage. And outputs a decoding result that does not perform the above operation.

On the other hand, the second slot of the instruction 4 stored in the I2 latch 3 is decoded by the second instruction decoder 5. As a result of the decryption, the operation E is determined. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is stored in the D12 latch 10 and the D22 latch 12. IF stage: IB1 buffer accumulation instruction Since the accumulation bits of the IB11 buffer 15 and the IB12 buffer 16 are both "1", the AND circuit 27 outputs "1" assuming that data has been accumulated in the accumulation buffer,
Further, the OR circuit 29 sets "1" to interrupt the instruction fetch.
Is output. As a result, the instruction fetch is suspended.
At the same time, the accumulation bit of the IB11 buffer 15 becomes "
1 ", the selectors 23 and 24 select and output the IB1 buffer.
The I1 selector 19 and the I2 selector 20 are respectively IB1
One buffer 15 and IB21 buffer 16 are selected, and the stored instructions are stored in I1 latch 2 and I2 latch 3. Thereby, the IB11 buffer 15 and the IB21
Since the instruction stored in the buffer 16 has been used, the timing is adjusted by the clocked buffer 30 and the IB11 buffer 15 and the IB21 buffer 21 are adjusted.
Is reset, and the accumulation bit is set to "0". Although the buffer is reset here,
Only the accumulation bit may be set to “0”. Although not shown in the drawing, the I1 selector 19 and the I2 selector 20 set the accumulation bit to "" when selecting the accumulated instruction.
0 ", and output to the I1 latch 2 and the I2 latch 3.
This is to prevent the nop generators 21 and 22 from invalidating the stored instruction to the nop. Selector 2
The reason why the switching signals 3 and 24 are only the accumulation bits of the IB11 buffer 15 is that the IB11 buffer 15 and the IB12 buffer 16 (or the IB21 buffer 17 and the IB22 buffer 16) always execute the accumulated instruction.
Since the accumulation bit of the buffer 18) is "1", it is not necessary to look up to the accumulation bit of the IB12 buffer 16, and executing the instruction accumulated in the IB1 buffer means that the instruction accumulated in the IB2 buffer is executed. Is a state that has not been executed yet. For this reason, IB
The switching signal is not limited to the stored bits of the 11 buffer 15 but can be a switching signal depending on the value of any stored bit.

(Timing t6) EX stage: instruction 4 In operation F, since the accumulated bit is "1" and the nop generator 21 has invalidated it to nop, the first computing unit 13 does not operate. On the other hand, the operands stored in the D12 latch 10 and the D22 latch 12 are input to the second computing unit 14 to perform the operation E. The calculation result is stored in a general-purpose register of the register file 6 as needed. DEC stage: IB1 buffer storage instruction The first slot stored in the I1 latch 2 is decoded by the first instruction decoder 4. As a result of the decryption, the operation F is determined. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is stored in the D11 latch 9 and the D21 latch 11. On the other hand, the second slot stored in the I2 latch 3 is decoded by the second instruction decoder 5. As a result of the decryption, operation G is determined. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is stored in the D12 latch 10 and the D22 latch 12. • IF stage: Instruction 5 Instruction 5 is read from ROM 1, the first slot (accumulation bit is “1” and operation I) is in I1 latch 2, and the second slot (accumulation bit is “0” and operation H).
Are stored in the I2 latch 3.

(Timing t7) EX stage: IB1 buffer accumulation instruction Operands stored in the D11 latch 9 and the D21 latch 11 are input to the first computing unit 13 to perform the operation F. The calculation result is stored in the register file 6 if necessary.
In a general-purpose register. On the other hand, the operands stored in the D12 latch 10 and the D22 latch 12 are input to the second computing unit 14 to perform the operation G. The calculation result is stored in a general-purpose register of the register file 6 as needed. DEC stage: instruction 5 The contents of the I1 latch 2 whose accumulation bit is "1" (operation I when the accumulation bit is "1") are taken into the IB21 buffer 17. Specifically, since the accumulation bit is “1”, an attempt is made to write data to the IB11 buffer 15 or the IB21 buffer 17,
Since the data has been written to the B11 buffer 15, the write signal of the IB21 buffer 17 is enabled by the write signal generator 25. Also, since the accumulation bit of the first slot of the instruction 5 stored in the I1 latch 2 is “1”, the nop generator 21 outputs nop, and the first instruction decoder 4 outputs substantially no EX stage. And outputs a decoding result that does not perform the above operation.

On the other hand, the second slot of the instruction 5 stored in the I2 latch 3 is decoded by the second instruction decoder 5. As a result of the decryption, operation H is determined. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is stored in the D12 latch 10 and the D22 latch 12. IF stage: IB2 buffer accumulation instruction Since the accumulation flags of the IB21 buffer 17 and the IB22 buffer 18 are both "1", the AND circuit 27 outputs "1" assuming that data is accumulated in the accumulation buffer,
Further, the OR circuit 29 sets "1" to interrupt the instruction fetch.
Is output. As a result, the instruction fetch is suspended.
At the same time, the accumulation bit of the IB11 buffer 15 becomes "
0 "(there is a possibility that there is an instruction stored in the IB2 buffer), so that the selectors 23 and 24 select and output the IB2 buffer. Further, the I1 selector 19 and the I2 selector 20 are output from the OR circuit 29. Selects the IB21 buffer 17 and the IB22 buffer 18, respectively, and stores the stored instruction in the I1 latch 2 and the I2 latch 3. Thereby, the IB21 buffer 17 and the I2 latch 3 are stored.
Since the instruction stored in the B22 buffer 18 has been used, the timing is adjusted by the clocked buffer 31, the contents of the IB21 buffer 17 and the IB22 buffer 18 are reset, and the accumulation flag is set to "0".

(Timing t8) EX stage: instruction 5 In operation I, the accumulated bit is "1" and the nop generator 21 has invalidated it to nop, so the first computing unit 13 does not operate. On the other hand, the operands stored in the D12 latch 10 and the D22 latch 12 are input to the second computing unit 14 to perform the operation H. The calculation result is stored in a general-purpose register of the register file 6 as needed. DEC stage: IB2 buffer storage instruction The first slot stored in the I1 latch 2 is decoded by the first instruction decoder 4. As a result of the decryption, it is determined that the operation is operation I. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is stored in the D11 latch 9 and the D21 latch 11. On the other hand, the second slot stored in the I2 latch 3 is decoded by the second instruction decoder 5. As a result of the decryption, it is determined that the operation is operation J. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is stored in the D12 latch 10 and the D22 latch 12.

(Timing t9) EX stage: IB2 buffer accumulation instruction Operands stored in the D11 latch 9 and the D21 latch 11 are input to the first computing unit 13 to perform the operation I. The calculation result is stored in the register file 6 if necessary.
In a general-purpose register. On the other hand, the operands stored in the D12 latch 10 and the D22 latch 12 are input to the second computing unit 14 to perform the operation J. The calculation result is stored in a general-purpose register of the register file 6 as needed.

3. Recording Medium As an embodiment of the recording medium of the present invention, a magnetic disk (floppy disk, hard disk, or the like) on which the machine instruction program 112 of FIG.
And PD), magneto-optical disks, and semiconductor memory (ROM and flash memory, etc.).

As described above, according to the present embodiment, the machine instruction compression unit 109 of the compiler extracts a pair of the nop code of the first slot and the nop code of the second slot in the same order, and The instruction by replacing the first slot and the second slot of the pair with the operation of the first slot and the second slot of the pair of the valid operation that appears first after the pair, and deleting the valid operation pair used for the replacement. The waste area in the inside is reduced, and the program size can be reduced.

According to the processor of this embodiment,
By providing an IB1 buffer and an IB2 buffer for storing valid operations embedded in scattered conventional nop code positions, and executing this when either of the IB1 or IB2 buffers has two valid operations, It is possible to execute a compressed machine instruction program while maintaining the conventional processing performance.

Further, according to the present embodiment, the conventional nop
Since it is based on the idea that the valid operation in the same slot as the nop code is filled in the position of the code, it is not necessary to transfer the operation between the first slot and the second slot, thereby simplifying the configuration of the processor. Has an effect. Specifically, the operation of the I1 latch 2 is performed by the IB11 buffer 15 or the IB21.
The operation stored in the buffer 17 only needs to be returned to the I1 latch 2 only.
Since the data stored only in the B22 buffer 18 and the operations stored therein need only be returned to the I2 latch 3, the transfer path between the first slot and the second slot and the transfer control means are not required.

In the processor of this embodiment, I1
The selector 19 and the I2 selector 20 are provided on the input side of the I1 latch 2 and the I2 latch 3, respectively. However, the selector 19 and the I2 selector 20 are provided on the output side of the I1 latch 2 and the I2 latch 3, respectively. 5 may be selected. When doing this, IB
The input to the 1 buffer and the IB2 buffer must be changed so as to be performed directly from the ROM 1 in the IF stage. However, the input to the IB1 buffer and the IB2 buffer and the selection of the I1 selector 19 and the I2 selector 20 are the same as in the present embodiment. Can be controlled by the value of the accumulation bit.

In the processor of the present embodiment, IB
Although two accumulation buffers, one buffer and IB2 buffer, are provided, any number may be used. As the number of storage buffers increases, the chances of filling nop codes with valid operations increase, and the program size can be further reduced. This can be easily understood from, for example, assuming that there is no IB2 buffer in the processor of the present embodiment, because the nop code in the second slot of the instruction 3 in FIG. 5 is not filled with a valid operation.

(Embodiment 2) Embodiment 2 is different from Embodiment 1 in that the degree of freedom in filling the nop code slot in the effective operation is increased.

1. Compiler The configuration of the compiler is the same as that described in the first embodiment except for the operation of the machine instruction compression unit 109. The machine instruction compression unit 109 is shown in FIGS. 10 to 12, and operates based on the following principle.

An uncompressed machine instruction program is searched in the order of instructions to extract two nop codes whose appearance order is continuous regardless of either the first slot or the second slot. , The operation of the first slot and the operation of the second slot of the effective operation pair appearing first after the two nop codes are respectively replaced and marked as replaced, and the effective operation pair used for replacement is deleted, The first and second slots of the instruction immediately before the deleted pair
Mark one of the slots as deleted.
That is, in the compiler of the first embodiment, the nop is deleted for each slot, but the compiler of the present embodiment replaces the nop with an effective operation in the order of appearance without considering the slot. For this reason, even if nop is concentrated in any of the slots, it can be replaced with an effective operation.

1.1 Example of Operation of Machine Instruction Compression Unit 109 FIG. 9 is a view showing an example of a compressed machine instruction program. It is compressed. The compressed instruction is made up of two slots, a first and a second, where each slot has an accumulation bit, a position bit, and an operation (O
P) field. The symbols A to J indicate valid operations. The accumulated bits and position bits are encoded as follows. 00, 01 Do nothing 10 Should be stored in IB1 buffer 11 Should be stored in IB2 buffer More specifically, operation F of instruction 5 in FIG.
And operation G are buried in the nop code slot of instruction 1 and instruction 3, and operation I and operation J of instruction 7 are buried in the nop code slot of instruction 4 and instruction 6. The accumulation bit is set to 01, and instructions 5 and 7 are deleted. The operation F, the operation G, the operation I, and the operation J are in this order, the first slot of the IB1 buffer,
It is assumed that the data is stored in the second slot and the first and second slots of the IB2 buffer, and 10 is stored in the storage bit of the second slot of the instruction 4 immediately before the deleted instruction 5, and 10 is deleted. 11 is set to the accumulation bit of the second slot of the instruction 6 immediately before the instruction 7. The accumulated bits of the other slots are 00. The machine instruction program generated in this way is shown in FIG. Note that the instruction 5 in FIG. 9 is generated from the instruction 6 in FIG.

When FIG. 10 is compared with FIG. 2, the point where the nop counter is one (S501) and the point where the position bit is set (S501) are set.
505) are different. The reason why the number of nop counters is one is that in the present embodiment, unlike the first embodiment, there is no need to be aware of the slot. However, this nop counter is used for a completely different purpose from the nop counter of FIG. 2, and repeats "0" and "1" every time nop applies for determining the value of the position bit. .

FIGS. 11 and 12 are basically the same as FIGS. 3 and 4, except that the value of the position bit is determined by the nop counter (S609, S709). Another difference is that C = 0 when an instruction is deleted due to the use of the above-mentioned nop count (S611, S711).

2. Processor FIG. 13 is a schematic configuration diagram of an IF stage portion of the processor.

The DEC stage and the EX stage, not shown, have the same structure as in FIG.
The same components as those described above are denoted by the same reference numerals. 7 is different from FIG. 7 in that selectors 32 and 33 are provided. That is, depending on the value of the position bit, the instruction stored in the I1 latch 2 is stored in the IB12 buffer 16 or the IB22 buffer 18, and the instruction stored in the I2 latch 3 is stored in the IB11 buffer 15 or the IB21 buffer 17. Can be accumulated, and the nop can be further reduced as compared with the first embodiment. Other operations are the same as those in the first embodiment, and a description thereof will not be repeated.

3. Recording Medium As an embodiment of the recording medium of the present invention, a magnetic disk (floppy disk, hard disk, etc.), an optical disk (CD-ROM, PD, etc.), a magneto-optical disk, a semiconductor memory (ROM) storing the machine instruction program of FIG. And flash memory).

As described above, according to the present embodiment, the machine instruction compression unit 109 of the compiler performs
Appearance order is continuous regardless of one of the slots 2
Extract two nop codes, replace the nop code slot with the operation of the first slot and the operation of the second slot of the pair of valid operations that appear first after the two nop codes, respectively, and use the pair of valid operations used for the replacement. Is deleted, the useless area in the instruction is reduced, and the program size can be reduced.

According to the processor of this embodiment,
Providing an IB1 buffer and an IB2 buffer for storing valid operations embedded in scattered conventional nop code positions, and specifying either the IB1 buffer or the IB2 buffer by a storage bit in an instruction immediately before the position to be executed Executing the stored operation enables execution of a compressed machine instruction program while maintaining the conventional processing performance.

Further, according to the present embodiment, since the nop code is filled with valid operations in the order of appearance regardless of the position of the slot, it is determined whether the nop code is in the first slot or the second slot. There is no need to identify, and the configuration of the compiler is changed to the first embodiment.
This has the effect of being simpler than that of

In the processor of this embodiment, I1
The selector 19 and the I2 selector 20 are provided on the input side of the I1 latch 2 and the I2 latch 3, respectively. The selector 19 and the I2 selector 20 are provided on the output side of the I1 latch 2 and the I2 latch 3, respectively. The input may be selected. To do this, the inputs to the IB1 and IB2 buffers are
The IB1 selector 31 and the IB1 selector 31 are changed according to the value of the storage bit of the instruction read from the ROM1.
It is necessary to make a change to control the B2 selector 32. However, as with the present embodiment, it is necessary to control the capture to the IB1 buffer and the IB2 buffer and the selection of the I1 selector 19 and the I2 selector 20 by the value of the accumulation bit as in the present embodiment. Good.

In the processor of the present embodiment, IB
Although two accumulation buffers, one buffer and IB2 buffer, are provided, any number may be used. As the number of storage buffers increases, the chances of filling nop codes with valid operations increase, and the program size can be further reduced. This can be easily understood from the fact that, for example, assuming that there is no IB2 buffer in the processor of the present embodiment, the nop code in the first slot of the instruction 4 in FIG. 5 is not filled with a valid operation.

(Embodiment 3) Embodiment 3 is a VLIW architecture compiler and processor that executes three operations in parallel with an instruction having only two slots.

1. Compiler The configuration of the compiler is the same as that described in the first embodiment except for the operation of the machine instruction generation unit 107 and the machine instruction compression unit 109. The machine instruction generation unit 107 receives the intermediate code stored in the intermediate code buffer 106, schedules the instruction for the purpose of executing the instruction in three parallels (two parallel executions in the first embodiment), and executes the uncompressed instruction. A machine instruction program is generated and written to the provisional output buffer 108. The machine instruction compression unit 109 operates based on the following principle.

An uncompressed machine instruction program is searched in the order of instructions, and three successive appearances are determined regardless of the first slot or the second slot except for the third slot.
extract the nop code and slot these nop code,
From the first slot to the third slot of the instruction in which three valid operations appearing first after the three nop codes are specified.
Replace with each slot operation, mark the replacement, delete the instruction that specifies the three valid operations used for replacement,
Mark the deletion in one of the first slot and the second slot of the instruction immediately before the deleted pair.

1.1 Example of Operation of Machine Instruction Compression Unit 109 FIG. 15 is a view showing an example of a compressed machine instruction program. The machine instruction compression unit 109 converts the uncompressed machine instruction program of FIG. It is compressed. The compressed instruction consists of two slots, a first and a second, each slot having two stored bits and an operation (O
P) field. The symbols A through H indicate valid operations. The two bits of the accumulation bit (left side) and the execution bit (right side) are encoded as follows. 00 Do nothing 10 The operation has been replaced and I
The instruction immediately after 01 should be sequentially stored in the B buffer in the order of the first, second, and third slots 01. The instruction in the IB buffer should be executed 11 (unused). Operation of instruction 5
F, operation G, and operation H are filled in the slots of the nop code of the second slot of the instruction 1, the second slot of the instruction 3, and the first slot of the instruction 4, and the accumulated bits of the filled slots are set to 01. Set and delete instruction 5. The operation F, the operation G, and the operation H are in this order, the first slot of the IB buffer,
It is assumed that data is stored in the second slot and the third slot. The storage bit of the second slot of the instruction 4 immediately before the deleted instruction 5 is set to “1” and the execution bit is set to “0”. The accumulation bits of the other slots are set to "0" and the execution bits are set to "0". The machine instruction program generated in this way is shown in FIG. The "IB buffer" will be described next.

[0092] 2. Processor FIG. 16 is a schematic configuration diagram of a processor.

Compared to FIG. 7, since three operations are executed in parallel with an instruction having only two slots,
The instruction of one slot is internally converted into an instruction of three slots by storing the instruction in three buffers including the IB3 buffer 41. Then, the I3 latch 38 for giving the instruction of the third slot, the nop generator 3
9. The difference is that the third instruction decoder 40 is provided, and further, a D3 selector 34, a D13 latch 35, a D23 latch 36, and a third calculator 37 for executing the instruction of the third slot are provided. In addition, the IB
The write signals of the first buffer 15, the IB2 buffer 16, and the IB3 buffer 41 are sequentially enabled.

2.1 Example of Operation of Processor Hereinafter, the operation of the processor having the above configuration when the machine instruction program of FIG. 15 is stored in the ROM 1 will be described with reference to FIG.

FIG. 17 shows that the machine instruction program of FIG.
FIG. 6 is an operation timing chart of the processor when stored in the ROM 1. The figure shows the operation of the processor in which an instruction read from the ROM 41 at the IF stage of the pipeline, an instruction decoded at the DEC stage, an instruction executed at the EX stage, and an instruction held by the IB buffer are called machine cycles. It is shown for each. Hereinafter, the operation will be described for each timing in order of elapse of time. In the figure,
":" Represents a slot break, the left is the first slot,
The center means the second slot, the right means the third slot,
"-" Indicates that a valid operation is not held or is not operating.

(Timing t1) As an initial state, IB1
Buffer 15, IB2 buffer 16, IB3 buffer 4
Assume that 1 is reset and (0... 00) ₂ is stored in each of them. Also, the ring counter 42 is set to (001) ₂ as an initial state, and when the first operation of which the accumulation bit is “1” is stored in the I1 latch 2 or I2 latch 3, it becomes (100) ₂ and IB
The operation is accumulated in one buffer 15. IF stage: Instruction 1 Instruction 1 is read from ROM 1 and the first slot (operation A) is stored in I1 latch 2 and the second slot (operation F) is stored in I2 latch 3. I3 latch 3
8 stores (0... 00) ₂ of the IB3 buffer 41.

(Timing t2) DEC stage: instruction 1 The contents (operation F) of the I2 latch 3 whose accumulation bit is "1" are taken into the IB1 buffer 15. Specifically, since the accumulation operation is the first operation in which the accumulation bit is "1", the write signal of the IB1 buffer 15 is enabled when the ring counter 42 outputs (100) ₂ , and the contents of the I2 latch 3 are changed to the IB1 buffer 1
5 is stored.

The first slot of the instruction 1 stored in the I1 latch 2 is decoded by the first instruction decoder 4. As a result of the decryption, operation A is determined. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is set to D11.
The data is stored in the latch 9 and the D21 latch 11. On the other hand, I2
Since the accumulation bit of the second slot of the instruction 1 stored in the latch 3 is “1”, the nop generator 22 outputs nop, and the second instruction decoder 5 performs substantially no operation in the EX stage. Output a decoding result that does not occur. Also,
Since the third computing unit 37 does not need to be operated except when executing instructions in three slots, the execution bit is “0”.
In this case, the nop generator 39 outputs nop. IF stage: instruction 2 Instruction 2 is read from ROM 1 and the first slot (operation B) is stored in I1 latch 2 and the second slot (operation C) is stored in I2 latch 3. I3 latch 3
In (1), (0... 00) _{2 of the} IB3 buffer 41 is stored again.

(Timing t3) EX stage: Instruction 1 Operands stored in the D11 latch 9 and the D21 latch 11 are input to the first computing unit 13 to perform the operation A. The calculation result is stored in the register file 6 if necessary.
In a general-purpose register. On the other hand, the second computing unit 14 and the third computing unit 37 do not operate because they are invalidated by the nop generators 22 and 39. • DEC stage: instruction 2 The first slot of instruction 2 stored in I1 latch 2 is the first slot
The instruction is decoded by the instruction decoder 4. As a result of the decryption, operation B is determined. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is stored in the D11 latch 9 and the D11 latch.
21 are stored in the latch 11. On the other hand, the second slot of the instruction 2 stored in the I2 latch 3 is decoded by the second instruction decoder 5. As a result of the decryption, operation C is determined. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is stored in the D12 latch 10 and the D22 latch 12.
Is stored in The execution bit of the I3 latch 38 is "
0 ", the nop generator 39 outputs nop,
The third instruction decoder 40 outputs a decoding result that does not substantially perform any operation in the EX stage. • IF stage: instruction 3 Instruction 3 is read from ROM1, and the first slot (the accumulation bit is (00) ₂ and operation D) is stored in I1 latch 2,
The second slot (accumulated bit is (01) ₂ and operation G) is stored in the I2 latch 3. (0... 00) _{2 of the} IB3 buffer 41 is stored in the I3 latch 38 again.

(Timing t4) EX stage: instruction 2 Operands stored in the D11 latch 9 and the D21 latch 55 are input to the first computing unit 13 to perform the operation B. The calculation result is stored in the register file 6 if necessary.
In a general-purpose register. On the other hand, the operands stored in the D12 latch 11 and the D22 latch 12 are input to the second computing unit 14 to perform the operation C. The calculation result is stored in a general-purpose register of the register file 6 as needed. Further, the third computing unit 37 does not operate because it is invalidated by the nop generator 39. DEC stage: instruction 3 The content (operation G) of the I2 latch 3 whose accumulation bit is (10) ₂ is taken into the IB2 buffer 16.
Specifically, the operation is almost the same as that at the timing t1, but since the operation F has already been accumulated in the IB1 buffer 15, the ring counter 42 is set to (010).
By outputting ₂ , the write signal of the IB2 buffer 16 is enabled, and the operation is accumulated in the IB2 buffer 16.

The first slot of the instruction 3 stored in the I1 latch 2 is decoded by the first instruction decoder 4. As a result of the decryption, operation D is determined. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is set to D11.
The data is stored in the latch 9 and the D21 latch 55. On the other hand, I2
Since the accumulation bit of the second slot of the instruction 3 stored in the latch 3 is “1”, the nop generator 22 outputs nop, and the second instruction decoder 5 performs substantially no operation in the EX stage. Output a decoding result that does not occur. Also,
Since the execution flag is “0”, the nop generator 39 outputs n
op, and the third instruction decoder 40 outputs a decoding result that does not substantially perform any operation in the EX stage. IF stage: instruction 4 Instruction 4 is read from ROM 1 and the first slot (operation H) is stored in I1 latch 2 and the second slot (operation E) is stored in I2 latch 3. I3 latch 3
8 stores (0... 00) _{2 of the} IB3 buffer 41 again.

(Timing t5) EX stage: Instruction 3 Operands stored in the D11 latch 9 and the D21 latch 55 are input to the first computing unit 13 to perform the operation D. The calculation result is stored in the register file 6 if necessary.
In a general-purpose register. On the other hand, the second computing unit 14 and the third computing unit 37 have no effect because they are invalidated by the nop generators 22 and 39. DEC stage: instruction 4 The contents (operation H) of the I1 latch 2 whose accumulation bit is "1" are taken into the IB3 buffer 41. At this time, since the operations are already stored in the IB1 buffer 15 and the IB2 buffer 16, the ring counter 42 outputs (001) ₂ to enable the write signal of the IB3 buffer 41, and the operation is stored in the IB3 buffer 41. Stored. Also, I1
Since the accumulation bit of the first slot of the instruction 4 stored in the latch 2 is “1”, the nop generator 21 outputs nop, and the first instruction decoder 4 performs substantially no operation in the EX stage. Output a decoding result that does not occur.

On the other hand, the second slot of the instruction 4 stored in the I2 latch 3 is decoded by the second instruction decoder 5. As a result of the decryption, the operation E is determined. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is stored in the D12 latch 11 and the D22 latch 12.
Further, since the execution flag is “0”, the nop generator 3
9 outputs nop, and the third instruction decoder 40 outputs a decoding result that does not perform any operation in the execution stage. IF stage: IB buffer accumulation instruction Since the execution bit of the second slot of the instruction 4 stored in the I2 latch 3 is “1”, the instruction fetch control unit interrupts the instruction fetch. At the same time, the I1 selector 19 and the I2 selector 20
5, the IB2 buffer 16 is selected, and the I1 latch 2, I2
The IB1 buffer 15, I
The contents of the B2 buffer 16 and the IB3 buffer 41 are stored. When the execution bit of the I3 latch 38 becomes "1", the contents of the IB buffer are reset.

(Timing t6) EX stage: instruction 4 The first computing unit 13 and the third computing unit 37 are the nop generator 21,
It has no effect because it has been invalidated by the nop generator 39. On the other hand, the operands stored in the D12 latch 10 and the D22 latch 12 are input to the second computing unit 14 to perform the operation E. The calculation result is stored in a general-purpose register of the register file 6 as needed. DEC stage: IB buffer storage instruction The first slot stored in the I1 latch 2 is decoded by the first instruction decoder 4. As a result of the decryption, the operation F is determined. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is stored in the D11 latch 9 and the D21 latch 55. On the other hand, the second slot stored in the I2 latch 3 is decoded by the second instruction decoder 5. As a result of the decryption, operation G is determined. The general-purpose register is read from the register file 6 based on the decoding, and the read value or the constant value in the instruction is stored in the D12 latch 11 and the D22 latch 12.
The third slot stored in the I3 latch 3 is decoded by the third instruction decoder 40. That is, the execution bit is "
Since the value is 1 ", the nop generator 39 outputs the contents of the I3 latch 38 as it is, and it is determined that the operation is operation H as a result of the decoding. The read value or the constant value in the instruction is the D13 latch 35 and D2
3 latch 36.

(Timing t7) EX stage: IB buffer accumulation instruction Operands stored in the D11 latch 9 and the D21 latch 55 are input to the first computing unit 13 to perform the operation F. The calculation result is stored in the register file 6 if necessary.
In a general-purpose register. On the other hand, the operands stored in the D12 latch 11 and the D22 latch 12 are input to the second computing unit 14 to perform the operation G. The calculation result is stored in a general-purpose register of the register file 6 as needed. The D13 latch 35 and the D23 latch 36
Is input to the third computing unit 37 to perform the operation of operation H. The calculation result is stored in a general-purpose register of the register file 6 as needed.

3. Recording Medium As an embodiment of the recording medium of the present invention, a magnetic disk (floppy disk, hard disk, etc.) and an optical disk (CD-ROM, PD
), A magneto-optical disk, and a semiconductor memory (such as a ROM or a flash memory).

As described above, according to the present embodiment, the machine instruction compression unit 109 of the compiler determines that the three nop sequences whose appearance order is continuous regardless of either the first slot or the second slot except for the third slot. Extract the code and these n
The op code slot is replaced with the first to third slot operations of an instruction in which three valid operations appearing first after the three nop codes are specified, and the three valid operations used for replacement are specified. By deleting the instruction to be executed, a waste area in the instruction is reduced, and the program size can be reduced. In particular, according to the present embodiment, the conventional three-parallel execution using an instruction consisting of three slots has been replaced by the conventional no
Since the instruction can be executed with an instruction consisting of two slots using a slot serving as a p-code, the code efficiency is extremely high. In the operation example described above, 3 slots × 5 instructions in FIG.
It can be seen that 15 slots are compressed to 2 slots × 4 instructions = 8 slots in FIG.

Further, according to the processor of the present embodiment,
By providing an IB buffer for storing valid operations embedded in scattered conventional nop code positions and executing the stored operation by specifying the IB buffer with a storage bit in an instruction immediately before the position to be executed, It is possible to execute the compressed machine instruction program while maintaining the conventional processing performance.

In the processor of this embodiment, I1
The selector 19 and the I2 selector 20 are provided on the input side of the I1 latch 2 and the I2 latch 43, respectively.
The output of the I1 latch 2 and the I2 latch 3, respectively, may be provided to select the input of the first instruction interpreter 4 and the second instruction decoder 4. When doing this, IB
In the IF stage, the input to the buffer must be changed so as to be performed directly from ROM1, and the value of the accumulation bit of the instruction read from ROM1 must be changed so as to control the IB selector 66. The selection of the I1 selector 19 and the I2 selector 20 may be controlled by the value of the accumulation bit as in the present embodiment.

In the processor of this embodiment, IB
Although one accumulation buffer called a buffer is provided, a plurality of storage buffers may be provided. Nop as the number of accumulation buffers increases
The opportunity to fill the code with valid operations increases, and the program size can be further reduced.

Furthermore, in the processor of the present embodiment, three instruction decoders and three arithmetic units are provided to achieve a maximum of three parallel executions. Or more. In the case of four-parallel execution, the effective operation may be filled by using four slots that become a nop code when the two-slot instruction is uncompressed, as in the present embodiment. The effective operation may be filled by using four slots that are nop codes when not compressed. However, in the former case, it is necessary to provide an additional IB buffer for another slot. The former is effective when the number of slots that become nop codes when uncompressed is extremely large compared to the latter, and a considerable improvement in code efficiency can be expected. By doing so, even if the parallelism of instructions in the VLIW processor is improved, the increase in nop code can be greatly reduced.

(Embodiment 4) Embodiment 4 differs from Embodiment 3 in that only the operation of the third slot is performed by the first slot.
Alternatively, it is changed so as to fill the slot of the nop code of the second slot.

1. Compiler The configuration of the compiler is the same as that described in the third embodiment except for the operation of the machine instruction compression unit 109. The machine instruction compression unit 109 operates based on the following principle.

An uncompressed machine instruction program is searched in the order of instructions, and one nop code is extracted irrespective of either the first slot or the second slot except for the third slot. The third slot which appears first after the nop code is replaced with the operation of the instruction whose valid operation is specified, the replacement is marked, and the third slot of the instruction whose valid operation used for replacement is specified is Delete and mark the deletion in either the first slot or the second slot of the instruction.

1.1 Operation Example of Machine Instruction Compression Unit 109 FIG. 18 is a view showing an example of a compressed machine instruction program. The machine instruction compression unit 109 converts the uncompressed machine instruction program of FIG. It is compressed. The compressed instruction consists of two slots, a first and a second, each slot having two stored bits and an operation (O
P) field. The symbols A through H indicate valid operations, and nop indicates an invalid nop code. Two bits of the stored bits are encoded as follows. 00 Does nothing 01 The operation has been replaced and I
The operation of the IB buffer should be executed in the third slot since the third slot has been deleted. 11 (Unused) Specifically, the operation is the operation placed in the third slot. , Operation H of instruction 5 in FIG.
Fill in the nop code slot of the second slot of instruction 1,
The accumulation bit of the filled slot is set to 01, and the third slot of the instruction 5 is deleted. Operation H is
It is assumed that the data is accumulated in the IB buffer.
The storage bit of the second slot of the instruction 5 from which the slot has been deleted is set to 10 (it may be the storage bit of the first slot). The accumulated bits of other slots are 00
It is. The machine instruction program generated in this way is shown in FIG. Here, the nop codes of the second slot of the instruction 3 and the first slot of the instruction 4 remain without being replaced. The "IB buffer" will be described next.

[0116] 2. Processor FIG. 19 is a schematic configuration diagram of an IF stage portion of the processor.

The parts not shown of the DEC stage and the EX stage have the same configuration as in FIG. 16, and the same components as those in FIG. 16 are denoted by the same reference numerals. This processor is different from the one shown in FIG.
It differs in that it has only one 0. For this reason,
Compared with FIG. 16, it is needless to say that only one IB buffer is required, and the selectors 41 and 42 for accumulating the three buffers from the left are unnecessary, and the circuit can be simplified. The operation is the same except that the storage destination is fixed to the IB buffer 50.
The description is omitted because it is the same as the third embodiment.

3. Recording Medium As an embodiment of the recording medium of the present invention, a magnetic disk (floppy disk, hard disk, etc.) and an optical disk (CD-ROM, PD
), A magneto-optical disk, and a semiconductor memory (such as a ROM or a flash memory).

As described above, according to the present embodiment, the machine instruction compression unit 109 of the compiler determines whether or not one of the first and second slots except for the third slot.
Extract two nop codes, and slot this nop code,
The third slot that appears first after the nop code is replaced with the operation of the instruction whose valid operation is specified, and the third slot of the instruction whose valid operation is used for replacement is deleted. The area is reduced, and the program size can be reduced. In particular, according to the present embodiment, the conventional three-parallel execution with an instruction consisting of three slots
Since the instruction can be executed with an instruction consisting of two slots by using a slot serving as a nop code, the code efficiency is extremely high.
In the operation example described above, 3 slots × 5 instructions = 15 slots in FIG. 12 are replaced with 2 slots × 5 instructions = 10 slots in FIG.
It can be seen that it is compressed in the slot.

Further, according to the processor of the present embodiment,
By providing an IB buffer for storing an effective operation embedded in the position of the conventional nop code, specifying the IB buffer with a storage bit in an instruction, and executing the operation of the instruction and the stored operation in parallel,
It is possible to execute a compressed machine instruction program while maintaining the conventional processing performance.

In the processor of this embodiment, IB
Although one accumulation buffer called a buffer is provided, a plurality of storage buffers may be provided. Nop as the number of accumulation buffers increases
The opportunity to fill the code with valid operations increases, and the program size can be further reduced. For example, instruction 3
The nop code of the second slot of instruction 4 and the first slot of instruction 4 remains without being replaced, but one instruction having a valid operation placed in the third slot immediately after instruction 5 of the uncompressed (FIG. 14) If so, or two, respectively, one or both of these nop codes can be filled with the valid operation.

Furthermore, in the processor of the present embodiment, three instruction decoders and three arithmetic units are provided to achieve a maximum of three parallel executions. Or more. In the case of four-parallel execution, the effective operation may be filled by using two slots that become nop codes when the two-slot instruction is not compressed, as in the present embodiment. The valid operation may be filled by using one slot that becomes a nop code when not compressed. However, in the former case, it is necessary to provide an additional IB buffer for another slot. The former is effective when the number of slots that become nop codes when uncompressed is extremely large compared to the latter, and a considerable improvement in code efficiency can be expected. By doing so, even if the parallelism of instructions in the VLIW processor is improved, the increase in nop code can be greatly reduced.

As described above, the compiler and the processor according to the present invention have been described based on the above four embodiments, but it is needless to say that the present invention is not limited to these embodiments. That is, (1) In the above four embodiments, the architecture of the VLIW format in which two or three operations are specified for one instruction is used, but an architecture other than the VLIW format in which one operation specifies one operation may be used. .

In particular, in the case of fixed-length instructions, many instructions having unused areas may be defined. For example, MIPS R
The processor "R3000" based on the ISC architecture executes a 32-bit fixed-length instruction. The operation instruction of this processor has a 12-bit operation field (indicated by "op1" and "op2") as shown in FIG. And three register fields of 5 bits each (designated by “rs” and “rt” of the source operand and “rd” of the destination operand), and an unused area indicated by “res” of 5 bits. Have. According to the present invention, the occurrence of a waste area generated during such a single operation instruction is also avoided. Specifically, as shown in FIG. 23B, the compiler divides one instruction to be executed after the instruction F by using the unused areas a to f of the six instructions A to the instruction F. The instructions are deleted and the instructions are deleted. These instructions are sequentially stored in an instruction storage register provided in the processor, and the contents of this register are executed after the execution of the instruction F. By doing so, a waste area in the program is eliminated, and the code efficiency is improved. The contents of the instruction storage register may be executed not just after the instruction F but after execution of another instruction following the instruction F, or may be executed in parallel with the instruction F. In particular, the latter concept is useful because it is possible to realize a VLIW format architecture that specifies two operations, though local, in an architecture that is not a VLIW format that specifies one operation with one instruction. By providing a plurality of such instruction accumulation registers, a VLIW architecture with three or more parallels can be realized. Note that the six instructions A to F need not necessarily be continuous without any gaps.

(2) In the above four embodiments, the instruction storage register (corresponding to IB1, IB2, and IB buffers) is read and the contents are erased at the same time. It may be reused. For example, the third and fourth embodiments do not use the state in which the 2-bit accumulated bit is 11, and use this state. When the accumulated bit is 11, the IB buffer is executed without erasing. It can be. By doing so, for example, when a program repeatedly executes the same instruction such as forming a loop, the same instruction is frequently executed many times.
There is no need to store data in the B buffer, and the code efficiency is further improved. It is also possible to provide two types of instruction accumulation registers, those whose contents are erased immediately after reading and those which can be reused without being erased.

(3) In the above four embodiments, in the compiler, the machine instruction generation unit 107 once generates the same machine instruction program as the conventional one, and then executes the machine instruction compression unit 1
09 compresses this, but the functions of both may be integrated to directly generate a target compressed machine instruction program without generating the same machine instruction program as in the related art.

(4) Although the processors of the above four embodiments are configured by a three-stage pipeline of instruction fetch, decoding, and execution, the number of stages of the pipeline may be any, It is not necessary to take a line.

[0128]

As is apparent from the above description, according to the present invention, nop can be reduced and the code size can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a compiler according to a first embodiment.

FIG. 2 is a flowchart showing a processing flow of a machine instruction compression unit 109 of the compiler according to the first embodiment;

FIG. 3 is a flowchart showing a processing flow of a machine instruction compression unit 109 of the compiler according to the first embodiment;

FIG. 4 is a flowchart showing a processing flow of a machine instruction compression unit 109 of the compiler according to the first embodiment;

FIG. 5 is an exemplary diagram of an uncompressed machine instruction program.

FIG. 6 is an exemplary diagram of a compressed machine instruction program according to the first embodiment;

FIG. 7 is a schematic configuration diagram of a processor according to the first embodiment;

FIG. 8 is an operation timing chart corresponding to the machine instruction program of FIG. 6 of the processor according to the first embodiment;

FIG. 9 is a view showing an example of a compressed machine instruction program according to the second embodiment;

FIG. 10 is a flowchart showing a processing flow of a machine instruction compression unit 109 of the compiler according to the second embodiment.

FIG. 11 is a flowchart showing a processing flow of a machine instruction compression unit 109 of a compiler according to the second embodiment.

FIG. 12 is a flowchart showing a processing flow of a machine instruction compression unit 109 of a compiler according to the second embodiment.

FIG. 13 is a schematic configuration diagram of an IF stage portion of the processor according to the second embodiment;

FIG. 14 is an exemplary diagram of an uncompressed machine instruction program.

FIG. 15 is an exemplary diagram of a compressed machine instruction program according to the third embodiment.

FIG. 16 is a schematic configuration diagram of a processor according to a third embodiment.

FIG. 17 is an operation timing chart corresponding to the machine instruction program of FIG. 13 of the processor according to the third embodiment;

FIG. 18 is an exemplary diagram of a compressed machine instruction program according to the fourth embodiment.

FIG. 19 is a schematic configuration diagram of an IF stage portion of the processor according to the embodiment;

FIG. 20 is an operation timing chart corresponding to the machine instruction program of FIG. 16 of the processor according to the fourth embodiment;

FIG. 21 is a schematic configuration diagram of a processor in the first related art.

FIG. 22 is a schematic configuration diagram of a processor according to a second conventional technique.

FIG. 23 is a format diagram of an instruction according to another related art and another embodiment.

[Explanation of symbols]

 1, 41 ROM 2, 42 I1 latch 3, 43 I2 latch 4, 45 First instruction decoder 5, 46 Second instruction decoder 6, 48 Register file 7, 49 D1 selector 8, 50 D2 selector 9, 52 D11 latch 10, 53 D12 latch 11, 55 D21 latch 12, 56 D22 latch 13, 58 First operation unit 14, 59 Second operation unit 15, 33 IB11 buffer 16, 34 IB12 buffer 17, 35 IB21 buffer 18, 36 IB22 buffer 19 , 64 I1 selector 20, 65 I2 selector 21, 37, 67, 72 Control circuit 31 IB1 selector 32 IB2 selector 44 I3 latch 47 Third instruction decoder 51 D3 selector 54 D13 latch 57 D23 latch 60 Third arithmetic unit 61 IB1 buffer 62 IB2 buffer 3 IB3 buffer 66 IB selector 71 IB buffer 101 C language program 102 Compiler 103 File reading unit 104 Reading buffer 105 Syntax analysis unit 106 Intermediate code buffer 107 Machine instruction generation unit 108 Temporary output buffer 109 Machine instruction compression unit 110 Output Buffer 111 File output unit 112 Machine instruction program

Claims (11)

[Claims] 1. A compiler for generating, from a high-level language program, a machine instruction program in a long-word instruction format having a plurality of slots in which a plurality of operation descriptions are arranged, a plurality of processors capable of simultaneously executing the processor in parallel from the high-level language program. After generating the operation in the long instruction format, the nop included in the instruction is replaced with a valid operation executed after the nop, and the valid operation is deleted. A compiler characterized by being added. 2. A compiler for generating, from a high-level language program, a machine instruction program in a long-word instruction format including a plurality of slots in which a plurality of operation descriptions are arranged, a plurality of processors capable of simultaneously executing the processor from the high-level language program in parallel. After generating an instruction in a long-word instruction format in which an operation is arranged in each slot, the nop included in the instruction is replaced with a valid operation executed later in the same slot as the nop, and information indicating the replacement. Compiler characterized by adding. 3. A compiler for generating, from a high-level language program, a machine instruction program in a long-word instruction format including a plurality of slots in which a plurality of operation descriptions are arranged, wherein the high-level language program allows the processors to execute simultaneously in parallel. After generating an instruction in the long-word instruction format in which the operation is arranged in each slot, the nop included in the instruction is replaced with a valid operation executed later regardless of whether or not the operation is in the same slot as the nop. And information indicating the replaced slot and the information of the replaced slot having a valid operation. 4. A compiler for generating, from a high-level language program, a machine instruction program in a long-word instruction format including a plurality of slots in which a plurality of operation descriptions are arranged, wherein the number of processors from the high-level language program is greater than the number of the slots. Generates an instruction in a long-word instruction format in which a plurality of operations that can be executed in parallel at the same time are arranged in each slot, and then replaces nops of slots exceeding the plurality of operations that can be executed in parallel by the processor with valid operations that are executed later. A compiler that adds information indicating that the slot has been replaced and information of the slot in which the replaced valid operation has been performed. 5. A compiler for generating, from a high-level language program, a machine instruction program in a long-word instruction format including a plurality of slots in which a plurality of operation descriptions are arranged, wherein the number of the processors from the high-level language program is larger than the number of the slots. After generating an instruction in a long-word instruction format in which a plurality of operations that can be executed in parallel at the same time are arranged in each slot, the nop is replaced with a valid operation to be executed later in the order of appearance, and information indicating the replacement is replaced with the replaced information. Compiler characterized by adding information of a slot where a valid operation has been performed. 6. A processor for executing instructions in a plurality of slots in parallel at the same time, wherein the instructions are temporarily stored in a storage buffer based on a value of a storage bit in the instruction, and then the instructions stored in the storage buffer are executed. A processor, characterized in that: 7. A processor for simultaneously executing instructions in a plurality of slots in parallel, comprising a storage buffer for storing the instructions, wherein the instructions have storage bits for controlling whether the instructions are to be executed immediately or temporarily stored. A processor that temporarily stores the instruction in a storage buffer based on a value of a storage bit in the instruction, and then executes the instruction stored in the storage buffer. 8. A processor for simultaneously executing instructions of a plurality of slots in parallel, comprising: a storage buffer for storing the instructions, wherein the instructions include a storage bit for controlling whether to execute the instructions immediately or to temporarily store the instructions. A position bit for controlling whether to store the instruction in the storage buffer, and temporarily storing the instruction in the storage buffer based on the value of the storage bit and the position bit in the instruction, and then executing the instruction stored in the storage buffer A processor comprising: 9. A processor for simultaneously executing instructions of a plurality of slots in parallel, comprising a storage buffer having a number of storage buffers larger than the number of slots for storing the instructions, wherein the instructions determine whether the instructions are to be executed immediately or stored once. A processor having an accumulation bit to be controlled, wherein the instruction is temporarily stored in an accumulation buffer based on a value of the accumulation bit in the instruction, and then the instruction accumulated in the accumulation buffer is executed. 10. A recording medium recording machine instructions to be executed by a processor, wherein the machine instructions include a plurality of operation descriptions and an accumulation bit for controlling whether to execute or accumulate the instructions immediately. A recording medium on which a characteristic machine instruction is recorded. 11. A recording medium storing machine instructions to be executed by a processor, wherein the machine instructions store a plurality of operation descriptions, an accumulation bit for controlling whether to execute or accumulate the instructions immediately, and where to store the instructions. And a position bit indicating whether the machine instruction has been recorded.