JP2000224848A - Asymmetric flyback circuit using synchronous rectifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an asymmetric flyback circuit which prevents double delays, by using the output of a pulse-width modulation(PWM) part, when a synchronous rectifier is turned off. SOLUTION: The gate drive signal of a switch is generated by a pulse width modulation controller(PWM) 70A. At the same time, a reference voltage is generated. In a signal delay part 91, the gate drive signal, of the switch which is output by the PWM controller 70A is delayed. Then, in an inversion and compensation part 92, a gate drive signal which is output by the signal delay part 91 is compared with the reference voltage output by the PWM controller 70A. Its resulting value is amplified. When a synchronous rectifier SR is turned off, a compensated gate drive signal is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asymmetric flyback circuit applied to an AC adapter, and more particularly to an asymmetric flyback circuit before turning on a synchronous rectifier by using an output of a pulse width modulation unit. MOS that is a switch
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asymmetric flyback circuit using a synchronous rectifier for minimizing a loss generated when a parasitic diode of a transistor (MOSFET) is turned on and preventing a double delay when the synchronous rectifier is turned off.

[0002]

2. Description of the Related Art In recent years, notebook PCs have been reduced in size and weight all over the world, and in pursuit of higher performance, a multimedia system has been inevitably constructed, and a high-speed CPU has been inevitable. There is a continuous demand for an increase in system specifications, for example, increase in memory and memory.

[0003] In addition, AC adapters for notebook PCs currently use 45 to 50 Watts of power due to the increase in capacity for each resource of each system specification, but gradually use 60 to 75 Watts. Demands for higher capacity of 80 watts or more, ultra-compact and slimness that is easy to carry, and high efficiency are increasing.

Further, the reason why the efficiency of the AC adapter must be increased is that the higher efficiency means that the internal power loss is small, which means that the internal heat generation is small. , Miniaturization becomes possible.

[0005] However, at present, there are a flyback circuit system and a resonance type system as the most typical systems used for AC adapters. Among them, the flyback circuit system is the turn-off voltage (Vds) of a MOS transistor which is a semiconductor device. There is a disadvantage that power loss is large due to hard switching in which the intersection of the turn-on current (Ids) and the turn-on current (Ids) is large. On the other hand, the resonance type method can suppress switching loss and is an effective method for reducing the size and weight, but since the voltage and current are formed in a sine wave shape, the controllability is poor, and the voltage applied to the switching element is low. However, it has the disadvantage that the current stress is large.

Accordingly, recently, from the viewpoint of high efficiency, a synchronous rectifier (Synchronous Rectifier) is used.
er: SR) has attracted attention. Synchronous rectifier, using MOS transistors instead of the output diode during conduction of the synchronous rectifiers, but R _{ds (on)} Loss ^{_{(I F 2 * R ds (}} on)) is generated, R _{ds (on),} the 0.
Since it is very small at about 020 to 0.025Ω and the loss is small, it has a great effect on increasing the efficiency.

[0007]

FIG. 1 shows the configuration of a conventional AC adapter to which the above-described synchronous rectification system is applied.

According to the configuration shown in FIG. 1, after removing noise mixed with the input commercial AC power, the noise is transmitted to a device provided at the rear end and generated on the device side at the rear end. An EMI filter 10 for preventing power supply noise from being transmitted to the input terminal side of the commercial AC power supply, a bridge rectifying unit 20 for rectifying AC power input through the EMI filter 10 and converting the AC power to DC power, A voltage doubler 30 that constantly maintains the DC power rectified through the bridge rectifier 20 in a state of DC power in an AC input state of 220 V, and flows in through the voltage doubler 30 according to an input switching control signal. An asymmetric flyback converter 40 for performing a zero voltage switching operation for a power supply, A synchronous rectification unit 50 for rectifying a power supply induced via the transformer T1 with a specific synchronization signal with respect to a variation in the voltage at which the voltage is switched, and a voltage finally output via the synchronous rectification unit 50 A feedback unit 100 that senses a state of the voltage and transmits information about a voltage state to a front end;
And a protection circuit 110 for preventing damage to a device located at a rear end of the synchronous rectification unit 50, and modulates a PWM signal for a control signal according to a state of an output voltage of the synchronous rectification unit 50 transmitted through the feedback unit 100. PWM controller 70 and the PWM controller 7
A switch gate driver 80 for generating a drive signal for controlling the zero voltage switching operation of the asymmetric flyback converter 40 according to the control signal output at 0; It comprises an SR gate driver 90 for controlling the synchronous state of the synchronous rectifier 50 with a drive signal L for driving a low side switch inside the flyback converter 40.

In the configuration of the conventional AC adapter to which the synchronous rectification system configured as described above is applied, the configuration related to the synchronous rectification system is shown in FIG. 2 as shown in FIG. A simplified circuit configuration of the asymmetric flyback converter 40, the synchronous rectifier 50, and the SR gate driver 90, and the PWM controller 70 and the switch gate driver 80 are illustrated.

Referring to the configuration shown in FIG. 2, a PWM controller 70 for generating a pulse width modulation signal, and the gates of the high side and low side switches are driven by the pulse width modulation signal output from the PWM controller 70. A switch gate driver 80, a high-side switch SWH and a low-side switch SWL that perform a switching operation in accordance with an output signal of the switch gate driver 80, and a primary-side voltage is changed to a secondary voltage by the switching operation of the high-side switch SWH and the low-side switch SWL. A synchronous rectifier SR for rectifying the secondary output voltage of the transformer T1, and a gate drive signal of the low side switch output from the switch gate driver 80 to drive the gate of the synchronous rectifier SR. And an insulating transformer T2 Metropolitan to.

The conventional asymmetric flyback circuit using the synchronous rectifier constructed as described above uses the pulse width modulation signal output from the PWM controller 70 to generate a high-level signal inside the asymmetric flyback converter 40 using the switch gate driver 80. The gates of the side switch SWH and the low side switch SWL are driven.

The transformer T1 induces the primary side voltage to the secondary side by the switching operation of the high side switch SWH and the low side switch SWL, and the synchronous rectifier SR connects the secondary side of the transformer T1. Output voltage is rectified and output. The insulating transformer T2 is connected to the switch gate driver 80.
The gate of the synchronous rectifier SR is driven by using the gate drive signal of the low side switch output at step (1).

That is, the gate drive signal of the synchronous rectifier SR is supplied while being delayed between the turn-off of the high-side switch SWH and the turn-on of the synchronous rectifier SR, and between the turn-off of the synchronous rectifier SR and the turn-on of the high-side switch SWH. You.

Further, after the low side switch SWL is turned off and before the high side switch SWH is turned on, the energy transmitted to the secondary side is consumed, and a negative primary side current flows. The synchronous rectifier SR must be turned off within the turn-off of the low-side switch SWL.

Therefore, conventionally, in order to make the gate signal of the synchronous rectifier SR the same as that of the low-side switch SWL, a gate drive signal of the low-side switch SWL is applied to the gate of the synchronous rectifier SR via the insulating transformer T2.

The waveform a shown in FIG. 3 is the waveform of the gate voltage of the high side switch, the waveform b is the waveform of the gate voltage of the low side switch, and the waveform c
Is a waveform of the gate voltage of the synchronous rectifier.

Referring to the operation of the circuit shown in FIG. 2 with reference to the voltage waveform shown in FIG. 3, the high-side switch SWH is turned on in the section of the waveform a in FIG. Energy is stored in the transformer T1.

Thereafter, when the voltage state of the waveform a is changed to a low state, the high-side switch SWH is turned off, whereby the polarity of the transformer T1 is changed and a voltage is induced on the secondary side. Then, the current isec flows.

At this time, since the current isec flows, the synchronous rectifier SR is turned on through the SR gate driver 90 using the voltage of the turn-on operation of the low side switch SWL, that is, the voltage of the waveform b.

Therefore, while the low-side switch SWL is turned on, the current isec continuously flows,
When the low side switch SWL is turned off,
The current isec stops flowing.

However, actually, the high-side switch S
WH turn-off time and the low-side switch SWL
And the current isec on the secondary side of the transformer T1 flows from the turn-off time of the high-side switch SWH, so that the synchronous rectifier SR is not turned on until the synchronous rectifier SR is turned on. The current flows through a parasitic diode inside the rectifier SR (see waveform c in FIG. 3).

[0022] Thus, while the current flows isec through the synchronous rectifier SR internal parasitic diode, the power losses D _SR due to a voltage drop across the parasitic diode is generated.

Further, the synchronous rectifier SR is provided with a switch gate driver 8 based on an output signal of the PWM controller 70.
Since the operation is performed by the signal 0 and the signal passed through the SR gate driver 90, a double time delay occurs. Due to such a delay time, the low-side switch SWL is turned off at a time later than the turn-off time, so that a problem of malfunction occurs (see a waveform d in FIG. 3).

Further, the current ipri on the primary side of the transformer T1 flows through the parasitic diode of the high-side switch SWH at the same time as the low-side switch SWL is turned off. It must be the same as when the low-side switch SWL is turned off. However, the conventional technique shown in FIG. 2 has a problem that such a requirement cannot be satisfied.

The present invention has been made to solve the above problems, and has as its object to prevent a double delay when a synchronous rectifier is turned off by using an output of a pulse width modulator. It is an object of the present invention to provide an asymmetric flyback circuit using a synchronous rectifier.

[0026]

To achieve the above object, according to the present invention, there is provided a pulse width modulation section for generating a gate drive signal for driving a gate of a switch and a reference voltage; A switch gate drive unit for driving a high-side switch and a low-side switch by a gate drive signal output by the unit; a transformer for inducing a primary-side voltage to a secondary side by a switching operation of the high-side and low-side switches; A synchronous rectifier for rectifying the output voltage on the secondary side of the transformer, and a gate drive signal output from the pulse width modulator is delayed, and then compared with a reference voltage output from the pulse width modulator. A rectification drive signal generator for amplifying a result value and providing the result as a drive signal for the synchronous rectifier; and a drive signal output from the rectification drive signal generator. MOS There are provided in the synchronous rectification portion is inputted through an insulation transformer
The gist of the present invention is to include a synchronous rectification drive unit for driving a synchronous rectifier composed of a transistor.

According to a second aspect of the present invention, in the asymmetric flyback circuit using the synchronous rectifier of the first aspect, the rectification drive signal generator delays a gate drive signal output from the pulse width modulator. Means for comparing the gate drive signal output from the signal delay means with the reference voltage output from the pulse width modulator, amplifying the result, and compensating the gate drive signal when the synchronous rectifier is turned off. The gist of the invention is to include inversion and compensation means for generating

According to a third aspect of the present invention, in the asymmetrical flyback circuit using the synchronous rectifier of the second aspect, the signal delay means includes an RC and a capacitor for delaying the switch gate drive signal by a correction number. The point is to use a filter.

According to a fourth aspect of the present invention, in the asymmetric flyback circuit using the synchronous rectifier according to the second aspect, the inverting and compensating means includes a reference voltage output from the pulse width modulator and the signal delaying means. And a buffer amplifier that amplifies the output signal of the comparator and generates a gate drive signal of a synchronous rectifier whose delay is compensated for.

According to a fifth aspect of the present invention, in the asymmetric flyback circuit using the synchronous rectifier of the fourth aspect, the buffer amplifier is configured such that a predetermined positive voltage is input to a collector terminal via a first resistor, and Is input to a base terminal via a second resistor, and a first transistor which is turned on / off by an output signal of the comparator applied to the base terminal, and a voltage applied to an emitter terminal of the first transistor is applied to an emitter terminal And a second transistor that receives the output signal of the comparator and that operates in reaction with the first transistor at a base terminal.

According to a sixth aspect of the present invention, in the asymmetric flyback circuit using the synchronous rectifier of the first aspect, the synchronous rectifier is connected in parallel between a voltage output terminal on the secondary side of the transformer and a ground terminal. The gist of the present invention includes a first capacitor and a synchronous rectifier which is a MOS transistor element having a drain terminal connected to one end on the secondary side of the transformer and a source terminal connected to a ground terminal.

According to a seventh aspect of the present invention, in the asymmetric flyback circuit using the synchronous rectifier of the first aspect, the synchronous rectification drive section includes a third resistor connected between a gate terminal of the synchronous rectifier and a ground terminal. A first diode having a cathode terminal connected to the gate terminal of the synchronous rectifier and an anode terminal connected to the ground terminal; and a second diode output terminal of the insulating transformer and a gate terminal of the synchronous rectifier. The gist of the present invention includes a fourth resistor connected thereto and a second capacitor connected between the other end on the secondary side of the insulating transformer and an anode terminal of the first diode.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to describing the present invention, the technical concept of the present invention will be briefly described. The problem with the prior art is that the current isec on the secondary side of the transformer T1 is not sufficient.
The problem is that power loss occurs when the synchronous rectifier SR flows through a parasitic diode inside the synchronous rectifier SR, and the on / off operation time of the synchronous rectifier SR depends on the delay time depending on the section of the normal operation condition and the other section. The problem is that it works with. Therefore, the delay time is reduced, the flow of the secondary side current isec in the transformer T1 via the parasitic diode is suppressed, and the secondary side current isec is reduced.
It is a technical problem to prevent the delay by turning off the gate voltage of the synchronous rectifier SR when c is off, that is, simultaneously with turning off the low-side switch SWL.

Therefore, the asymmetric flyback converter 4
When the synchronous rectifier SR is turned on at the time of turning off the high-side switch SWH inside the synchronous rectifier SR, the output of the transformer T1 via the parasitic diode of the synchronous rectifier SR becomes 2
The fact that the flow of the current isec on the secondary side can be suppressed and the input signal of the switch gate driver, that is,
It is noted that using the output signal of the PWM controller allows the gate voltage of the synchronous rectifier to prevent turn-off delay.

Therefore, the gist of the present invention is to deviate from the prior art in which the output signal of the switch gate driver is used for the drive signal of the synchronous rectifier SR, and to directly use the signal output by the PWM controller for the drive signal of the synchronous rectifier SR. It is to do.

Hereinafter, the present invention will be described in detail.

FIG. 4 is a block diagram showing an example of a block configuration of an AC adapter to which the synchronous rectification system according to the present invention is applied. Referring to the configuration shown in FIG. 4, noise mixed in the input commercial AC power is removed. After that, the EMI filter 10 transmits to the device side provided at the rear end, and conversely, prevents the power noise generated at the rear end device side from being transmitted to the input end side of the commercial AC power supply. A bridge rectifier 20 for rectifying the AC power input through the filter 10 to convert it to a DC power; and a state of the DC power in a state where the DC power rectified through the bridge rectifier 20 is always 220 V AC input. Voltage doubler 30 to maintain
An asymmetric flyback converter 40 that performs a zero voltage switching operation on a power supply that flows in through the voltage doubler 30 according to an input switching control signal; A synchronous rectification unit 50 for rectifying a power supply induced via the transformer T1 with respect to the variation by a specific synchronization signal;
A feedback unit 1 that senses the state of the voltage finally output through the FB and transmits information on the voltage state to the front end.
00, a protection circuit 110 for preventing damage to a device located at the rear end of the feedback unit 100 and the synchronous rectification unit 50, and a state of an output voltage of the synchronous rectification unit 50 transmitted through the feedback unit 100. A PWM controller 70 for modulating a PWM signal for a control signal; and a control signal output from the PWM controller 70, the asymmetric flyback converter 40
A gate driver 80 for generating a drive signal for controlling a zero voltage switching operation of the PW
It comprises an SR gate driver 90 for receiving a control signal output from the M controller 70 and a reference voltage signal and controlling the synchronous state of the synchronous rectifier 50.

As a block diagram, it seems that the configuration of FIG. 4 does not have any special difference from the configuration of the prior art shown in FIG. The difference between the prior art and the present invention will be clarified by the detailed circuit configuration described below.

FIG. 5 is a block diagram of an asymmetric flyback circuit using a synchronous rectifier according to the present invention.

As shown, a PWM controller 70A for generating a gate drive signal for driving the gate of the switch and a reference voltage Vref, and a high side switch SWH and a low side switch according to the gate drive signal output from the PWM controller 70A. A switch gate driving unit 80 for driving the SWL; a transformer T1 for inducing a primary-side voltage to a secondary side by switching operations of the high-side and low-side switches SWH and SWL; and a secondary-side output voltage of the transformer T1. Rectifier 50A for rectifying the power supply, and the PWM controller 70
After delaying the gate drive signal output at A,
Reference voltage Vref output from WM controller 70A
The synchronous rectification unit 50A
And an SR gate driver 90A that provides the drive signal for the drive signal.

At this time, the SR gate driver 90A
Is a signal delay unit 91 for delaying a signal output from the PWM controller 70A, a gate drive signal output from the signal delay unit 91 and the PWM controller 70A.
A reference voltage Vref output at A is compared, the result is amplified, and when the synchronous rectifier SR is turned off, the inversion and compensation unit 92 generates a compensated gate drive signal. The signal delay unit 91 includes a resistor R1 and a capacitor C3 for delaying the switch gate drive signal by a correction number.
It is composed of

The inverting and compensating unit 92 is provided with the P
Reference voltage Vref output from WM controller 70A
And a buffer amplifier 93 that amplifies the output signal of the comparator OP to generate a gate drive signal for the synchronous rectifier.
It is composed of

In the buffer amplifier 93, a predetermined positive voltage Vcc is input to a collector terminal via a fifth resistor R5, and the positive voltage Vcc is input to a base terminal via a fourth resistor R4. A first transistor Q1 that is turned on / off by an output signal of the comparator OP applied to the base terminal, and a voltage applied to an emitter terminal of the first transistor Q1 is input to an emitter terminal;
The output terminal of the comparator OP is input to a base terminal, and the base terminal includes the first transistor Q1 and a second transistor Q2 which operates in reaction.

An isolation transformer T2 is provided to provide the primary-side signal output from the inverting and compensating section 92 to the gate drive signal of the synchronous rectifier provided on the secondary side.

The synchronous rectifier 50A includes a second capacitor C2 connected in parallel between a voltage output terminal on the secondary side of the transformer T1 and a ground terminal, and a drain connected to one end of the secondary side of the transformer T1. And a synchronous rectifier SR which is a MOS transistor element having a terminal connected to the ground terminal and a source terminal connected thereto.

The synchronous rectifier driver 94 for driving the synchronous rectifier SR includes a third resistor R3 connected between a gate terminal of the synchronous rectifier SR and a ground terminal, and a gate of the synchronous rectifier SR. A first diode D1 having a cathode terminal connected to the terminal and an anode terminal connected to the ground terminal; and a second resistor R2 connected between a voltage output terminal on the secondary side of the insulating transformer T2 and the gate terminal of the synchronous rectifier SR. And a fifth capacitor C5 connected between the other end of the secondary side of the insulating transformer T2 and the anode terminal of the first diode D1.

The asymmetric flyback circuit according to the present invention thus constructed generates a gate drive signal for driving the switch gate by the PWM controller 70A and the reference voltage Vref, and the switch gate driver 80 The gates of the high-side switch SWH and the low-side switch SWL are driven by the gate drive signal.

The transformer T1 induces the primary side voltage to the secondary side by the switching operation of the high-side switch SWH and the low-side switch SWL, and the synchronous rectifier SR connects the secondary side of the transformer T1.
The output voltage on the secondary side is rectified and output.

On the other hand, when the synchronous rectifier SR is turned off, in order to prevent a delay, the output signal of the PWM controller 70A is directly used without using the gate drive signal of the existing low-side switch, and the inverted signal is input to the inverting input of the comparator OP. used.

At this time, the reason that the signal delay unit 91 is provided is that the synchronous rectifier SR is turned on while the high-side switch SWH is turned on, and the current isec on the secondary side of the transformer T1 is turned on. This is to prevent reverse flow.

The comparator O in the inverting and compensating unit 92
P receives the signal obtained by the signal delay unit 91 at the input terminal of the inverted data, and inputs the signal to the PWM controller 70A.
After receiving the reference voltage Vref output at the input terminal of the non-inverted data and comparing the magnitudes, a voltage signal associated with the comparison value is output as a high or low state voltage signal.

The output of the comparator OP is amplified by a buffer amplifier 93, and is output as a gate drive signal for compensating a delay when the synchronous rectifier SR is turned off. Maintain a state where the phase of the signal output from the comparator OP is inverted.

Further, the insulating transformer T2 is
After the voltage is divided by resistors R1 and R3 as an inverted and compensated gate drive signal output by the buffer amplifier 93, the gate of the synchronous rectifier SR is It is driven and compensates for delay at turn-off.

FIG. 6 shows waveforms of the gate voltage of the synchronous rectifier and the gate voltage of the low-side switch.
As shown in the figure, it can be seen that the synchronous rectifier SR is turned off at the same time when the low-side switch SWL is turned off, so that no delay occurs.

FIG. 7 shows waveforms of the gate voltage of the synchronous rectifier and the secondary current of the transformer. After the gate voltage of the high-side switch is turned off, the secondary current i
After a minimum RC delay time after conduction of sec, the gate voltage of the synchronous rectifier is turned on, so that the loss through the parasitic diode is minimized. When the secondary current is turned off, the synchronous rectifier is turned off and the parasitic diode is turned off. And there is no double delay phenomenon and no malfunction occurs.

FIG. 8 shows the synchronous rectifier gate voltage and the high-side current waveform, and shows that the gate voltage of the synchronous rectifier is turned off without delay before the primary high-side current flows negatively. ing.

[0057]

As described above in detail, according to the present invention, the output of the pulse width modulation section is used, and the gate drive signal of the switch output from the pulse width modulation section is inverted using a comparator. By driving the gate of the synchronous rectifier, the turn-on delay of the gate voltage in the synchronous rectifier can be prevented, the loss through the parasitic diode can be minimized, and the delay that occurs when the synchronous rectifier is turned off can be eliminated. This has the effect.

[Brief description of the drawings]

FIG. 1 is an exemplary block diagram of an AC adapter to which a synchronous rectification method is applied.

FIG. 2 is a simplified circuit diagram of a portion related to a conventional synchronous rectification method.

FIG. 3 is a waveform chart for explaining a problem of the circuit diagram shown in FIG. 2;

FIG. 4 is an exemplary block diagram of an AC adapter to which a synchronous rectification method according to the present invention is applied.

FIG. 5 is an asymmetric flyback circuit diagram using a synchronous rectifier according to the present invention.

FIG. 6 is a waveform diagram showing a gate voltage of a switch L and a gate voltage of a synchronous rectifier according to the present invention.

FIG. 7 is a waveform diagram showing the gate voltage of the synchronous rectifier and the current on the secondary side of the transformer according to the present invention.

FIG. 8 is a waveform diagram showing a gate voltage of a synchronous rectifier and a secondary high side current in the present invention.

[Explanation of symbols]

10 EMI filter, 20 bridge rectifier, 30
Voltage doubler, 40 ... Asymmetric flyback converter, 5
0A: Synchronous rectifier, 70A: PWM controller, 80
... switch gate driver, 90A ... SR gate driver, 91 ... signal delay unit, 92 ... inversion and compensation unit, 93 ...
Buffer amplifier, 100 feedback section, 110
... Protection circuit.

Claims (7)

[Claims] A pulse width modulator for generating a gate drive signal for driving a gate of a switch and a reference voltage, and a high side switch and a low side switch are driven by the gate drive signal output from the pulse width modulator. A switch gate driving unit; a transformer for inducing a primary-side voltage to a secondary side by a switching operation of the high-side and low-side switches; a synchronous rectification unit for rectifying a secondary-side output voltage of the transformer; After delaying the gate drive signal output from the width modulation unit, the gate drive signal is compared with the reference voltage output from the pulse width modulation unit, and the result value is amplified to provide a drive signal for the synchronous rectification unit to provide a drive signal. A signal generation unit; and a drive signal output from the rectification drive signal generation unit is input via an insulation transformer to perform the synchronous rectification. Asymmetric flyback circuit using a synchronous rectifier, characterized in that it comprises a synchronous rectifier drive unit for driving the synchronous rectifiers consisting of MOS transistors are provided within. 2. The rectification drive signal generator includes: a signal delay unit that delays a gate drive signal output by the pulse width modulator; a gate drive signal output by the signal delay unit; and the pulse width modulator. 2. The inverter according to claim 1, further comprising: an inverting and compensating unit that compares the reference voltage output from the synchronous rectifier and amplifies the result to generate a compensated gate driving signal when the synchronous rectifier is turned off. Asymmetric flyback circuit using synchronous rectifiers. 3. The synchronous rectifier according to claim 2, wherein the signal delay means uses an RC filter including a resistor and a capacitor for delaying the switch gate drive signal by a correction number. Asymmetric flyback circuit. 4. The inverting and compensating means includes: a comparator for comparing a reference voltage output from the pulse width modulator with a signal output from the signal delay means; and amplifying an output signal of the comparator. 3. The asymmetric flyback circuit using a synchronous rectifier according to claim 2, further comprising: a buffer amplifier that generates a gate drive signal of the synchronous rectifier whose delay is compensated. 5. The buffer amplifier, wherein a predetermined positive voltage is input to a collector terminal via a first resistor, and the positive voltage is input to a base terminal via a second resistor. A first transistor that is turned on / off by an output signal of the comparator; a voltage applied to an emitter terminal of the first transistor is input to an emitter terminal; an output signal of the comparator is input to a base terminal; The asymmetric flyback circuit using a synchronous rectifier according to claim 4, further comprising one transistor and a second transistor that operates in reaction. 6. The synchronous rectifier, wherein: a first capacitor connected in parallel between a voltage output terminal on the secondary side of the transformer and a ground terminal; and a drain terminal connected to one end of the secondary side of the transformer. 2. The asymmetric flyback circuit using a synchronous rectifier according to claim 1, further comprising: a synchronous rectifier that is a MOS transistor device having a source terminal connected to a ground terminal. 7. The synchronous rectifier driver includes a third resistor connected between a gate terminal of the synchronous rectifier and a ground terminal, a cathode terminal connected to the gate terminal of the synchronous rectifier, and an anode terminal connected to the ground terminal. A fourth diode connected between a voltage output terminal on the secondary side of the insulating transformer and a gate terminal of the synchronous rectifier; a second end connected on the secondary side of the insulating transformer; The asymmetric flyback circuit using a synchronous rectifier according to claim 1, further comprising a second capacitor connected between the anode terminal of the first diode and the anode terminal of the first diode.