CN1938931A - Soft switching power converter with power saving components - Google Patents

Abstract

The present invention relates to a pulse width modulated soft switching power converter having a pair of main switches and a pair of auxiliary switches coupled to a primary winding of a transformer. The main switch and the auxiliary switch intermittently conduct an input voltage source to the primary winding to operate the soft-switched power converter in four phases of operation per switching cycle. In a first phase of operation, the main switch conducts the input voltage source to the transformer. In the second operating phase, the conduction is switched off. In a third operating phase, the transformer operates as an inductor, wherein the auxiliary switch is switched on in a zero voltage or zero current switching mode. In a fourth phase of operation, the auxiliary switch is switched off, so that the flyback energy achieves zero voltage conversion. The zero voltage detection is used to optimize zero voltage switching. The switching frequency is decreased in response to a decrease in the load. In addition, the auxiliary switch is limited according to the reduction of the load. Thus reducing power consumption under light load and no load conditions.

Description

Soft switching power converter with power saving components

technical field

The present invention generally relates to a pulse width modulation (PWM) power converter, and more particularly, the present invention relates to a pulse width modulation power converter using zero voltage switching techniques and power saving components.

Background technique

Power converters have been commonly used to convert an unregulated power source into a constant voltage source. A transformer with primary and secondary windings is the heart of most power converters. Typically, a switching device is connected to the primary winding to control the transfer of energy from the primary winding to and output from the secondary winding. Currently, pulse width modulated power converters can operate at a constant high frequency with reduced size and weight under the control of switching devices. However, this power converter suffers from switching losses, component stress and noise, and electromagnetic interference (EMI).

To address the switching loss issue of pulse width modulated power converters, phase shifting schemes for soft switching operations have been proposed, especially for high frequency power conversion. For example, the full-bridge (fu11-bridge, FB) quasi-resonant zero-voltage switching (zero-voltage switching, ZVS) technique was disclosed on August 8, 1989 to Christopher P. Henze, Ned Mohan and John G. Hayes US Patent No. 4,855,888 "Constant frequencyresonant power converter with zero-voltage switching", US Patent No. 5,442,540 "Soft-SWitching PWM converters" issued to Guichao C Hua and Fred C. Lee on August 15, 1995, and In "Soft-switched full-bridge converters" revealed by YungtaekJang and Milan M. Jovanovic, March 12, 2002. U.S. Patent No. 5,973,939 "Double forward converter with soft-PWM switching" issued to F.Don Tan on October 26, 1999 and U.S. Patent No. 6,191,960 issued to Simon Fraidlin and Anatoliy Polikarpov on February 20, 2001 In "Active clamp isolated power converter and method of operating thereof", active clamp technology has been used in forward zero voltage switching power converter. In US Patent No. 6,069,798 "Asymmetrical power converter and method of operation thereof" issued to Rui Liu on May 30, 2000, an asymmetrical scheme for half-bridge (HB) topology has been developed.

In various ZVS power converters, the transformer's parasitic leakage inductor or at least one additional magnetic component is used as a resonant inductor or a switch to generate circulating current for ZVS and switching operation. The transformer's parasitic leakage inductors or additional magnetic components, while aiding in zero voltage transition and switching, thus increase switching stress and noise. Furthermore, in this approach, the power consumption caused by the circulating current is significantly higher at light or zero load conditions.

Contents of the invention

The present invention provides a zero voltage switching pulse width modulation power converter for high frequency operation. The zero voltage switching pulse width modulation power converter operates at a constant high frequency with low switching losses, low stress and low noise.

The present invention further provides a zero voltage switching pulse width modulation power converter that can achieve zero voltage switching and switching operations without using additional magnetic devices or leakage inductors of transformers.

The present invention also provides a zero voltage switching pulse width modulated power converter that consumes relatively low power under light load and zero load conditions.

Furthermore, the present invention provides a control scheme for optimizing the soft switching of the power converter.

The zero voltage switching pulse width modulation power converter provided by the present invention includes a transformer, a primary circuit and a secondary circuit. The transformer has a primary winding coupled to the primary circuit and a secondary winding coupled to the secondary circuit. The zero voltage switching pulse width modulation further includes a feedback circuit coupled to the output of the secondary circuit to generate a feedback voltage. The primary circuit further includes a controller coupled to the feedback voltage. The controller is operable to conduct the primary winding to an input voltage source in response to the feedback circuit. In addition, the primary circuit further includes a pair of main switches and a pair of auxiliary switches.

The soft-switching power converter further includes: a timing resistor coupled to the controller to adjust a pulse width of a second switching signal; a programming resistor coupled to the controller to change the second switching signal The pulse width of is determined as a function of the load of the power converter, and the controller may further include a reference resistor to determine the switching frequency of the power converter.

The controller is operable to generate first and second switching signals such that each switching cycle of the power converter includes four phases of operation. In a first operation phase, the controller conducts the input voltage source and the primary winding via the main switch by generating the first switching signal. In a second operating phase, the controller switches off the first switching signal. In a third operating phase, the controller generates a second switching signal to conduct the input voltage source to the primary winding via the auxiliary switch. In a fourth operating phase, the second switching signal is switched off.

The present invention further provides a controller, which includes an oscillator, an inverter, first to second comparators, first to third D-type flip-flops, and a first AND gate (AND gate) and a second AND gate.

The oscillator is operable to generate a clock signal, a ramp signal and a sawtooth signal. The inverter has an input terminal that receives the clock signal and an output terminal. The first comparator has a positive terminal connected to a feedback voltage obtained from an output voltage of the power converter, a negative terminal coupled to the ramp signal, and an output terminal. The second comparator has a positive terminal coupled to a variable current, a negative terminal coupled to the sawtooth signal, and an output terminal. A variable current flows through a timing resistor to form a variable voltage, which is compared with the sawtooth signal to generate a signal for generating the second switching signal. The first D-type flip-flop is coupled to the inverter and the output terminal of the first comparator and a voltage source. The first D-type flip-flop further includes an output. The second D-type flip-flop is coupled to the inverter and the output terminals of the second comparator and the voltage source, and the second D-type flip-flop further includes an output. The third D-type flip-flop is coupled to the output terminal of the inverter, and the third D-type flip-flop has a first output and a second output inverted from the first output. The first output of the third D-type flip-flop outputs a first enable signal for the first switching signal. The second output of the third D-type flip-flop outputs a second enable signal for the second switching signal. The first AND gate is coupled to the first D-type flip-flop and the output of the inverter and the first enable signal. The second AND gate is coupled to the second D-type flip-flop and the output of the inverter and the second enable signal. The first AND gate generates a first switching signal to drive the main switch, and the second AND gate generates the second switching signal to drive the auxiliary switch.

The controller further includes a variable current source to generate the variable current. The variable current source includes a programmable current, a current-to-voltage (I/V) resistor, an operational amplifier, a constant current source, a pair of mirror transistors, and a transistor. The programmable current flowing through the I/V resistor produces a voltage that is connected to the positive input terminal of the operational amplifier. A negative input terminal of the operational amplifier is connected to the transistor and the programming resistor, wherein the programming resistor determines a pulse width of the second switching signal as a function of a load of the power converter. The pair of mirror transistors are connected to the constant current source. The transistor is coupled to one of the mirror transistors. Another mirror transistor outputs the variable current.

The oscillator includes a reference voltage, a mirror transistor, a transistor and an operational amplifier to generate a reference current through the reference resistor. The operational amplifier is coupled between the reference voltage, the transistor and the resistor. The transistor is coupled to one of the mirror transistors to generate the reference current.

The oscillator further includes three mirror transistors, a transistor, first and second operational amplifiers, a resistor, and a constant current source mirrored from the reference current. Three mirror transistors are connected to the constant current source. The transistor is coupled to the first mirror transistor. The first operational amplifier is coupled between the transistor and the feedback voltage. The resistor is coupled to the transistor and the first operational amplifier. The second operational amplifier is coupled to the resistor and a threshold voltage. The second mirror transistor outputs the programmable current. The third mirror transistor outputs a programmable discharge current. The programmable current and the programmable discharge current are proportional to the mirror ratio of the mirror transistor and the difference between the feedback voltage and the threshold voltage, and inversely proportional to the resistance of the resistor. Since the feedback voltage decreases in response to a decrease in output load of the power converter, the programmable current and the programmable discharge current decrease under light load and no load conditions.

The oscillator further includes a frequency capacitor operable to determine an operating frequency. The reference current mirrors a charging current associated with the frequency capacitor to generate the ramp signal and determine a maximum on-time of the first switching signal. The oscillator further includes a first pair of mirror transistors and a second pair of mirror transistors, a first disable transistor (first-disable transistor) and a second disable transistor for controlling the discharge current. The reference current further mirrors a discharge current that flows through the second pair of mirrored transistors to discharge the frequency capacitor, wherein the discharge current is enabled by a second discharge signal via the second disable transistor. The discharge current is associated with the frequency capacitor to determine an off time of the second switching signal. The programmable discharge current flows through the first pair of mirror transistors to discharge the frequency capacitor, wherein the programmable discharge current is enabled by a first discharge signal via the first disable transistor. The programmable discharge current is associated with the frequency capacitor to determine an off time of the first switching signal. Since the programmable discharge current is reduced according to a decrease in load under light load conditions, an off time of the first switching signal is increased. At the same time, the off time of the second switching signal remains constant, which maintains a short delay time to achieve zero voltage transition before starting the next switching cycle. Therefore, the off-time of the first switching signal is increased, the switching frequency of the switching signal is reduced, and thus the switching losses and power consumption of the power converter are reduced under light load and no load conditions.

The oscillator further includes three comparators, four NAND gates, NOR gates, transistors, current sources, switches, capacitors and a discharge current mirrored by a reference current. The negative input terminal of the first comparator and the positive input terminal of the second comparator are connected to the frequency capacitor. To determine the switching frequency and the ramp signal, the positive input terminal of the first comparator and the negative input terminal of the second comparator are connected to a high threshold voltage and a low threshold voltage, respectively. The first and second NAND gates form an S-R latch circuit. The inputs of the first and second NAND gates are respectively connected to the outputs of the first and second comparators. The output of the first NAND gate is connected to the clock signal of the input of the third and fourth NAND gates. applying the first and second enable signals to the third and fourth NAND gates to generate the first discharge signal and the Second discharge signal. The clock signal is also applied to turn on the switch associated with the release current and the capacitor to generate the sawtooth signal. Thus, the sawtooth signal is used for comparison with the variable voltage to generate a signal for the second switching signal. The positive input terminal of the third comparator is connected to the current source and the detection diode for detecting a zero voltage transition. The current source is used to pull high. The negative input terminal of the third comparator is coupled to a threshold voltage. Once the third comparator detects a low signal, during the period of the second switching signal, the transistor will be turned on by the NOR gate to quickly discharge the frequency capacitor and start the next switching cycle in time. Thus, the zero voltage switching is achieved and the efficiency of the power converter is improved.

Advantageously, the zero voltage switching PWM power converter of the present invention operates at a constant high frequency with low switching losses, low stress and low noise. The zero voltage switching PWM power converter can achieve zero voltage switching and switching operation without using additional magnetic devices or leakage inductors of the transformer. It consumes relatively low power at light load and zero load conditions.

Description of drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain principles of the invention. In the attached picture,

FIG. 1 is a circuit diagram of a soft-switching power converter according to the present invention.

FIG. 2 illustrates waveforms in different operating phases of each switching cycle of the soft-switching power converter as shown in FIG. 1 .

Fig. 3a illustrates the current flow of the soft-switching power converter as shown in Fig. 1 during the first operation phase of a switching cycle.

Fig. 3b illustrates the current flow of the soft-switching power converter as shown in Fig. 1 during the second operation phase of a switching cycle.

Fig. 3c illustrates the current flow of the soft-switching power converter as shown in Fig. 1 during the third operation phase of a switching cycle.

Fig. 3d illustrates the current flow of the soft-switching power converter as shown in Fig. 1 in the fourth operation phase of a switching cycle.

FIG. 4 is a circuit diagram of a controller of the soft switching power converter as shown in FIG. 1 .

5 and 6 illustrate circuits for generating programmable clock signals to control the pulse width modulation frequency and soft switching operation of the soft switching power converter as shown in FIG. 1 .

FIG. 7 illustrates a circuit for generating a variable current that determines the pulse width of a switching signal applied to an auxiliary switch of a soft-switching power converter as shown in FIG. 1 .

FIG. 8 illustrates the waveforms of the clock signal and the control signal as illustrated in FIG. 4 .

Figure 9 shows the off time of the switching signal applied to the main switch as a function of load.

Figure 10 shows the switching signal applied to the auxiliary switch as a function of load.

Detailed ways

FIG. 1 is a circuit diagram of a soft-switching power converter provided by the present invention. As shown in FIG. 1 , the soft-switching power converter includes a transformer 50 , a pair of main switches 10 and 20 , a pair of auxiliary switches 30 and 40 , and a secondary circuit 150 . The transformer 50 further includes a primary winding Wp coupled to the main and auxiliary switches 10, 20, 30 and 40, and a secondary winding Ws coupled to the secondary circuit. More specifically, in this embodiment, the main switch 10 connects the primary winding Wp from the node A at one end of the primary winding Wp to the input voltage source V _IN , and the node A is further connected to the auxiliary switch 40 . The auxiliary switch 30 connects the input voltage source V _IN from node B at the other end of the primary winding Wp to the primary winding Wp, and the main switch 20 further connects from node B to the primary winding Wp. The main and auxiliary switches 10, 20, 30, and 40 may include, for example, metal-oxide semiconductor field effect transistors (MOSFETs), insulated gate bipolar transistors (insulated gate bipolar transistors, IGBTs) and Gate turn off transistors (gate-tum-off transistors, GTO). As shown in FIG. 1 , the input voltage source V _IN is further connected to a capacitor 5 .

Secondary circuit 150 includes a half-bridge rectifier assembled from diodes 60 (preferably rectifier diodes) and diodes 70 (often called freewheel diodes or reverse diodes with respect to diodes 60). The secondary circuit 150 further includes an inductor 80 and a capacitor 90 . The positive terminal of diode 60 is coupled to one end of secondary winding Ws, and the positive terminal of diode 70 is coupled to the other end of secondary winding Ws. Inductor 80 is connected between the negative terminals of diodes 60 and 70 . One terminal of the capacitor 90 is connected to the positive terminal of the diode 70 and the other terminal is connected between the inductor of the secondary circuit and the output terminal.

As shown in FIG. 1, the main switches 10 and 20 are driven by the switching signal _S1 , and the auxiliary switches 30 and 40 are driven by the switching signal _S2 . Referring to FIG. 2 , the switching signal S ₁ is preferably a pulse signal with a pulse width T ₁ , and the switching signal S ₂ is preferably a pulse signal with a pulse width T ₃ . The soft-switching power converter further includes: a controller 100 for generating switching signals S ₁ and S ₂ ; and a feedback circuit 300 coupled to the output terminal of the secondary circuit to respond to the output voltage V ₀ of the power converter And the feedback voltage V _FB is supplied to the controller 100 .

Feedback circuit 300 includes error amplifier 120 and optocoupler 110 . The output voltage V ₀ of the secondary circuit 150 is fed into the error amplifier 120 from the negative input terminal of the error amplifier 120 via the resistors 130 and 131 , and compared with the reference voltage V _REF . After being compared and amplified by the error amplifier 120 , the feedback voltage V _FB is input to the controller 100 via the optocoupler 110 .

As shown in FIG. 1 , the controller 100 is connected to resistors 315 , 415 , 515 , a feedback voltage V _FB , main switches 10 , 20 , auxiliary switches 30 , 40 and a negative voltage coupled between node B and main switch 20 . terminal of the diode 105. The resistor 315 can be adjusted to determine the pulse width T ₃ of the switching signal S ₂ used to drive the auxiliary switches 30 and 40 . The variation range of the feedback voltage _VFB is determined according to the voltage on the resistor 415, so that the pulse _T3 of the switching signal _S2 can be further adjusted as a function of the load connected to the output terminal of the secondary circuit 150, the output of the power converter A voltage V ₀ is output from the output terminal. The switching frequency of the power converter can be determined by adjusting the resistance of resistor 515 . A detailed description of the various components of the controller 100 will be described further later in this specification.

By controlling the on/off states of the main and auxiliary switches 10 to 40, the power converter as shown in Fig. 1 has four operation phases in each switching cycle, as shown in Fig. 2 and Figs. 3a to 3d. Additionally, to operate the power converter in the four operating phases of each cycle, the switching signals S ₁ and S ₂ must be out of phase. For example, in the embodiment shown in FIGS. 1 and 2 , the main switches 10 and 20 are turned on when the switching signal S ₁ is high during T ₁ of each switching cycle. During the duration _T1 , the auxiliary switches 30 and 40 are switched off. After the switching signal S ₁ has been turned off for a period of time (ie, T ₂ as shown in FIG. 2 ), the auxiliary switches 30 and 40 are turned on for a period of time T ₃ .

The four operational phases are further described as follows with reference to Figures 2 and 3a to 3d. As shown in FIG. 2 , at the beginning of each switching cycle, the main switches 10 and 20 are turned on within the pulse width T ₁ of the switching signal S ₁ . As shown in FIG. 3a, when the main switches 10 and 20 are activated, the current _I1 from the input voltage V _IN flows through the primary winding Wp via the main switches 10 and 20 . Therefore, energy is transferred from the primary circuit to the secondary circuit. Meanwhile, the polarities of the primary winding Wp and the secondary winding Ws are turned on by supplying a forward bias voltage to the rectifier diode 60 , while the freewheel diode 70 is cut off due to the reverse bias voltage supplied thereto. Therefore, the secondary current I2 flows along the secondary circuit, as indicated by the arrows in the secondary circuit. Energy is thus transferred to the output terminal and output at output voltage V ₀ .

After T ₁ , the switching signal S ₁ drops to zero or lower voltage to switch off the main switches 10 and 20 in a second phase of operation as shown in FIG. 2 . Referring to Figure 3b, the primary current _I1 is cut off. However, before the auxiliary switches 30 and 40 are switched on by the switching signal _S2 , a current _I3 is induced to flow from the primary winding Wp via the parasitic diodes of the auxiliary switches 30 and 40 in the second operating phase shown in FIG. 3b flow to the input voltage source. Therefore, the rectifying diode 60 in the secondary winding Ws is reverse biased and cut off, the diode 70 is forward biased and turned on, and a closed loop is formed between the inductor 80 and the capacitor 90 .

Therefore, the secondary winding Ws becomes open circuit and the energy stored in the transformer 50 is reset and freewheeled back to the input voltage source V _IN via the parasitic diodes of the auxiliary switches 30 and 40 . Simultaneously, the energy stored in the inductor 80 and capacitor 90 is continuously transferred to the output terminals of the secondary circuit, and a current _I4 is generated and circulated in a closed loop, as indicated by the arrows in the secondary circuit in FIG. 3b. Furthermore, as shown in Fig. 2, the duration _T2 of the second operating phase may be extended until all the energy stored in the transformer 50 is released. The variable duration of the second operating phase is indicated as T _R in FIG. 2 .

2 and 3c illustrate the third phase of operation in each switching cycle of the soft-switching power converter. As shown in FIG. 2 , the switching signal S2 turns on the auxiliary switches 30 and 40 before starting the next switching cycle, ie before the main switches 10 and 20 are turned on again by the switching signal _S1 . As shown in FIG. 3 c , current I ₅ is directed to flow from node B to node A via primary winding Wp, and energy is stored in transformer 50 . In the primary circuit, the current I ₅ flows in the opposite direction to the current I ₃ generated in the second operating phase. For the secondary circuit, similarly to the second phase of operation, the direction of the current _I5 results in a reverse bias of the rectifying diode 60 such that the secondary winding Ws becomes open circuited. Thus, the transformer 50 operates as an inductor in this phase of operation. The secondary winding Ws is open and no current flows through, so zero-current switching (ZCS) or zero-voltage switching (ZVS) of the auxiliary switches 30 and 40 can be realized. Therefore, the soft-switching power converter operates similarly to a discontinuous mode flyback power converter in this case. Therefore, the energy stored in the transformer 50 in the third phase of operation can be expressed as:

ε=Lp×Ip ² /2,

where Lp is the inductance of the primary winding Wp, and Ip is the current flowing through the primary winding Wp and can be expressed as:

Ip = V _IN × T ₃ /Lp,

Where T ₃ is the turn-on time of the auxiliary switches 30 and 40 . By substituting the equation for Ip into the equation for energy ε,

ε=V _IN ² ×T ₃ ² /(2×Lp).

In the fourth phase of operation as shown in Figures 2 and 3d, the switching signal _S2 drops to zero or low voltage to switch off the auxiliary switches 30 and 40, while the switching signal _S1 remains low or zero, thereby maintaining the main switch 10 and 20 cut off. The current I5 is thus cut off from the primary winding Wp. Meanwhile, the energy generated in the period T ₃ of the third operation stage and magnetizing the transformer 50 flies back to the input voltage source V _IN via the parasitic diodes of the main switches 10 and 20 . Thus, a current I ₇ is generated that flows in the opposite direction to the current I ₁ generated in the first operating phase. This achieves zero voltage switching.

In order to generate a current I ₇ through the main switches 10 and 20 and achieve zero voltage switching during this phase of operation, the parasitic diodes of the main switches 10 and 20 must be switched on. Furthermore, in order to turn on the parasitic diodes of the main switches 10 and 20, their parasitic capacitors must first be discharged. Therefore, to achieve ZVT, the following inequalities must be satisfied:

V _IN ² ×T ₃ ² /(2×Lp)＞2×(Cr×V _IN ² /2)

Where Cr is the parasitic capacitance of the main switches 10 and 20 . The resonant frequency fr between the primary winding Wp and the parasitic capacitors of the main switches 10 and 20 can be expressed as:

fr=1/(2π×(Lp×Cr) ^1/2 ),

The minimum transfer time T _F of the phase shift to achieve zero voltage transition is

T _F =1/(4×fr)=π×(Lp×Cr) ^1/2 /2

That is, the minimum time from when the switching signal _S2 goes low to turn off the auxiliary switches 30 and 40 to when the main switches 10 and 20 are turned on again by the switching signal _S1 , that is, the minimum duration of the fourth phase available T _F calculated by the above equation. From the above equation, it is known that the minimum time required to achieve zero voltage transition is determined by the inductance of the primary winding Wp and the parasitic capacitance Cr.

The duration of the fourth operation phase may be delayed by a delay time Tz after the parasitic diodes of the main switches 10 and 20 are turned on and before starting the next switching cycle. Therefore, the total duration of the fourth operating phase is the sum of the minimum transfer time T _F and the delay time Tz, ie T ₄ =T _F +Tz. However, in order to operate the inductor 80 in continuous mode under conditions of zero voltage switching, the energy stored in the transformer 50 during the duration _T3 of the third operating phase must satisfy the following inequality:

V _IN ² ×T ₃ ² /(2×Lp)＞{[Cr×V _IN ² ]+[V _IN ×(Ns/Np)×I _O ×T _Z ]+[T _Z ×V _IN ² ×T ₃ /Lp]},

Among them, Ns and Np are the turns of the secondary winding Ws and the primary winding Wp respectively, and I ₀ is the output current of the power converter. That is, the energy stored in the transformer 50 must be large enough for the duration _T3 to discharge the parasitic capacitance 2Cr and then provide the primary side reverse flywheel current and maintain the output current during the delay time Tz.

Furthermore, to optimize the soft handover operation, the delay time Tz must be minimized to save energy. Once the controller 100 detects a zero voltage transition via the diode 105 in the fourth operating phase, the main switches 10 and 20 are momentarily switched on by the switching signal S ₁ . Therefore, it is possible to minimize the delay time Tz and optimize the soft handover operation.

FIG. 4 is a circuit diagram of the controller 100 for generating the switching signals _S1 and _S2 . As shown in FIG. 4 , the controller 100 includes an oscillator 200 , an inverter 370 , comparators 320 and 330 , a variable current source 310 , D-type flip-flops 340 , 350 and 360 , and AND gates 380 and 390 . Oscillator 200 is coupled to the input of inverter 370 , the negative inputs of comparators 320 and 330 . The output of inverter 370 is coupled to the inputs of D-type flip-flops 340 , 350 , 360 and AND gates 380 and 390 . D-type flip-flop 340 is further coupled to voltage source V _CC and the output of comparator 320 , whose output is coupled to AND gate 380 . Enable signals S _A and S _B output by D-type flip-flop 350 are inverted and fed into AND gates 380 and 390 , respectively. D-type flip-flop 360 is further coupled to the output of comparator 330 and voltage source V _CC , while the output of D-type flip-flop 360 is coupled to the input of AND gate 390 . Switching signals _S1 and _S2 are output from AND gates 380 and 390 to drive main switches 10, 20 and auxiliary switches 30, 40, respectively.

As shown in FIG. 4, D-type flip-flop 350 provides enable signals S _A and S _B to AND gates 380 and 390, respectively, to ensure that main switches 10, 20 and auxiliary switches 30 and 40 as shown in FIG. Driven in individual phases and slightly less than 50% of the maximum duty cycle. The oscillator 200 is operable to generate a clock signal 210 , a ramp signal 220 and a sawtooth signal 230 . Clock signal 210 determines the PWM switching frequency of the power converter and provides an off-time (dead time) between pulses of switching signals S ₁ and S ₂ to achieve a phase shift for zero voltage switching. The feedback voltage V _FB reflecting the output voltage V ₀ of the power converter is compared with the ramp signal 220 in a comparator 320 . When the feedback voltage V _FB is high, the pulse width T ₁ of the switching signal S ₁ becomes wider and more power is transferred to the output of the power converter. Therefore, the feedback voltage V _FB derived from the output voltage V ₀ can be used to regulate the output voltage V ₀ . The feedback voltage V _FB is compared with the ramp signal 220 generated by the oscillator 200 in a comparator 320 . The sawtooth signal 230 generated by the oscillator 200 is synchronized with the ramp signal 220 , and the amplitude of the sawtooth signal 230 is inversely proportional to the amplitude of the ramp signal 220 . Variable current source 310 generates a variable current Im through resistor 315 as a function of feedback voltage V _FB , thereby generating a variable voltage across resistor 315 . The sawtooth signal 230 is compared with the variable voltage generated by the variable current source 310 in a comparator 330 . By adjusting the variable current Im, the variable voltage on the resistor 315 is programmable, so that the pulse width _T3 of the switching signal _S2 can be programmed or adjusted. When the feedback voltage increases according to the increase of the load, the variable current Im will increase and the pulse width T ₃ of the switching signal S ₂ will widen, as shown in FIG. 10 .

The variable current source 310 shown in FIG. 7 includes a programmable current source 420 , a resistor 425 , an operational amplifier 410 , a current source 490 , a pair of mirror transistors 460 , 480 and a transistor 450 . Programmable current source 420 flows through resistor 425 to generate a voltage that is connected to the positive input terminal of operational amplifier 410 . The negative input terminal of the operational amplifier 410 is connected to the transistor 450 and the programming resistor 415 to generate a current according to the voltage of the resistor 425, wherein the programming resistor 415 determines the pulse width _T3 of the switching signal _S2 as the load of the power converter The function. The pair of mirrored transistors 460 , 470 is connected to a current source 490 . Transistor 450 is coupled to mirror transistor 460 . The mirror transistor 470 outputs a variable current Im.

Referring to FIG. 5 , the oscillator 200 includes a reference voltage V ₁ , a transistor 551 , a transistor 553 and an operational amplifier 510 to generate a reference current through a resistor 515 . The operational amplifier 510 is coupled between the reference voltage V ₁ , the transistor 553 and the resistor 515 . Transistor 553 is coupled to transistor 551 to generate a reference current. The oscillator further comprises three mirror transistors 561 , 562 , 563 , transistor 560 , two operational amplifiers 520 and 521 , resistor 540 and a current source mirrored by transistor 557 from the reference current. Transistors 561 , 562 , 563 are connected to transistor 557 . Transistor 560 is coupled to transistor 561 . The positive terminal of operational amplifier 520 is coupled to feedback voltage V _FB , and the negative terminal of operational amplifier 520 is coupled to transistor 560 . Resistor 540 is coupled to transistor 560 and operational amplifier 520 . Opamp 521 is coupled to resistor 540 and the positive terminal of opamp 521 is coupled to threshold voltage V _TH . Transistor 562 mirrors programmable current 420 from transistor 561 . Transistor 563 mirrors the programmable discharge current from transistor 561 . The programmable current 420 and the discharge programmable current are proportional to the mirror ratio of the mirror transistors 561 , 562 , 563 and the difference between the feedback voltage V _FB and the threshold voltage V _TH , and are inversely proportional to the resistance of the resistor 540 . As the feedback voltage V _FB decreases in response to a decrease in the output load of the power converter, the programmable current 420 and the programmable discharge current decrease under light load and no load conditions.

The oscillator 200 further includes a capacitor 530 operable to determine an operating frequency. The charging current Ic mirrored from the reference current is associated with the capacitor 530 and used to generate the ramp signal 220 and determine the maximum turn-on time of the first switching signal S ₁ . The oscillator 200 further includes a first pair of mirror transistors 564, 565, a second pair of mirror transistors 574, 575, a first disable transistor 568, and a second disable transistor 578 for controlling the discharge current _ID . The discharge current mirrored from the reference current by transistor 559 flows through a second pair of mirrored transistors 574 , 575 to discharge capacitor 530 . The discharge current _ID is enabled by the second discharge signal WB via the second disable transistor 578 . The discharge current _ID is associated with the capacitor 530 to determine the off-time T _OFF of the second switching signal S ₂ . The programmable discharge current mirrored from transistor 563 flows through a first pair of mirrored transistors 564 , 565 to discharge capacitor 530 . The programmable discharge current is enabled by the first discharge signal WA via the first disable transistor 568 . A programmable discharge current is associated with the capacitor 530 to determine the off-time T _OFF of the first switching signal S ₁ . Since the programmable discharge current decreases according to the decrease of the load under the light load condition, the off-time T _OFF of the first switching signal S ₁ increases accordingly, as shown in FIG. 9 . Meanwhile, the off-time T _OFF of the second switching signal S ₂ remains constant, which maintains a short delay time T ₄ to achieve zero voltage transition before starting the next switching cycle, as shown in FIG. 8 . Therefore, the off-time T _OFF of the first switching signal S ₁ is increased, the switching frequency of the switching signal is reduced, and thus the switching loss and power consumption of the power converter are reduced under light load and no load conditions.

The switching frequency Freq of the oscillator is the reciprocal of the period, expressed as:

Freq=1/T=1/(2×T _ON +T _OFF +T ₄ ),

Where in each switching cycle, the transformer 50 is turned on to the input voltage source V _IN twice, once via the main switches 10 and 20, and once via the auxiliary switches 30 and 40, so that each period T contains two turn-on times, which Expressed as 2×T _ON (T ₁ and T ₃ ). In addition, the main and auxiliary switches 10 to 40 also switch twice in each cycle, ie one off time denoted by T _OFF and another off time T ₄ .

The turn-on time, turn-off time, and _T4 can be derived from capacitance 530 ("Cc"), the voltage drop across capacitor 530, and the current flowing through it, as follows:

T _ON ＝Cc×(V _H -V _L )/I _C

Wherein Ic is the charging current of the capacitor 530;

T _OFF ＝Cc×(V _H -V _L )/Id-A

where Id-A is the discharge current through capacitor 530 supplied from transistors 564, 565 and 568 under the control of signal WA;

T ₄ =Cc×(V _H -V _L )/Id-B

where Id-B is the discharge current of capacitor 530 supplied from transistors 574, 575 and 578 under the control of signal WB during the duration _T4 of the fourth operating phase.

In addition, the charging current Ic and the discharging currents Id-A and Id-B can be expressed as:

Ic=(V ₁ /R ₅₁₅ )×K1,

Where V ₁ is a reference voltage, and K1=N ₅₅₈ /N ₅₅₁ , which is the geometric ratio of the transistor 558 to the transistor 551;

Id-A=[(V _FB -V _TH )/R ₅₄₀ ]×K2

where (V _FB −V _TH ) is the voltage drop across resistor 540, and K2=(N ₅₆₃ /N ₅₆₁ )×(N ₅₆₅ /N ₅₆₄ ), which is determined by the geometric ratio of transistors 563, 561 and transistors 565, 564 to determine; and

Id-B=(V ₁ /R ₅₁₅ )×K3

where K3 = (N ₅₅₉ /N ₅₅₁ )×(N ₅₇₅ /N ₅₇₄ ), which is the product of the geometric ratios of transistors 559 , 551 and transistors 575 , 574 .

The oscillator 200 further includes three comparators 710, 720, 730, four NAND gates 740, 750, 770, 780, a NOR gate 790, a transistor 725, a current source 715, a switch 625, a capacitor 540 and a reference current mirror The discharge current 620 of the shot. The negative input terminal of comparator 710 and the positive input terminal of comparator 720 are connected to capacitor 530 . To determine the switching frequency and ramp signal 220, the positive input terminal of comparator 710 and the negative input terminal of comparator 720 are connected to the high threshold voltage _VH and the low threshold voltage _VL , respectively. NAND gates 740, 750 form an SR latch circuit. The inputs of NAND gates 740 and 750 are connected to the outputs of comparators 710 and 720, respectively. NAND gate 740 outputs clock signal 210 which is connected to inputs of NAND gates 770 and 780 . The first and second enabling signals Sa and SB are respectively applied to the NAND gates 770 and 780 to generate the first discharge signal WA and the second discharge signal WA for the off-time control of the first and second switching signals _S1 and _S2 discharge signal WB. Clock signal 210 is also applied to turn on switch 625 associated with release current 620 and capacitor 540 to produce sawtooth signal 230 as shown in FIG. 8 . Therefore, the sawtooth signal 230 is used for comparison with a variable voltage to generate a signal for the second switching signal _S2 . The positive input terminal of comparator 730 is connected to current source 715 and detection diode 105 for detecting zero voltage transitions. Current source 715 is used to pull high. The negative input terminal of comparator 730 is coupled to threshold voltage V ₂ . Once the low signal is detected by the comparator 730, during the period of the second switching signal _S2 , the transistor 725 will be turned on by the NOR gate 790 to quickly discharge the capacitor 530 to start the next switching cycle in time. Thus zero voltage switching is achieved and the efficiency of the power converter is improved.

As shown in Fig. 9, in response to the decrease of the feedback voltage V _FB , the duration T _OFF for turning off the main switches 10, 20 increases with the slope K _x until a minimum value T _min is reached. which can be expressed as

T _OFF ＝k _x ÷(|V _FB -V _TH |)

where T _OFF >T _min >0.

On the contrary, as shown in Fig. 10, the duration for which the auxiliary switch 30, 40 is switched on, ie its pulse width _T3 increases with the slope _qx until a maximum value _Tmax is reached. The resistance of the resistors 315, 415 determines the slope _qx . which can be expressed as

T ₃ =q _x ×(V _FB -V _TH )

q _x = (R ₃₁₅ /R ₄₁₅ )×K5

Where K5 is a constant.

In the proposed circuit, the main switch and auxiliary switch are operated by ZVS and ZCS, respectively. Compared with the state-of-the-art of soft switching, no additional magnetic device or leakage inductance of the transformer is required. Consequently, switching losses, stress and noise are reduced. Furthermore, the power consumption of the power converter is additionally reduced under light load conditions due to the reduced switching frequency.

It will be readily apparent to those skilled in the art that various modifications and changes can be made in the structure of this invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover the modifications and variations of this invention that come within the scope of the appended claims and their equivalents.

Claims (14)

1. soft switch power converter, it comprises:

Transformer, it has winding and secondary winding;

Primary circuit, it is coupled to a described winding, and wherein said primary circuit further comprises a pair of main switch and a pair of auxiliary switch,

Secondary circuit, it is coupled to described secondary winding;

Feedback circuit, its output of being coupled to described secondary circuit is to produce feedback voltage; And

Controller, it is coupled to feedback voltage and described primary circuit, described controller is operated in response to described feedback circuit a described winding is conducting to input voltage source, wherein said controller is operated producing first switching signal and second switching signal of out-phase each other, thereby drives described main switch and described auxiliary switch respectively.

2. soft switch power converter according to claim 1, it further comprises:

Detect diode, it is connected between described main switch and the described controller, and wherein said detection diode is operated with when detecting the Zero voltage transition condition of described transformer, produces the detection signal that outputs to described controller.

3. soft switch power converter according to claim 1, it further comprises:

The sequential resistor, it is coupled to described controller to adjust the pulse duration of described second switching signal;

The programming resistors device, it is coupled to described controller is defined as the load of described power converter with the pulse duration with described second switching signal function; And

Reference resistor, it is used to adjust the switching frequency of described power converter.

4. power converter, it comprises:

Transformer, it has winding and secondary winding;

Primary circuit, it is coupled to a described winding, and described primary circuit further comprises:

First main switch, it is connected to the first terminal of an input voltage source and a described winding;

Second main switch, it is connected to second terminal of a described winding, in order to receive first switching signal;

First auxiliary switch, it is connected to the described secondary terminal of a described input voltage source and a described winding;

Second auxiliary switch, it is connected to described the first terminal, in order to receive second switching signal;

Controller, it is operated to produce described first and second switching signals;

Detect diode, it is coupled between the detection input of a described winding and described controller, to detect the transition status of described transformer;

Feedback circuit, it is operated to produce feedback voltage in response to the output voltage of described power converter to described controller; And

Secondary circuit, it is connected between the output of described secondary winding and described power converter, and wherein said secondary circuit further comprises:

Half bridge rectifier, it is coupled to described secondary winding;

Inductor, it is coupled to described half bridge rectifier; And

Capacitor, it is coupled to described inductor.

5. power converter according to claim 4, wherein said power converter was operated in a plurality of operational phases, comprising:

In first operational phase, described controller is operated to produce described first switching signal, with via a described input voltage source of described main switch conducting and a described winding, wherein when described first switching signal produced, electric current was switched on and flows to from the described the first terminal of a described winding via described first and second main switches described second terminal of a described winding;

In second operational phase, described first switching signal is cut off so that described input voltage source is connected with described winding disconnection, wherein said first switching signal is cut off, and electric current is caused and flows to described input voltage source via described first and second auxiliary switches from a described winding;

In the 3rd operational phase, described second switching signal is produced via described auxiliary switch described input voltage source is conducting to a described winding, wherein said second switching signal is produced, and electric current is switched on and flows to from described second terminal of a described winding via described first and second auxiliary switches described the first terminal of a described winding; And

In the 4th operational phase, described second switching signal is cut off so that described input voltage source is connected with described winding disconnection, wherein when described second switching signal was cut off, electric current was caused and flows to described input voltage source via described first and second main switches from a described winding.

6. power converter according to claim 4, wherein said controller further comprises:

Oscillator, it is operated with clocking, ramp signal and serrated signal;

A plurality of D flip-flops, it is operated producing first output in response to described clock signal, the feedback voltage that produces in response to the output voltage of described power converter and described ramp signal, produces second output in response to described clock signal and described serrated signal and the variable voltage that produces in response to variable current and described sequential resistor; And

Two and door, to export in response to described first output and described second and to produce described first and second switching signals respectively, the described pulse duration of wherein said second switching signal is adjusted by described variable voltage through operation for it.

7. controller, it is applicable to and comprises the power converter of transformer with the conducting of control input voltage source and described transformer that described controller comprises:

Oscillator, it is operated with clocking, ramp signal and serrated signal;

Inverter, it has input terminal and the lead-out terminal that receives described clock signal;

First comparator, it has the plus end that is connected to the feedback voltage that obtains from the output voltage of described power converter, the negative terminal that is coupled to described ramp signal, and lead-out terminal;

Second comparator, it has the plus end that is coupled to described variable current and described sequential resistor, the negative terminal that is coupled to described serrated signal, and lead-out terminal;

First D flip-flop, it is coupled to the described lead-out terminal and the voltage source of described inverter and described first comparator, and described first D flip-flop further comprises output;

Second D flip-flop, it is coupled to the described lead-out terminal and the described voltage source of described inverter and described second comparator, and described second D flip-flop further comprises output;

The 3rd D flip-flop, it is coupled to the described lead-out terminal of described inverter, and described the 3rd D flip-flop has first output and second output reverse with described first output;

First with door, it is coupled to first output of the described output of described first D flip-flop and described inverter and described the 3rd D flip-flop; And

Second with door, it is coupled to described second output of the described output of described second D flip-flop and described inverter and described the 3rd D flip-flop.

8. controller according to claim 7, wherein said first is operated producing first switching signal driving described main switch with door, and described second is operated to produce described second switching signal to drive described auxiliary switch with door.

9. controller according to claim 7, it further comprises variable current source, in order to produce described variable current, wherein said variable current is adjusted in response to described feedback voltage.

10. controller according to claim 9, wherein said variable current source further comprises:

Electric current changes voltage resistor voltage;

Programmable current, it changes voltage resistor voltage and produces programmable voltage via described electric current;

Constant current source;

A pair of mirrored transistor, it is connected to described constant current source;

Transistor, it is coupled to one in the described mirrored transistor; And

Operational amplifier, it is coupled between the described programmable voltage of described transistor AND gate, thereby produces described variable current by described programming resistors device and mirrored transistor.

11. controller according to claim 7, wherein said oscillator comprises:

Reference voltage;

Mirrored transistor;

Transistor; And

Operational amplifier, it produces reference current via described reference resistor, wherein said operational amplifier is coupled between described reference voltage, the described reference resistor of described transistor AND gate, and described transistors couple in the described mirrored transistor one to produce described reference current.

12. controller according to claim 7, wherein said oscillator further comprises:

Three mirrored transistor;

Transistor;

First and second operational amplifiers;

Resistor; And

Constant current source, it is from described reference current mirror, wherein said three mirrored transistor are connected to described constant current source, described transistors couple in the described mirrored transistor first, described first operational amplifier is coupled between the described feedback voltage of described transistor AND gate, described resistor is coupled to described transistor and described first operational amplifier, described second operational amplifier is coupled to described resistor and threshold voltage, the two exports described programmable current in the described mirrored transistor, the third party in the described mirrored transistor exports discharging current able to programme, the mirror ratio and the difference between described feedback voltage and the described threshold voltage of described programmable current and described discharging current able to programme and described mirrored transistor are proportional, and be inversely proportional to the resistance of described resistor, owing to the minimizing of described feedback voltage in response to the output loading of described power converter reduces, therefore described programmable current and described discharging current able to programme reduce under light-load conditions and no-load condition.

13. controller according to claim 7, wherein said oscillator further comprises:

The frequency capacitor, it is operated with definite frequency of operation,

Charging current, it is from described reference current mirror, and described charging current is associated with described frequency capacitor, to produce the maximum opening time of described ramp signal and definite described first switching signal;

First pair of mirrored transistor and second pair of mirrored transistor,

First disable transistor and second disable transistor;

Discharging current, it is from described reference current mirror, and wherein said discharging current is flowed through described second pair of mirrored transistor so that described frequency capacitor is discharged, and wherein said discharging current is enabled by second discharge signal via described second disable transistor; Wherein said discharging current is associated with described frequency capacitor to determine the shut-in time of described second switching signal; Described discharging current able to programme is flowed through described first pair of mirrored transistor so that described frequency capacitor is discharged, and wherein said discharging current able to programme is enabled by first discharge signal via described first disable transistor; Wherein said discharging current able to programme is associated with described frequency capacitor to determine the shut-in time of described first switching signal; The minimizing according to load under light-load conditions of described discharging current able to programme reduces, therefore the corresponding increase of described shut-in time of described first switching signal; The described shut-in time of described second switching signal remains constant simultaneously, and it keeps short delaing time so that next realizes Zero voltage transition before switching circulation in beginning; In addition, when the described shut-in time of described first switching signal increased, the described switching frequency of described switching signal reduced.

14. controller according to claim 7, wherein said oscillator further comprises:

Three comparators, wherein the positive input terminal of the negative input end of first comparator and second comparator is connected to described frequency capacitor; For determining described switching frequency and described ramp signal, the positive input terminal of described first comparator and negative input end of described second comparator are connected respectively to high threshold voltage and low threshold voltage;

Four NAND gate, wherein said first and second NAND gate form the S-R latch cicuit; The input of described first and second NAND gate is connected respectively to the output of described first and second comparators; Described first NAND gate output is connected to the clock signal of the input of third and fourth NAND gate; Wherein enable signal and be applied to described third and fourth NAND gate, be used for described first discharge signal and described second discharge signal of the described shut-in time control of described first and second switching signals with generation described first and second;

NOR gate;

Transistor;

Current source, it is used to draw high;

Switch;

Capacitor; And

Release current, it is from described reference current mirror; Wherein apply described clock signal to open described switch, described switch is associated to produce described serrated signal with described release current and described capacitor; The positive input terminal of the 3rd comparator is connected to described current source and is used to detect the described detection diode of Zero voltage transition; Negative input end of wherein said the 3rd comparator is coupled to threshold voltage; In case described the 3rd comparator detects low signal, so during the cycle of described second switching signal, described transistor will be opened by described NOR gate, with to the repid discharge of described frequency capacitor and in time begin described next switch circulation.

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