JP2000214828A - Liquid crystal display - Google Patents

Abstract

(57) [Summary] An object of the present invention is to provide a liquid crystal display device which performs high quality liquid crystal display. When an analog switch in a block is turned on, a display signal is supplied to a block in a display area from a digital driver via a common signal line for a block control time.
When the display signal D is supplied to the block B1, a reset signal R is supplied from a timing generation circuit (not shown) to the reset circuit 26, and the potentials of the common signal lines D1 to Dn are set to the reset potential Vrs. When one horizontal scanning period ends, a blanking period Tbk starts. At the end of the blanking period Tbk, the reset signal R is supplied from the timing generation circuit to the reset circuit 28. As a result, the reset circuit 28 operates, and the potential of the signal line 46 is set to the reset potential Vrs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device having a reset circuit for resetting the potential of a signal line to a reference potential at a predetermined cycle.
In recent years, a liquid crystal display device capable of performing higher quality liquid crystal display has been desired.

[0002]

2. Description of the Related Art FIG. 1 is a basic structural view of a conventional active type liquid crystal display device 10. As shown in FIG. As shown in FIG. 1, the liquid crystal display device 10 includes a signal line unit 12 and a pixel cell unit 14. The pixel cell section 14 includes a pixel TFT (Thin Film).
Transistor) 16, a liquid crystal _CLC and a storage capacitor Cs.

At the time of liquid crystal display, a scanning signal G is applied to a scanning line from a gate driver (not shown). Then, when the scanning signal G is input to the gate electrode of the pixel TFT 16, the pixel TFT 16 is turned on. On the other hand, the signal line portion 1
2, a display signal D is supplied from a data driver (not shown) via the input unit 18. When the display signal D passes through the pixel TFT 16 in the ON state, the liquid crystal _CLC and the storage capacitance C
_Written to _S. Then, liquid crystal display is performed based on a potential difference between a pixel potential Vs generated by writing the display signal D into the liquid crystal _CLC and the storage capacitor Cs and a potential of a counter electrode (not shown). The written display signal D is held until the scanning signal G is supplied to the pixel TFT 16 again. A period during which the display signal D is held is defined as a signal holding period. In FIG. 1, R _SL and C _SL indicate the resistance value and the electric capacitance of the signal line unit 12, respectively.

When a DC voltage is continuously supplied to the liquid crystal _CLC for a long time, the material characteristics of the liquid crystal _CLC change and the liquid crystal CLC changes.
_LC deteriorates. Therefore, conventionally, the liquid crystal display device 1
0 is driven by an AC voltage whose polarity is inverted at a predetermined cycle. 2 and 3 are waveform diagrams of the scanning signal G and the display signal D supplied to the pixel cell unit 14 of the liquid crystal display device 10. FIG. FIG. 2 shows the waveforms of the scanning signal G and the display signal D supplied to the pixel cell unit 14 arranged on the upper side of the display panel provided in the liquid crystal display device 10. FIG. 3 shows a scanning signal G supplied to a pixel cell unit 14 disposed below a display panel included in the liquid crystal display device 10.
And the waveform of the display signal D.

As shown in FIGS. 2 and 3, one frame is divided into first and second fields. Each pixel cell unit 1 in the display panel of the liquid crystal display device 10
4, a display signal D having a potential in the range of + Vmax (for example, +5 V) to + Vmin (for example, +2 V) is supplied in the first field, and in the second field,
The display signal D having a potential in a range from -Vmax (for example, -5 V) to -Vmin (for example, -2 V) is supplied.
Here, the center value of the amplitude of the display signal D is Vcom (for example, 0 V).

As shown in FIG. 2, the potential of the scanning signal G supplied to the upper pixel TFT 16 of the display panel becomes -Vg (for example, -8) immediately after the start of the first and second fields.
V) to + Vg (for example, +8 V). At this time, the pixel TFTs 16 arranged on the upper side of the display panel are turned on, and the display signal D is written. On the other hand, as shown in FIG. 3, the potential of the scanning signal G supplied to the pixel TFT 16 on the lower side of the display panel changes from -Vg to + Vg just before the end of the first and second fields. At this time, the pixel TFT 16 arranged on the lower side of the display panel is turned on, and the display signal D
Is written.

In FIGS. 2 and 3, Vgs is:
The gate-source voltage of the pixel TFT 16 of the liquid crystal display device 10 is shown, and Vds is the source-drain voltage of the pixel TFT 16. For example, Vmax = 5V, V
When min = 2V and Vg = 8V, as shown in FIG.
The voltages Vgs and Vds of the pixel TFT 16 arranged on the upper side of the display panel are 3 V and 0.5 V, respectively. Further, as shown in FIG. 3, the voltages Vgs and Vds at the pixel TFT 16 arranged on the lower side of the display panel are:
They are 13V and 10V, respectively. As described above, the voltages Vgs and V of the pixel TFT 16 depend on the upper and lower positions of the pixel TFT 16 in the display panel of the liquid crystal display device 10.
ds is different.

FIG. 4 shows the drain current I of the pixel TFT 16.
FIG. 4 is a diagram showing a relationship between d and a voltage Vg of a gate electrode. As shown in FIG. 4, the magnitude of the on-current, which is the charging current when the display signal D is written to the pixel TFT 16, and the magnitude of the off-current, which is the leakage current when the charge is retained, are determined by the pixel TFT 16
Depends on the voltage Vds and the voltage Vgs. Here, as described with reference to FIGS. 2 and 3, the pixel TFT in the display panel of the liquid crystal display device 10 is used.
The voltage V of the pixel TFT 16 depends on the position above and below the pixel TFT 16.
gs and Vds are different. That is, the magnitudes of the ON current and the OFF current of the pixel TFT 16 are different between the upper side and the lower side of the display panel provided in the liquid crystal display device 10.

[0009]

FIG. 5 shows that an initial potential V _SL0 of the potential V _SL of the signal line section 12 shown in FIG.
FIG. 9 is a diagram illustrating a relationship with a rising time Tr required to rise to s. As shown in FIG. 5, for example, when the initial potential V _SL0 is V1, it takes time Tr1 for the pixel potential to rise to the potential Vs. Also, if initial potential V _{SL 0} is V2, until the pixel potential rises to the potential Vs it is time consuming Tr2. When the initial potential V _SL0 is V3, a time Tr3 is required until the pixel potential rises to the potential Vs. Here, as shown in FIG. 5, the magnitude relationship between the potentials V1, V2, and V3 is V1
>V2> V3. Then, the rise time Tr1,
The magnitude relationship between Tr2 and Tr3 is Tr1 <Tr2 <Tr3
It is. As described above, the rising time Tr required for the pixel potential to reach the potential Vs differs depending on the magnitude of the initial potential V _SL0 of the signal line unit 12.

Here, in the conventional liquid crystal display device 10, the initial potential V _SL0 of the signal line section 12 before the scanning signal G is applied differs depending on the signal line. Therefore, the rise time Tr of the pixel potential also differs depending on the signal line,
The writing time of the display signal D varies. Since the writing time of the display signal D varies, it is difficult for the conventional liquid crystal display device 10 to perform a uniform liquid crystal display.

As described with reference to FIGS. 2 to 4, the liquid crystal display device 10 is disposed on the lower side of the display panel in comparison with the off current of the pixel TFT 16 disposed on the upper side of the display panel. The off current of the pixel TFT 16 is much larger. For this reason, the reduction rate of the pixel voltage of the pixel TFT 16 disposed on the lower side of the display panel is greater than the reduction rate of the pixel voltage of the pixel TFT 16 disposed on the upper side of the display panel, and the luminance becomes uneven in the display panel. Vertical tilt display occurred. Specifically, for example, when the liquid crystal display device 10 performs black liquid crystal display, the black display on the lower side of the display panel is thin.

The present invention has been made in view of the above point, and resets the signal line potential to a reference potential at a predetermined cycle, thereby increasing the rise time Tr of the pixel potential and the pixel TF.
It is an object to provide a liquid crystal display device which performs high-quality liquid crystal display by making the off-state current of T16 uniform.

[0013]

Means for Solving the Problems In order to solve the above problems, the present invention is characterized by taking the following means. According to the invention described in claim 1, pixel cells arranged in a matrix in a display panel, a plurality of signal lines and scanning lines connected to the pixel cells, a driver for providing a display signal to the signal lines, And a reset circuit for resetting the potential of the signal line to a predetermined potential at a period of.

According to the present invention, the pixel cells arranged in a matrix in the display panel, a plurality of signal lines and scanning lines connected to the pixel cells, and an analog switch connected to the signal lines And a driver connected to the analog switch via a common signal line and supplying a display signal to the signal line via an on-state analog switch, and resetting the potential of the signal line to a predetermined potential at a predetermined cycle. And a reset circuit.

According to the third aspect of the present invention, the first or second aspect is provided.
In the liquid crystal display device described above, the reset circuit is connected to the signal line. Claim 4
According to a preferred embodiment of the present invention, in the liquid crystal display device according to the first or second aspect, the reset circuit is connected to an output unit of the driver. According to a fifth aspect of the present invention, in the liquid crystal display device according to the first or second aspect, the reset circuit includes a first reset circuit connected to the signal line and a second reset circuit connected to an output unit of the driver. And a reset circuit.

According to a sixth aspect of the present invention, in the liquid crystal display device of the second aspect, the reset circuit is connected to the common signal line. According to a seventh aspect of the present invention, in the liquid crystal display device according to the second aspect,
The reset circuit includes a third reset circuit connected to the signal line, and a fourth reset circuit connected to one of the output section of the driver and the common signal line. .

According to the first to seventh aspects of the present invention, the reset circuit resets the potential of the signal line or the like to a predetermined potential at a predetermined cycle. For this reason, the rise time of the potential of the pixel cell at the time of writing the display signal becomes uniform, and the writing time of the display signal becomes equal in all the pixel cells. Further, since the potential of the signal line or the like is reset to a predetermined potential at a predetermined cycle, the off current in each pixel cell during the signal holding period becomes equal. Therefore, a high-quality liquid crystal display with uniform luminance on the display panel is realized. The number and arrangement position of the reset circuits included in the liquid crystal display device are determined in consideration of the circuit configuration and the like in the liquid crystal display device so that the signal line potential can be reliably reset to a predetermined potential in a short time. And

According to an eighth aspect of the present invention, in the liquid crystal display device according to any one of the first to seventh aspects, the reset circuit receives the reset signal during a blanking period of one horizontal scan. The potential of the line is reset to the predetermined potential. According to the eighth aspect, the potential of the signal line is reset to a predetermined potential during a blanking period of one horizontal scan. Therefore, the initial potentials of all the signal lines are surely uniform. Therefore, the rise time of the potential of the pixel cell at the time of writing the display signal is reliably made uniform.

According to a ninth aspect of the present invention, a plurality of pixel cells arranged in a matrix in a display panel divided into a plurality of blocks, a plurality of signal lines and scanning lines connected to the pixel cells, and An analog switch connected to a line, a driver connected to the analog switch via a common signal line, and providing a display signal to a signal line in a block sequentially activated by a block control signal; A reset circuit for resetting the potential of the line to a predetermined potential.

According to the ninth aspect of the present invention, the potentials of the signal lines and the like in the display panel driven sequentially by the block selection are reset to a predetermined potential at a predetermined cycle by the reset circuit. For this reason, the rise time of the potential of the pixel cell at the time of writing the display signal becomes uniform, and the writing time of the display signal becomes equal in all the pixel cells. Further, since the potential of the signal line or the like is reset to a predetermined potential at a predetermined cycle, the off current in each pixel cell during the signal holding period becomes equal. Therefore, a high-quality liquid crystal display with uniform luminance on the display panel is realized.

According to a tenth aspect of the present invention, in the liquid crystal display device according to the ninth aspect, the reset circuit is provided with a reset signal for each blanking period of one block scan or one horizontal scan, so that the reset signal is supplied to the signal line. The potential is reset to the predetermined potential. According to the tenth aspect, the potential of the signal line is reset to a predetermined potential during a blanking period of one block or one horizontal scan. Therefore, the initial potentials of all the signal lines are surely uniform. Therefore, the rise time of the potential of the pixel cell at the time of writing the display signal is reliably made uniform.

According to the eleventh aspect of the present invention, the first to the first aspects are provided.
0. The liquid crystal display device according to claim 1, wherein a polarity of the predetermined potential is inverted in synchronization with the display signal which is an AC signal. A twelfth aspect of the present invention is characterized by including an internal LSI circuit that generates a display signal, an OP amplifier, and a reset circuit that resets the potential of the output portion of the display signal to the outside to a predetermined potential.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the principle of the present invention will be described with reference to FIG. FIG. 6 is a basic configuration diagram of the liquid crystal display device 20 for explaining the principle of the present invention. As shown in FIG. 6, the liquid crystal display device 20 has a display panel 24. The display panel 24 includes the signal line section 12 and the pixel cell section 1.
4 etc. are provided. The same components as those of the liquid crystal display device 10 shown in FIG. 1 are denoted by the same reference numerals.

In the liquid crystal display device 20, the signal line section 12
Has a plurality of signal lines 46 to which reset circuits 26 and 28 are connected. The reset circuit 26
The reset circuit 28 is connected to the signal line 46 outside the display panel 24 and connected to the signal line 46 inside the display panel 24. The reset circuits 26 and 28 are turned on when a reset signal R is supplied from a timing generation circuit (not shown) during a signal holding period at a predetermined cycle. When the reset circuits 26 and 28 are turned on, the display panel 24
The externally provided reset voltage generation source (not shown) and the signal line 46 conduct, and the potential of the signal line 46 is set to the reset potential (reference potential) Vrs.

As described above, since the initial potential V _SLO of the signal line 46 before the display signal D is written is set to the same reset potential Vrs by the reset circuits 26 and 28, the potential rise time Tr of each pixel TFT 16 is set. Becomes uniform. For this reason, the writing time of the display signal D becomes equal in all the pixel TFTs 16. In addition, the reset circuits 26 and 28 reset the potential of the signal line 46 to the reset potential Vrs, so that each pixel TFT 16
Are also equal. Therefore, in the liquid crystal display device 20, high quality liquid crystal display with uniform luminance is performed. In addition,
In FIG. 6, R _SL and C _SL indicate a resistance value and a capacitance of the signal line 46, respectively.

FIG. 7 is a basic configuration diagram of the liquid crystal display device 30. The principle of the present invention may be applied to a liquid crystal display device 30 having an analog switch 32 as shown in FIG.
The same components as those of the liquid crystal display devices 10 and 20 described above are denoted by the same reference numerals. In the liquid crystal display device 30, the common signal lines D1 to Dn are electrically connected to the pixel TFT 16 via the analog switch 32 which is turned on when the analog switch control signal A is supplied. At this time, the display signal D is supplied from the digital driver LSI 22 to the pixel TFT 16 in the ON state via the analog switch 32 in the ON state. Thus, in the liquid crystal display device 30,
By controlling the analog switch 32, the pixel TFT 16 to which the display signal D is given can be selected.

In the liquid crystal display device 30, the reset circuit 26 is connected to common signal lines D1 to Dn. Also,
The reset circuit 28 is connected to the signal line 46. When a reset signal R is supplied from a timing generation circuit (not shown) during the signal holding period, the reset circuit 26 sets the potentials of the common signal lines D1 to Dn to the reset potential Vrs. When the reset signal R is supplied from the timing generation circuit during the signal holding period, the reset circuit 28
The potential of No. 6 is set to the reset potential Vrs.

As described above, the common signal lines D1 to D1 before the display signal D is written by the reset circuits 26 and 28.
Since the initial potential V _SLO of Dn and the signal line 46 are the same reset potential Vrs, the rise time Tr of the potential in each pixel TFT 16 becomes uniform. Therefore, the writing time of the display signal D is equal to the time required for all the pixel TFTs 16
Becomes equal. Further, the reset circuits 26 and 28 reset the potentials of the common signal lines D1 to Dn and the signal line 46 to the reset potential Vrs.
Are also equal. Therefore, in the liquid crystal display device 30, high quality liquid crystal display with uniform luminance is performed. In addition,
In FIG. 7, R _SL and C _SL are each a common signal line D1.
To Dn, and R _L and C _L indicate the resistance value and the capacitance of the signal line 46, respectively.

The reset circuits 26, 2 shown in FIGS.
8 is configured as shown in FIGS. 8 and 9, for example. FIG. 8 is a diagram showing a configuration example of the NMOS reset circuits 26 and 28. FIG. 9 is a diagram showing a configuration example of the CMOS reset circuits 26 and 28. If the reset circuits 26 and 28 are of the NMOS type as shown in FIG. 8, the reset circuits 26 and 28 having a simple configuration can be realized. If the reset circuits 26 and 28 are of the CMOS type as shown in FIG.
Can be increased. In this case, the reset time of the signal line 46 can be reduced. The reset circuits 26 and 28 may be of a PMOS type. The reset circuits 26 and 28 are connected to a double gate N
It may be a MOS type or a CMOS type. In this case, the leak current of the pixel TFT 16 during the signal holding period can be further reduced.

The reset circuit 26 may be arranged in the digital driver LSI 22 for supplying the display signal D to the signal line 46. FIG. 10 is an equivalent circuit diagram of a reset signal output unit of the digital driver LSI 22 having a reset circuit 26 therein. As shown in FIG. 10, the digital driver LSI 22 includes an internal LSI circuit 34, a reset circuit 26, an OP amplifier 36, protection elements 38 and 39, and the like. A display signal D which is an output signal of the internal LSI circuit 34
Is a display panel 24 (not shown) via an OP amplifier 34.
Supplied to the side. When resetting the potential of the signal line 46,
A reset signal R is supplied to a reset circuit 26 from a timing generation circuit (not shown). As a result, the reset point 40 between the internal LSI circuit 34 and the OP amplifier 36 is set to the reset potential Vrs by the reset circuit 26.

Next, an embodiment of a liquid crystal display device to which the principle of the present invention is applied will be described. FIG. 11 is a configuration diagram of the liquid crystal display device 40 according to the first embodiment of the present invention. As shown in FIG. 11, the liquid crystal display device 40 includes a digital driver LSI 22, block control lines BL1 to BL
n, a display panel 24 and the like. The display panel 24
A display area 25, common signal lines D1 to Dn, a plurality of analog switches 32, a gate-side peripheral drive circuit 42, reset circuits 26 and 28, and the like are provided therein. In the liquid crystal display device 40, a display area 25 for performing liquid crystal display and peripheral circuits such as a gate side peripheral drive circuit 42 are integrally formed on the display panel 24, so that the size of the liquid crystal display device 40 is reduced. The above-described liquid crystal display devices 10, 20, 30
The same components as those described above are denoted by the same reference numerals.

The display area 25 includes n blocks B1 to B
The scanning lines 44 and the signal lines 46 are arranged in a matrix in each of the blocks B1 to Bn.
The pixel cell unit 14 is provided at each intersection of the scanning line 44 and the signal line 46. The pixel cell section 14 includes a pixel T
It comprises an FT 16, a liquid crystal C _LC , a storage capacitor Cs, and the like. The gate electrode of the pixel TFT 16 which is a p-Si TFT is connected to the scanning line 44, and the source electrode is the signal line 4.
6 and the drain electrode is a liquid crystal _CLC and a storage capacitor C
s.

A plurality of analog switches 32 are arranged for each of the blocks B1 to Bn. The common signal lines D1 to Dn are connected to signal lines 46 in the display panel 24 via analog switches 32 arranged corresponding to each block. In the display panel 24, the reset circuit 26 is connected to common signal lines D1 to Dn, and the reset circuit 28 is connected to a signal line 46. Note that the location of the reset circuits 26 and 28 is not limited to the location shown in FIG. For example, a digital driver L in which the reset circuit 26 is provided outside the display panel 24
You may connect to the display signal output part of SI22.

As shown in FIG. 11, the digital driver L
The SI 22 is connected to the common signal lines D1 to Dn.
When receiving a digital signal from an external data driver (not shown), the digital driver LSI 22 converts the digital signal into an analog signal and outputs a display signal D. The display signal D is transmitted from the digital driver LSI 22 to the display panel 24 via the common signal lines D1 to Dn for each block in a time-division manner. Note that the digital driver LSI 22 may be provided in the display panel 24.

The analog switch 32 is supplied with a block control signal BL for turning on the analog switch 32 via block control lines BL1 to BLn. When the liquid crystal display device 40 is driven, first, a scanning signal G is supplied to the scanning line 44 from the gate side peripheral driving circuit 42. Then, when the scanning signal G is input to the gate electrode of the pixel TFT 16, the pixel TFT 16 is turned on. On the other hand, the common signal line D1 is connected to the signal line 46 via the analog switch 32 turned on by the block control signal BL.
To Dn. Then, the liquid crystal display is performed by inputting the display signal D to the pixel TFT 16 in the ON state.

The potentials of the common signal lines D1 to Dn are reset to a reference potential Vrs by a reset circuit 26 at a predetermined cycle, and the potential of the signal line 46 is reset to a reference potential Vrs by a reset circuit 28 at a predetermined cycle. . Next, the operation of the liquid crystal display device 40 will be described with reference to FIGS. FIG. 12 is a timing chart of the display signal D, the scanning signal G, the block control signal BL, and the reset signal R provided to the liquid crystal display device 40.

As shown in FIG. 12, when a high-level scanning signal G is applied to the display area 25 from the gate-side peripheral driving circuit 42, first, the high-level block control signal BL is blocked for one block control period Tb. B1 is supplied to the analog switch 32 to turn on the analog switch 32. At this time, the block B1 in the display area 25
The display signal D is supplied from the digital driver LSI 22 via the common signal lines D1 to Dn for the time Tb.

When the display signal D is supplied to the block B1, a reset signal R is supplied to the reset circuit 26 from a timing generation circuit (not shown) provided outside the display panel 24. As a result, the reset circuit 26 operates to change the potentials of the common signal lines D1 to Dn to the reset potential Vrs.
(For example, Vcom). And then, time T
The block control signal BL at the high level by b
Block B2
Is turned on. At this time, the display signal D is applied to the block B2 from the digital driver LSI 22 via the common signal lines D1 to Dn for the time Tb. When the display signal D is given to the block B2, next, the reset signal R is supplied from the timing generation circuit to the reset circuit 26. As a result, the reset circuit 26 operates, and the potentials of the common signal lines D1 to Dn are set to the reset potential Vrs.

The above operation is repeated, and the display signal D is also supplied to the block Bn, and the common signal lines D1 to Dn
Is reset potential Vrs by the reset circuit 26.
Then, the blanking period Tbk starts. When the time Tb elapses after the start of the blanking period Tbk, the scanning signal G input to the display area 25 goes low. When the blanking period Tbk ends, the reset signal R is supplied to the reset circuit 28 from the timing generation circuit. As a result, the reset circuit 28
Operates, and the potential of the signal line 46 is set to the reset potential Vrs. Then, one horizontal scanning period Th ends. 1
When the horizontal scanning period Th ends, scanning of the next scanning line 44 is performed, and the display signal D is sequentially applied again from the block B1 to the block Bn.

Here, Ton and Toff shown in FIG.
Indicates the rise time and fall time of the scanning signal G, respectively. The blanking period Tbk is sufficiently longer than the block control period Tb, and Tbk> Tb + Ton
+ Toff. In the liquid crystal display device 40,
The block control signal BL may be provided to the analog switch 32 such that all the analog switches 32 of the blocks B1 to Bn are simultaneously turned on during one horizontal scanning period Th.

As described above, in the liquid crystal display device 40, block selection sequential driving is performed. As shown in FIG. 12, the writing time (block control period) Tb of the display signal D per block of the liquid crystal display device 40 that performs block selection sequential driving is Tb = (Th−Tbk) / n. Therefore, as the number n of blocks of the liquid crystal display device 40 decreases, the writing time Tb of the display signal D per block decreases.
Can be longer. When the writing time Tb per block becomes longer, the ratio of the fluctuation of the rising time Ton and the falling time Toff of the scanning signal G due to the variation in the characteristics of the pixel TFT 16 to the writing time Tb of the display signal D decreases. Become. Therefore, the write time Tb of the display signal D to each block is sufficiently ensured, and a display failure mode such as a laser scan stripe pattern and a vertical stripe pattern due to a variation in the write time Tb of the display signal D is prevented.

The reset circuit 26 resets the potentials of the common signal lines D1 to Dn to the reset potential V each time one block scan is completed.
rs, and the reset circuit 28 resets the potential of the signal line 46 to the reset potential Vrs each time one horizontal scan is completed.
r is unified, and the variation of the writing time of the display signal D due to the variation of the rising time Tr of the potential of the pixel TFT 16 is prevented. Further, since the potential of the signal line 46 is reset to the reset potential Vrs at a predetermined cycle, there is no difference between the off-state currents of the pixel TFTs 16 on the upper side and the lower side of the display panel 24.
High quality liquid crystal display with uniform brightness is performed.

In the liquid crystal display device 40, only one of the reset circuits 26 and 28 may be provided. Also, the reset signal R is supplied to the reset circuits 26 and 28.
Is not limited to the timing shown in FIG. 12, but may be any other timing within a range that satisfies the principle of the present invention. FIG. 13 is a timing chart showing the relationship between the block control signal BL, the reset signal R, and the signal line potential.

As shown in FIG. 13, for example, block B
1, the signal line 46 corresponding to the block B1
Becomes Vs. Then, immediately after the end of the control period of the block B1, the reset signal R is supplied to the reset circuit 26, and the potential of the signal line 46 corresponding to the block B1 is set to Vcom which is the reset potential (reference potential). Similarly,
Immediately after the end of the control period of the block B2, the reset signal R is supplied to the reset circuit 26, and the potential of the signal line 46 corresponding to the block B2 is the reset potential (reference potential) Vc.
om, and the reset signal R is supplied to the reset circuit 26 immediately after the end of the control period of the block Bn.
Is set to Vcom which is a reset potential (reference potential). Note that the reset potential Vr
s is not limited to Vcom but may be another value.

When the reset potential Vrs is Vcom, the potentials of the source electrodes of the pixel TFTs 16 arranged on the upper side and the lower side of the display panel 24 are both set to Vcom except during the writing period of the display signal D. At this time, since the off-state currents of the pixel TFTs 16 arranged on the upper and lower sides of the display panel 24 are substantially the same, the pixels TF on the upper and lower screens are
The execution voltage at T16 becomes substantially the same, and the display panel 24 is prevented from displaying a vertically inclined display.

In the liquid crystal display device 40, as shown in FIG. 14, the reset potential Vr is changed according to the change in the polarity of the display signal D.
The polarity of s may be changed. In FIG. 14, the display signal D
And the change in the polarity of the reset potential Vrs are the same. For example, the range of the potential of the display signal D is ± V
In the case of min to ± Vmax, the range of the reset potential Vrs is Vrs = ± Vmin.

FIGS. 15 and 16 show the reset potential Vr
FIG. 7 is a diagram illustrating a potential change of a display signal D when the polarity of s changes. FIG. 15 shows that the reset potential Vrs is Vrs = ±
5 shows a potential change of the display signal D when the voltage is Vmin. FIG. 16 shows that the reset potential Vrs is Vrs = ± 1/2.
The potential change of the display signal D when ΔVs is shown. FIG.
5 and FIG. 16, the reset potential Vrs is set to ± V
By setting to min or ± 1 / 2ΔVs, a time corresponding to a rise time from the potential Vcom at the time of writing the display signal D is reduced. Further, the common signal lines D1 to D
By resetting n and the signal line 46, the variation of the rise time Tr of the display signal D due to the variation in the characteristics of the analog switch 32 included in the liquid crystal display device 40 is prevented. Further, the reset potential Vrs is set to ± Vmin or ±
When 1 / 2ΔVs is applied, a preliminary bias is applied to the analog switch 32, so that the initial charging current flowing through the signal line 46 at the time of writing the display signal D increases, and the display signal D can be written to the pixel TFT 16 quickly. it can. As shown in FIG. 16, the reset potential Vrs is set to V
When rs = ± 1 / 2ΔVs, the rise time of the display signal D becomes almost constant regardless of the level of the display signal D.

FIGS. 17A and 17B are diagrams showing the polarity of the reset potential Vrs in the liquid crystal display device 40 in which the reset potential is field-inverted. As shown in FIG. 17A, in the positive field, all signal lines 46 in the display area 25 are set to the positive reset potential + Vrs. Also,
As shown in FIG. 17B, in the case of the negative field, all the signal lines 46 in the display area 25 are set to the negative reset potential -Vrs.
It is said. FIG. 18 is a timing chart of the display signal D, the reset signal R, and the reset potential Vrs in the liquid crystal display device 40 in which the reset potential is field-inverted.

FIGS. 19A and 19B show the reset potential V
FIG. 9 is a diagram illustrating the polarity of a reset potential Vrs in the liquid crystal display device 40 in which rs is inverted by an H / V line (dot). As shown in FIG. 19A, in the case of the positive field,
For example, the reset potential Vrs1 of the even signal line 46 is set to a positive reset potential + Vrs, and the reset potential Vrs2 of the odd signal line 46 is set to a negative reset potential -Vrs.
As shown in FIG. 19B, in the case of a negative field, the reset potential −Vrs1 of the even signal line 46 is set to the negative reset potential −Vrs, and the reset potential + Vrs2 of the odd signal line 46 is set to the positive reset potential. Vrs. The polarities of the reset potentials Vrs1 and Vrs2 change line by line depending on the field. FIG. 20 shows the reset potential Vr
A display signal D, a scanning signal G, and a reset signal R in the liquid crystal display device 40 in which s1 and Vrs2 are inverted by H / V lines.
FIG. 4 is a timing chart of reset potentials Vrs1 and Vrs2.

By the way, the principle of the present invention is not limited to the liquid crystal display device 40 of the block selection sequential drive, but is applied to the liquid crystal display device 50 of the dot sequential drive and the liquid crystal display devices 60 and 70 of the line sequential drive as described below. May be. FIG. 21 is a configuration diagram of a liquid crystal display device 50 according to a second embodiment of the present invention.
The liquid crystal display device 50 is driven dot-sequentially.

As shown in FIG. 21, the liquid crystal display 50
Are common signal lines D1 to Dn, p-Si TFT analog switch 32, gate side peripheral drive circuit 42, display area 2
5, a shift register circuit 52, a buffer circuit 54, and the like. The above-described liquid crystal display devices 10, 20, 30, 4
Components that are the same as 0 are denoted by the same reference numerals. The shift register circuit 52 and the buffer circuit 54 included in the liquid crystal display device 50 are circuits for generating an analog switch control signal A for controlling the analog switch 32. The shift register circuit 52 receives a start pulse SP and clock signals CL and / CL. Here, the operating frequency of the shift register circuit 52 is, for example, about 0.5 MHz.

A plurality of display areas 25 are arranged in a matrix.
The scanning lines 44 and the signal lines 46 are arranged. And run
At each intersection of the scanning line 44 and the signal line 46, the pixel cell unit 14
Is provided. The pixel cell section 14 includes a pixel TFT 16,
Liquid crystal C_LC, Storage capacity C_SAnd so on. Also, p-
The gate electrode of the pixel TFT 16 which is a SiTFT is a scanning line
44, the source electrode is connected to the signal line 46,
Drain electrode is liquid crystal C _LCConnected to the storage capacitor C
You. The common signal lines D1 to Dn connect the analog switch 32
It can be connected to the signal line 46 via the power line.

Shift register circuit 52 and buffer circuit 5
4, an analog switch control signal A for turning on the analog switch 32 is supplied. Liquid crystal display 5
At the time of driving of 0, first, a scanning signal G is supplied to the scanning line 44 from the gate side peripheral driving circuit 42. Then, when the scanning signal G is input to the gate electrode of the corresponding pixel TFT 16, the pixel TFT 16 is turned on. On the other hand, the display signal RGB is supplied to the signal line 46 from the common signal lines D1 to Dn via the analog switch 32 turned on by the analog switch control signal A. And
The display signal RGB is input to the pixel TFT 16 in the ON state, and color liquid crystal display is performed.

When a reset signal R is supplied from a timing generation circuit (not shown) at a predetermined cycle, the reset circuit 26 resets the potentials of the common signal lines D1 to Dn to the reset potential Vrs.
(For example, Vcom). The reset circuit 28 resets the potential of the signal line 46 to the reset potential Vrs when a reset signal R is supplied from the timing generation circuit at a predetermined cycle.

As described above, the reset circuit 26 resets the potential of the common signal lines D1 to Dn to the reset potential Vrs, and the reset circuit 28 resets the potential of the signal line 46 to the reset potential Vrs. The rising time Tr of the potential becomes uniform, and the variation of the writing time of the display signal D due to the variation of the rising time Tr of the potential of the pixel TFT 16 is prevented. Further, since the potential of the signal line 46 is reset to the reset potential Vrs in a predetermined cycle, there is no difference in the off current of the pixel TFT 16 included in the liquid crystal display device 50. Therefore, in the liquid crystal display device 50, the luminance is uniform and high. Quality liquid crystal display is performed.

FIG. 22 is a configuration diagram of a liquid crystal display device 60 according to a third embodiment of the present invention. The liquid crystal display device 60 is driven line-sequentially. As shown in FIG. 22, the liquid crystal display device 6
0 denotes a digital driver LSI 22, a display area 25, reset circuits 26 and 28, a gate side peripheral drive circuit 42, O
It has a P amplifier 62 and the like. The above-described liquid crystal display device 1
The same components as 0, 20, 30, 40, and 50 are denoted by the same reference numerals.

The reset circuit 26 includes a digital driver L
It is provided on a signal line 46 between the SI 22 and the OP amplifier 62. When driving the liquid crystal display device 60, first, the scanning signal G is supplied to the scanning line 44 from the gate side peripheral driving circuit 42. Then, the p-SiT corresponding to the scanning signal G
The pixel TFT 16 is turned on by inputting to the gate electrode of the pixel TFT 16 which is FT. On the other hand, signal line 4
6 is supplied with a display signal D from the digital driver LSI 22. Then, the pixel TF whose display signal D is in the ON state
Input to T16, liquid crystal display is performed.

When a reset signal R is supplied from a timing generation circuit (not shown) at a predetermined cycle, the reset circuit 26 changes the potential of the signal line 46 between the digital driver LSI 22 and the OP amplifier 62 to a reset potential Vrs (for example,
Vcom). Also, the reset circuit 28
Resets the potential of the signal line 46 to the reset potential Vrs when a reset signal R is supplied from a timing generation circuit (not shown) at a predetermined cycle.

As described above, since the reset circuits 26 and 28 reset the potential of the signal line 46 to the reset potential Vrs, the rise time Tr of the potential of each pixel TFT 16 becomes uniform, and the rise time T of the potential of the pixel TFT 16 becomes uniform.
The variation in the writing time of the display signal D due to the variation in r is prevented. Further, since the potential of the signal line 46 is reset to the reset potential Vrs at a predetermined cycle, there is no difference in the off current of the pixel TFT 16 included in the liquid crystal display device 60. Therefore, in the liquid crystal display device 60, the luminance is uniform and high. Quality liquid crystal display is performed.

In the liquid crystal display device 60, the analog switch 32 may be used instead of the OP amplifier 62. FIG. 23 is a configuration diagram of a liquid crystal display device 70 according to a fourth embodiment of the present invention. The liquid crystal display device 70 is driven line-sequentially. As shown in FIG. 23, the liquid crystal display device 70 includes a digital driver LSI 72, a display area 25, a reset circuit 28, a gate driver LSI 74, and the like. The above-described liquid crystal display devices 10, 20, 30, 40, 5
The same components as 0 and 60 are denoted by the same reference numerals.

When the liquid crystal display device 70 is driven, first, the scanning signal G is applied to the scanning line 44 from the gate driver LSI 74.
Is given. Then, the scanning signal G corresponds to the corresponding a-Si
The pixel TFT 16 is turned on by input to the gate electrode of the pixel TFT 16 which is a TFT. On the other hand, the signal line 46 is connected to the display signal D from the digital driver LSI 72.
Is given. Then, the pixel T whose display signal D is in the ON state
Input to the FT 16 for liquid crystal display.

The reset circuit 28 changes the potential of the signal line 46 to a reset potential Vrs (for example,
Vcom). As described above, since the reset circuit 28 resets the potential of the signal line 46 to the reset potential Vrs, the rise time Tr of the potential of each pixel TFT 16 becomes uniform, and the rise time Tr of the potential of the pixel TFT 16 is varied. The variation in the write time of the display signal D is prevented. Further, the signal line 4
6 is reset to the reset potential Vrs at a predetermined cycle, so that the pixel T
Since there is no difference in the off-state current of the FT 16, the liquid crystal display device 70 performs high-quality liquid crystal display with uniform luminance.

The reset circuit 26 of the liquid crystal display device 40 is connected to the digital driver LSI 72, and the potential of the signal line 46 is reset at a predetermined cycle to the reset potential Vr.
It may be configured to reset to s. The number of the digital driver LSI 72 and the gate-side driver LSI 74 is appropriately determined according to the number of the scanning lines 44 and the signal lines 46 in the liquid crystal display device 70 and the driving capabilities of the digital driver LSI 72 and the gate-side driver LSI 74. And

In the above embodiment, the digital driver L
The SI 22 corresponds to the driver and data driver LSI described in the claims. Further, the reset circuit 28 corresponds to first and third reset circuits described in claims, and the reset circuit 26 corresponds to second and fourth reset circuits described in claims. Further, the reset potential Vrs corresponds to a predetermined potential described in the claims.

[0065]

As described above, according to the first to twelfth aspects of the present invention, the reset circuit resets the potential of the signal line or the like to a predetermined potential at a predetermined cycle. For this reason, the rise time of the potential of the pixel cell at the time of writing the display signal becomes uniform, and the writing time of the display signal becomes equal in all the pixel cells. Further, since the potential of the signal line or the like is reset to a predetermined potential at a predetermined cycle, the off current in each pixel cell during the signal holding period becomes equal. Therefore, a high-quality liquid crystal display with uniform luminance on the display panel is realized.

[Brief description of the drawings]

FIG. 1 is a basic configuration diagram of a conventional liquid crystal display device.

FIG. 2 is a diagram illustrating waveforms of a scanning signal and a display signal supplied to a pixel cell unit.

FIG. 3 is a diagram showing waveforms of a scanning signal and a display signal supplied to a pixel cell unit.

FIG. 4 is a diagram showing a relationship between a drain current of a pixel TFT and a voltage of a gate electrode.

FIG. 5 is a diagram illustrating a relationship between an initial potential of a signal line portion and a rise time of a pixel potential.

FIG. 6 is a basic configuration diagram of a liquid crystal display device for explaining the principle of the present invention.

FIG. 7 is a basic configuration diagram of a liquid crystal display device of the present invention including an analog switch.

FIG. 8 is a configuration diagram of an NMOS reset circuit.

FIG. 9 is a configuration diagram of a CMOS reset circuit.

FIG. 10 is an equivalent circuit diagram of a reset signal output unit of a digital driver LSI having a reset circuit therein.

FIG. 11 is a configuration diagram of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 12 is a timing chart of a display signal, a scanning signal, a block control signal, and a reset signal provided to the liquid crystal display device of the present invention.

FIG. 13 is a diagram showing a relationship among a block control signal, a reset signal, and a signal line potential.

FIG. 14 is a diagram showing a change in polarity of a reset potential.

FIG. 15 is a diagram showing a potential change of a display signal.

FIG. 16 is a diagram showing a potential change of a display signal when a reset potential is ± 1 / 2ΔVs.

FIG. 17 is a diagram showing the polarity of a reset potential in a field-inverted liquid crystal display device.

FIG. 18 is a timing chart of a display signal, a reset signal, and a reset potential in a liquid crystal display device that is field-inverted.

FIG. 19 is a diagram showing the polarity of a reset potential in a liquid crystal display device in which H / V lines are inverted.

FIG. 20 is a timing chart of a display signal, a reset signal, and a reset potential in a liquid crystal display device in which H / V lines are inverted.

FIG. 21 is a configuration diagram of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 22 is a configuration diagram of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 23 is a configuration diagram of a liquid crystal display device according to a fourth embodiment of the present invention.

[Explanation of symbols]

10, 20, 30, 40, 50, 60, 70 Liquid crystal display device 12 Signal line unit 14 Pixel cell unit 16 Pixel TFT 18 Input unit 22 Digital driver LSI 24 Display panel 25 Display area 26, 28 Reset circuit 32 Analog switch 34 Inside LSI circuits 36, 62 OP amplifiers 38, 39 Protective element 42 Gate side peripheral drive circuit 44 Scan line 46 Signal line 52 Shift register circuit 54 Buffer circuit 72 Digital driver LSI 74 Gate side driver LSI D1 to Dn Common signal lines B1 to Bn Block BL1 to BLn Block control line

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 2H093 NA16 NA34 NA80 NC13 NC16 NC25 NC26 NC34 NC90 ND05 ND09 ND15 ND36 ND37 ND52 NF05 5C006 AC11 AF42 AF50 AF71 AF73 BB16 BC03 BC06 BC12 BC20 BF03 BF25 EB05 FA22 FA255080A AA10 BB05 DD05 EE28 FF11 JJ02 JJ04 JJ05

Claims (12)

[Claims] 1. A pixel cell arranged in a matrix in a display panel, a plurality of signal lines and scanning lines connected to the pixel cell, a driver for applying a display signal to the signal line, and at a predetermined cycle. A reset circuit for resetting the potential of the signal line to a predetermined potential. 2. A pixel cell arranged in a matrix in a display panel, a plurality of signal lines and scanning lines connected to the pixel cell, an analog switch connected to the signal line, and a common signal line. Connected to the analog switch via
A liquid crystal display device comprising: a driver that supplies a display signal to the signal line via an on-state analog switch; and a reset circuit that resets the potential of the signal line to a predetermined potential at a predetermined cycle. 3. The liquid crystal display device according to claim 1, wherein the reset circuit is connected to the signal line. 4. The liquid crystal display device according to claim 1, wherein said reset circuit is connected to an output section of said driver. 5. The liquid crystal display device according to claim 1, wherein the reset circuit includes a first reset circuit connected to the signal line, and a second reset circuit connected to an output unit of the driver. A liquid crystal display device comprising: 6. The liquid crystal display device according to claim 2, wherein
The liquid crystal display device, wherein the reset circuit is connected to the common signal line. 7. The liquid crystal display device according to claim 2, wherein
The reset circuit includes a third reset circuit connected to the signal line, and a fourth reset circuit connected to one of the output section of the driver and the common signal line. Liquid crystal display. 8. The liquid crystal display device according to claim 1, wherein the reset circuit sets the potential of the signal line to the predetermined level by receiving a reset signal during a blanking period of one horizontal scan. A liquid crystal display device resetting to a potential of 9. A pixel cell arranged in a matrix in a display panel divided into a plurality of blocks, a plurality of signal lines and scanning lines connected to the pixel cell, and an analog connected to the signal line A switch, connected to the analog switch via a common signal line,
A liquid crystal display comprising: a driver that supplies a display signal to a signal line in a block sequentially activated by a block control signal; and a reset circuit that resets the potential of the signal line to a predetermined potential at a predetermined cycle. apparatus. 10. The liquid crystal display device according to claim 9, wherein the reset circuit changes the potential of the signal line to the predetermined potential by applying a reset signal every blanking period of one block scan or one horizontal scan. A liquid crystal display device characterized in that: 11. The liquid crystal display device according to claim 1, wherein the polarity of the predetermined potential is inverted in synchronization with the display signal that is an AC signal. . 12. An internal LSI circuit for generating a display signal,
A data driver LS for driving a liquid crystal display panel, comprising: an OP amplifier; and a reset circuit for resetting a potential of an output portion of a display signal to the outside to a predetermined potential.
I.