JPH07199156A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To obtain a liquid crystal display device in which holding can be performed regardless of the length of a holding time and a holding potential is not varied by potential variation of a scanning line by providing one digital storage circuit for one pixel and connecting pixel electrodes to the output terminals. CONSTITUTION:Data of signal lines 106, 107 are fetched in digital storage circuits 117-120 arranged near each pixel electrode by signals of scanning lines 104, 105. This storage state is held until next signals of scanning lines 104, 105 are applied. Since outputs of the storage circuits 117-120 are connected directly to a pixel electrode, a potential of a pixel electrode is fixed to a potential of either of a high potential side or a low potential side of a power supply potential of the storage circuits 117-120. Also, in this embodiment, the device is constituted so that a power supply potentials of the digital storage circuits 117-120 are driven with the same amplitude and a specified frequency (vertical synchronizing frequency, etc.) and voltage applied to liquid crystal is made 0 on average.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device, and more particularly to a digital gray scale display liquid crystal display device.

[0002]

2. Description of the Related Art As a conventional digital gray scale active matrix type liquid crystal display device, the one described in "Flat Panel Display 91 pages 173 to 180" by Nikkei BP is standard.

FIG. 2 shows an example of a conventional liquid crystal display device.
The active matrix type liquid crystal display device can be roughly divided into three parts: a pixel matrix part, a signal line driving circuit, and a scanning line driving circuit. The operation will be described below with reference to the drawings.

In the pixel matrix, signal lines and scanning lines are arranged in a matrix form, and pixel TFTs are arranged at the intersections thereof.
The pixel TFT has a gate connected to the scanning line, a source connected to the signal line, and a drain connected to the pixel electrode. Further, in general, the liquid crystal capacitance between the pixel electrode and the counter electrode cannot have a large value, so that a storage capacitor for holding charges is arranged near the pixel electrode. When a voltage exceeding the threshold voltage of the TFT is applied to the scanning line and the TFT turns on, TF
The drain and source of T are short-circuited, the voltage of the signal line is applied to the pixel electrode, and the liquid crystal and the storage capacitor are charged. When the TFT turns off, the drain becomes open,
The charges stored in the liquid crystal and the storage capacitor are held until the TFT is turned on next time.

FIG. 3 shows an example of a 4-tone signal line drive circuit. Here, the case of four gradations will be described, but the basic operation is the same even when the number of gradations is different. Digital gradation signals are input from the input terminals 302 and 303 to the shift registers 310 and 31.
Input to 1. The outputs of the shift registers 310 and 311 are input to the shift registers 312 and 313 and the latch circuits 314 and 315 in the next stage, and the latch circuits hold data for a certain period. This holding period is determined by the horizontal synchronizing signal input to the input terminal 304. The output signal of the latch circuit is input to the decoder 316, and the 2-bit digital signal is converted into four voltage selection signals by this decoder. One of the switch transistors 317 to 320 is selected by this voltage selection signal, and the potential of one of the grayscale voltage lines 305 to 308 is transmitted to the signal line 9.

FIG. 4 shows an example of the scanning line driving circuit. The scanning line driving circuit is composed of a shift register, a NAND circuit, and an inverter type buffer, inputs a start pulse synchronized with a vertical synchronizing signal and a clock synchronized with a horizontal synchronizing signal, and sequentially drives the scanning lines.

[0007]

The above-mentioned conventional liquid crystal display device has the following two problems. The first problem is that when the TFT is in the off state, a leak current flows between the drain and the source, the charge of the pixel is discharged, and the potential changes. General N channel TF
The drain current and gate voltage characteristics of T are shown in FIG. As can be seen from FIG. 5, even when the gate voltage is negative, a current flow is flowing in the drain. This current causes discharge of electric charge. Although the explanation has been made with the N-channel TFT, the same applies to the P-channel TFT.

Since the writing cycle of a pixel is usually 100 Hz or less, the holding time is 10 msec or more. In order to take the holding time as long as possible, it is general to attach the holding capacitor 241 in parallel with the liquid crystal, but the total amount of the liquid crystal and the holding capacitor is only 0.1 pF to 0.2 pF. Pixel holding time is 16.6 msec (60 Hz), voltage applied to liquid crystal is 5 V, holding ratio is 99%, capacitance is 0.2 pF
Then, the allowable TFT leakage current is 5 × (1-0.99) × 0.2 pF / 16.6 msec.
= 0.6 pA, and it is difficult to realize this value in consideration of the operating temperature range and the variation of the TFT. Therefore, the electric charge of the pixel is discharged and the image quality is deteriorated.

The second problem is that, in the operation of the TFT, when the scanning line potential changes from a high potential to a low potential or from a low potential to a high potential, the drain potential is reduced by the capacitance between the gate and drain of the TFT. That is, it is drawn in the direction in which the scanning line potential changes by ΔV shown in FIG. ΔV = V × Cgd / (Cgd + Clc + Cstg) where V is the fluctuation range of the scanning line potential Cgd is the capacitance value between the gate and drain of the TFT, Clc is the capacitance value of the liquid crystal, Cstg is the capacitance value of the storage capacitance, and As shown in the figure, the potential of the pixel electrode is shifted downward from the center, which causes deterioration of the liquid crystal.

The liquid crystal display device of the present invention solves these two problems, and the purpose thereof is to enable holding regardless of the length of the holding time, and to scan lines. An object of the present invention is to provide a liquid crystal display device in which the holding potential does not change due to the potential change.

[0011]

In the liquid crystal display device of the present invention, the gray scale display system is a time gray scale system, the voltage applied to the pixel is only binary, and one pixel is
It has one digital memory circuit, and its output is connected to the pixel electrode.

[0012]

In the present invention, the potential of the signal line is taken into the digital memory circuit by the signal of the scanning line, and the potential is held for a certain period. Since the pixel electrode is connected to the output of the digital storage circuit, the high potential or the low potential of the digital storage circuit is applied as long as the storage circuit is in the holding state.

[0013]

EXAMPLE FIG. 1 shows an example of the present invention. In the time gradation method, as shown in FIG. 7, black and white are switched temporally to produce a halftone. The operation of the signal line drive circuit of this embodiment will be described. The time-modulated digital gradation signal is input to the shift register 109 from the input terminal 102, the output of the shift register 109 is input to the shift register 110 and the latch circuit 111 in the next stage, and the latch circuit 111 stores the data for a certain period. Hold. This holding period is determined by the horizontal synchronizing signal input to the input terminal 103. The outputs of the latch circuits 111 and 112 are inverter type buffer circuits 113, 114, 115 and 11
It is output to the signal lines 106 and 107 via 6. The data of the signal line is the digital storage circuits 117, 118, 119, 12 arranged in the vicinity of each pixel electrode according to the scanning line signal.
It is included in 0. This storage state is held until the next scanning line signal comes. FIG. 8 shows an example of a pixel area and a digital storage circuit. This digital memory circuit is TFT80
7, 808 and TFTs 809, 810 are combined in two, and when the TFT 806 is turned on, the memory circuit and the signal line are short-circuited and data is taken in.

Since the output of the memory circuit is directly connected to the pixel electrode, the potential of the pixel electrode is fixed to either the high potential side or the low potential side of the power source potential of the memory circuit. As described above, the potential of the pixel is not stored in the capacitor like the conventional example and is held by the data of the memory circuit, instead of holding the potential. It does not occur and the improvement of image quality is expected.

Further, since the liquid crystal element deteriorates when a DC voltage is applied for a long period of time, in this embodiment, the counter electrode has the same amplitude as the output amplitude of the digital memory circuit and at a specific frequency (vertical synchronizing frequency or the like). Driving is performed so that the voltage applied to the liquid crystal becomes 0 on average. This relationship is shown in FIG.

FIG. 9 shows a second example of the memory circuit. TF
An inverter is constituted by T908 and 910 and resistors 907 and 909, and a memory circuit is constituted. In this example, the operation is the same as that of the above-described embodiments, but it is possible to use only one type of polarity of the TFT in the pixel matrix.

[0017]

As described above, according to the present invention, the gray scale display system is the time gray scale display system, and a potential can be given to one pixel electrode by one digital storage device. There is an effect that the electric potential of the electrodes can be made constant, and there is an effect that the image quality is improved thereby.

[Brief description of drawings]

FIG. 1 shows an embodiment of a signal line drive circuit of a liquid crystal display device of the present invention.

FIG. 2 shows a block diagram of an active matrix liquid crystal display device.

FIG. 3 shows an example of a conventional signal line drive circuit.

FIG. 4 illustrates an example of a scan line driver circuit.

FIG. 5 shows drain current and gate voltage characteristics of a TFT.

FIG. 6 shows pixel retention characteristics.

FIG. 7 shows a time gradation operation.

FIG. 8 shows an embodiment of a pixel and digital storage circuit.

FIG. 9 illustrates an embodiment of a pixel and digital storage circuit.

FIG. 10 shows counter electrode and liquid crystal voltage characteristics.

[Explanation of symbols]

Clock input terminal: 101 Start pulse input terminal: 102 Horizontal synchronization signal input terminal: 103 Scan line: 104, 10
5 Signal line: 106, 10
7 Counter electrode connection terminal: 108 Shift register: 109, 11
0 Latch circuit: 111, 11
2 Inverter type buffer: 113-11
6 Digital memory circuit: 117-12
0 liquid crystal: 121 to 12
4 pixel matrix: 200 signal line: 201 to 20
3 scanning lines: 204 to 20
6 TFT: 207-21
0 liquid crystal: 211-21
4 Storage capacity: 215-21
8 Clock input terminal: 301 Start pulse input terminal: 302, 30
3 Horizontal sync signal input terminal: 304 Gradation voltage terminal: 305-30
8 signal line connection terminal: 309 shift register: 310-31
3 Latch circuit: 314, 31
5 Decoder: 316 TFT: 317-32
0 clock input terminal: 401 start pulse input terminal: 402 NAND: 403, 40
4 Inverter type buffer: 405, 40
6 Scan line connection terminals: 407, 40
8 scanning line: 801 signal line: 802 storage circuit power supply terminal: 803, 80
4 Counter electrode terminal: 805 TFT: 806-81
0 liquid crystal: 811 scanning line: 901 signal line: 902 storage circuit power supply terminal: 903, 90
4 counter electrode terminal: 905 TFT: 906, 90
8,910 Liquid crystal: 911 Resistor: 907, 90
9

Claims (1)

[Claims] 1. A substrate having a first insulating surface, provided with pixel electrodes and signal lines and scanning lines arranged in a matrix, and a substrate having a second insulating surface, provided with counter electrodes, wherein: In a time gray scale type liquid crystal display device having a liquid crystal between the substrate and the second substrate, each pixel electrode is provided with a digital storage circuit which is composed of a thin film transistor and whose output is connected to the pixel electrode. Has, and
A liquid crystal display device, wherein the counter electrode is AC-driven with an amplitude equivalent to an output logic amplitude of the digital storage circuit.