JP2000276369A - Bus bridge circuit, asic and electronic equipment - Google Patents

Abstract

[PROBLEMS] To provide a bus bridge circuit, an ASIC, and an electronic device having a diagnosis processing function capable of efficiently specifying a failure point. [MEANS FOR SOLVING PROBLEMS] A CPU 20 sends an I / O register 13 for diagnosis. , The data holding register 60 traps and holds the first data from the CPU 20. CPU 20 checks I / O register 1
If the reading process from the third data is executed twice consecutively, the first data from the data holding register 60 and the second data from the I / O register 13 are continuously output to the CPU 20. The CPU 20 compares the write data with the first and second data, and determines which of BUS1 and BUS2 has a failed portion. The write address at the time of writing is held and compared with the read address at the time of reading. A flag register is provided for storing a diagnostic mode flag that is turned on at the time of reset and turned off at the end of the diagnostic processing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus bridge circuit, an ASIC, and an electronic device.

[0002]

2. Description of the Related Art CPU
In an ASIC (microcomputer or the like) incorporating a (processor in a broad sense) or an electronic device incorporating the ASIC, a diagnosis process (self-diagnosis process) for examining the contents of a failure in its own system and the location where the failure occurred. Is required. In this diagnosis processing, how to efficiently identify the content and location of the failure is an important technical problem.

In particular, in the ASIC, a bus to which high-performance devices such as a CPU and a high-speed memory are connected, and a bus to which relatively low-performance I / O devices such as a timer, a PIO, and a UART are connected. Many have two buses. These buses are usually connected via what is called a bus bridge circuit.

[0004] However, in the conventional diagnostic processing method, efficient diagnostic processing in such an ASIC having two buses cannot be realized.

For example, Japanese Patent Application Laid-Open No. 2-148228,
No. 148229 discloses a conventional technique in which a buffer circuit and a bus connection circuit are interposed in parallel between the first and second buses.

However, according to this conventional technique, when data is written to a buffer circuit, for example, the diagnostic processing program itself must perform various processes required for data writing, such as specifying an address of the buffer circuit. Did not. Further, when connecting or disconnecting a bus, the diagnostic processing program itself has to specify the address of the bus connection circuit and control the bus connection processing and the bus disconnection processing. For this reason, there is a problem that the processing load of the diagnostic processing program becomes excessive.

Further, according to the above-mentioned prior art, the buffer circuit and the bus connection circuit are connected in parallel between the first and second buses, and data can be written to the buffer circuit from the second bus side. Therefore, there have been problems such as complicated and complicated routing of wiring and an increase in circuit scale.

The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a bus bridge circuit having a diagnostic processing function capable of efficiently identifying a failure point, and the bus bridge circuit. An object is to provide an ASIC using a circuit and an electronic device using the ASIC.

[0009]

According to the present invention, there is provided a bus bridge provided between a first bus and a second bus to which an input / output device is connected and having a diagnostic processing function. A circuit for trapping first data output from the processor to the input / output device via the first bus when the processor executes a write process to the input / output device for diagnosis. A data holding register to be held and a first data read from the data holding register when a processor executes a reading process from the input / output device to check whether the writing process is properly performed. A circuit that outputs data and second data read from the input / output device via the second bus to a processor. That.

According to the present invention, when the processor executes a write process to an input / output device (particularly, an input / output register of the input / output device) for diagnosis, first data from the processor is transmitted to the input / output device. It is output and held in the data holding register. When the processor executes one or more reading processes from the input / output device for confirmation, the first data from the data holding register and the second data from the input / output device are transmitted to the processor. Is output.

Therefore, according to the present invention, the processor comprises:
By comparing the write data (a specific bit of the write data may be changed) or the like with the read first and second data, a failure point is found in any of the first and second buses. It is possible to easily determine whether or not there is. As a result, the burden on the diagnostic processing can be reduced, and the diagnostic processing program can be simplified, downsized, and the like.

Further, according to the present invention, when the processor executes the read processing twice in succession, the first data from the data holding register and the second data from the input / output device are successively forward and backward. And output to the processor. With this configuration, the processor can continuously read the first and second data only by executing the reading process twice consecutively, thereby simplifying the processing of the processor and reducing the processing load. It can be reduced.

The present invention also provides an address holding register for holding a write address when a processor executes a write process to the input / output device, and an address holding register for holding a write address when the processor executes a read process from the input / output device. And an address comparator for comparing the read address with the write address held in the address holding register. This prevents the first data from the data holding register from being output to the processor even though the write address in the write process is different from the read address in the read process. it can.

Further, the present invention includes a flag register for storing a diagnostic mode flag which is set to ON at the time of resetting and is set to OFF at the end of diagnostic processing, wherein the diagnostic mode is set when the diagnostic mode flag is set to ON. The circuit operation in the mode is performed, and when the diagnostic mode flag is set to off, the circuit operation in the normal mode is performed without performing the circuit operation in the diagnostic mode. With this configuration, at the time of reset, the mode automatically shifts to the diagnostic mode, and the circuit operation in the diagnostic mode is automatically performed. Further, simply turning off the diagnostic mode flag automatically shifts to the normal mode, so that the circuit operation in the diagnostic mode is not performed. Therefore, switching between the diagnostic mode and the normal mode can be controlled with a small processing load.

An ASIC according to the present invention includes any one of the bus bridge circuits described above, the first and second buses connected to the bus bridge circuit, the processor for executing instructions, and the processor. The input / output device connected to a second bus, and diagnostic processing means for executing a process of writing to the input / output device and a process of reading from the input / output device by a function of the processor. . This makes it possible to improve the reliability of the ASIC and reduce the processing load in the diagnostic mode.

Further, the present invention is characterized in that the diagnostic processing means executes a series of diagnostic processing in which the writing processing and the two reading processings are a set. This makes it possible to simplify and downsize the diagnostic processing program used in the ASIC.

Further, the electronic apparatus according to the present invention is characterized by including input means for inputting data, and output means for outputting at least one of an image and a sound under the control of the ASIC. By doing so, the reliability of the electronic device can be improved and the cost can be reduced.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

1. 1. Bus Bridge Circuit FIG. 1 shows a block diagram of a bus bridge circuit 10 of the present embodiment and its periphery.

The bus bridge circuit 10 of the present embodiment
It is provided between US1 (first bus) and BUS2 (second bus), and has a function of connecting these BUS1 and BUS2.

Here, BUS1 is AB1 (first address bus), BC1 (first bus control line), DB1 (first bus).
Data bus). As the BUS1, a bus called a system bus can be considered.
Includes high-performance devices such as the CPU 20 and the high-speed memory 30 (devices that are required to perform high-speed processing)
Is connected. In BUS1, bus control using BC1 is also complicated.

BUS2 includes AB2 (second address bus), BC2 (second bus control line), and DB2 (second data bus). As the BUS2, a bus called a peripheral bus can be considered.
I / O devices (peripheral devices) 12, 14, and 16 having lower performance than the memory 20 and the memory 30 are connected.
In BUS1, bus control using BC2 is also BUS2
It is simpler than.

A CPU (processor in a broad sense) 20 connected to the BUS 1 executes various instructions for execution, and has a diagnosis processing unit 22. This diagnostic processing unit 22
It is software means operated by the function (hardware) of the CPU 20 and the diagnostic processing program 32 stored in the memory 30.

I / O device 1 connected to BUS 2
Examples of 2, 14, 16 include a timer, a PIO, and a UA
RT and the like, each I / O device 12,
14, 16 are at least one I / O register 13,
15 and 17. Such an I / O register 13,
As 15 and 17, a status register, a control register, a transmission data register, a reception data register, and the like can be considered.

The bus bridge circuit 10 of the present embodiment includes a data holding register 60. Here, when the CPU 20 (diagnosis processing unit 22) executes, for example, a write process to the I / O register 13 (I / O device 12 in a broad sense), the data holding register 60 transmits the BU from the CPU 20.
It has a function of trapping and holding first data (diagnostic data) output to the I / O register 13 via S1. After executing the writing process to the I / O register 13, the CPU 20 executes the reading process from the I / O register 13 to check whether the writing process is properly performed. In this case, the bus bridge circuit 10
Outputs the first data read from the data holding register 60 and the second data read from the I / O register 13 via the BUS2 to the CPU 20.

More specifically, the bus bridge circuit 10 of the present embodiment operates as shown in FIGS. 2 (A), 2 (B) and 2 (C).

That is, when the CPU 20 executes the writing process to the I / O register 13, the first data from the CPU 20 is written and held in the data holding register 60 as indicated by E1 in FIG. You. The first data is written to the I / O register 13 as indicated by E2.

Next, when the CPU 20 executes the reading process from the I / O register 13, in the first reading process, the first data held in the data holding register 60 as indicated by E3 in FIG. Is output to the CPU 20. Also, in the second read processing, FIG.
As shown in E4, the second data from the I / O register 13 is output to the CPU 20.

In FIGS. 2A, 2B and 2C, C
When the PU 20 executes the read processing twice consecutively, the first data is output from the data holding register 60 to the CPU 20 and then the second data is output from the I / O register 12. . However, conversely, the first data may be output after the second data is output.

CPU 2 that has read the first and second data
0 confirms whether there is an error in the first and second data. That is, the CPU 20 holds data to be written to the I / O register in a built-in general-purpose register or the like. Then, the held write data is compared with the read first and second data. If they match, it is determined that there is no error, and if they do not match, it is determined that there is an error.

However, depending on the type of the I / O register,
In some cases, specific bits are inverted from 1 to 0 or from 0 to 1 by writing data to the I / O register (in this case, the first data and the second data are inverted even when there is no error).
Will be different from the data of Therefore, in such a case, the bits of the write data held in the general-purpose register are also inverted.

If there is an error in the first data, the CPU 20 (diagnosis processing unit 22) sets BUS1 (or its vicinity).
It is determined that there is an abnormal part in. The first data is shown in FIG.
(A) As shown at E1, the CPU 20
Is written into the data holding register 60 from FIG.
This is because the data is read from the data holding register 60 to the CPU 20 via the BUS1 as indicated by E3.

On the other hand, if there is no error in the first data and there is an error in the second data,
It is determined that there is an abnormal part (or its vicinity). Second
The data of BU as shown in E1 and E2 in FIG.
The data is written from the CPU 20 to the I / O register 13 through S1 and BUS2, and the BU is written as shown at E4 in FIG.
CPU from I / O register 13 via S1, BUS2
This is because the data has been read out to 20.

As described above, according to the present embodiment, the BUS
CPU2 determines which of BUS2 has a faulty location.
0 can be easily determined. Therefore, it is easy to specify the failure location, and the efficiency of the diagnostic processing can be greatly improved.

Further, according to the present embodiment, the CPU 20
Can greatly reduce the burden of the diagnostic processing.

That is, JP-A-2-148228, 2-14
In the conventional technology of 8229, the diagnostic processing program itself
Processing such as specification of the address of the buffer circuit must be performed. Further, the diagnostic processing program itself has to specify the address of the bus connection circuit and control the bus connection processing and the bus disconnection processing. Therefore, the processing load on the CPU becomes extremely heavy, and the description of the diagnostic processing program is complicated, and the program is enlarged.

On the other hand, according to the present embodiment, the CPU
The diagnostic processing unit 20 (diagnosis processing unit 22) may simply execute the processing of writing to the I / O register 13 and the processing of reading twice from the I / O register 13. Therefore, the processing load on the CPU 20 can be greatly reduced as compared with the related art. In addition, the description of the diagnostic processing program 32 is simplified, so that the program can be made compact, the occurrence of bugs can be reduced, the development period of the program can be shortened, and the memory capacity for storing the program can be reduced.

Note that the CPU 20 operates in the I / O register 13
Is completed, the diagnosis of the I / O register 15 is performed next, the diagnosis of the I / O register 17 is performed next, and so on of all the I / O registers connected to the BUS2. A diagnosis will be made.

The I / O register at the time of writing data and the I / O register at the time of reading data do not necessarily have to match. For example, consider a case where the I / O device has a transmission data register, a reception data register, and a self-loop connecting the transmission data register and the reception data register. In this case, data is written to the transmission data register at the time of the writing process, and data (data transmitted from the transmission data register to the reception data register via the self-loop) is read at the time of the reading process. The I / O register at the time does not match the I / O register at the time of reading.

FIG. 3 shows a detailed configuration example of the bus bridge circuit 10.

The bus bridge circuit 10 shown in FIG. 3 includes a buffer 33, a tristate buffer 34, an address holding register 36, an address comparator 38, a control signal converter 40,
Access monitoring / operation control unit 42, flag register 44,
Tri-state buffers 46, 48, 50, 52, 54
Including.

Here, as shown in FIG. 2A, the CPU 20 stores the address holding register 36 in the I / O register 13 (I
When a write process to the / O device 12) is executed, the write address is held. The holding of the write address in this address holding register is as follows.
Latch signal LT1 from access monitoring / operation control unit 42
It is performed based on. Also, the address comparator 38 is provided in FIG.
When the CPU 20 executes a read process as shown in (B) and (C), the read address is compared with the write address held in the address holding register 36. Then, the address comparator 38 notifies the access monitoring / operation control unit 42 of the coincidence or non-coincidence between the read address and the write address using the signal CQ.

The control signal conversion section 40 receives the first signal from the BC 1
Is performed to convert the second bus control signal to the second bus control signal to the BC 2. For example, a process of converting the first bus control signal in a more complex signal form into a second bus control signal in a simpler signal form is performed. That is, a read signal and a write signal included in the first bus control signal are represented by one read / write signal whose L level indicates a read and whose H level indicates a write.
For example, a process of converting to a write signal is performed.

Further, the control signal converter 40, based on the signal CC from the access monitor / operation controller 42,
Enabling the output of a second bus control signal to
A process for disabling is also performed.

The access monitoring / operation control unit 42 includes a CPU
20 to monitor bus access and control the operation of the bus bridge circuit 10. More specifically,
It receives the address from AB1, the first bus control signal from BC1, the signal CQ from the address comparator 38, the signal FQ from the flag register 44, and receives various signals EN1, LT
1, LT2, LT3, WR1, WR2, RD1, RD
2. Output RD3.

The flag register 44 stores a diagnostic mode flag. This diagnostic mode flag is set on, for example, at power-on reset (reset in a broad sense), and is set off at the end of diagnostic processing. More specifically, the diagnostic mode flag of the flag register 44 is set to on using a pulse signal or the like generated by a power-on reset. When the diagnostic processing is completed, the CPU
20 via the DB1 and the tri-state buffer 46,
The diagnostic mode flag in the flag register 44 is set to off. The on / off setting of the diagnostic mode flag of the flag register 44 is determined by the access monitoring / operation control unit 42.
Is performed based on the latch signal LT2 from the CPU.

When the diagnostic mode flag of the flag register 44 is set to ON, the bus bridge circuit 10 performs a circuit operation in the diagnostic mode. On the other hand, when the diagnostic mode flag is set to off, the bus bridge circuit 10 performs the circuit operation in the normal mode without performing the circuit operation in the diagnostic mode. More specifically, when the diagnostic mode flag is set to ON, the CPU is turned on as indicated by E1 in FIG.
The first data from the data holding register 20 is held in the data holding register 60, and the circuit operation of outputting the first data from the data holding register 60 to the CPU 20 is performed as shown by E3 in FIG. On the other hand, when the diagnostic mode flag is set to OFF, such a circuit operation is not performed, and the bus bridge circuit 10 performs a circuit operation according to a normal bus bridge function.

By providing such a flag register 44, the mode automatically shifts to the diagnostic mode at power-on reset, and E1 in FIG. 2A and E in FIG.
The special circuit operation shown in FIG.
Will do it automatically. Further, the CPU 20 (diagnosis processing unit 22) automatically sets the diagnostic mode flag in the flag register 44 to off, automatically exits the diagnostic mode, and performs the special circuit operation as described above.
0 will not be performed. Therefore, the CPU 20 can control the switching between the diagnostic mode and the normal mode with a small processing load, and can simplify and downsize the diagnostic processing program 32.

The holding of the first data in the data holding register 60 is performed based on the latch signal LT3 from the access monitoring / operation control unit 42.

More specifically, as shown in FIG. 2A, when the CPU 20 executes the write processing to the I / O register 13, the tri-state buffer 46 becomes conductive when the signal WR1 becomes active. Through
The first data from the CPU 20 is stored in the data holding register 6
Written to 0. Further, the tri-state buffer 4 which has become conductive due to the activation of the signal WR2.
The first data is written to the I / O register 13 through the interface 8.

Further, as shown in FIG.
Performs the first read process, the signals RD1 and R
The first data from the data holding register 60 is output to the CPU 20 via the tri-state buffers 50 and 52 which are turned on when D2 becomes active.

Further, as shown in FIG.
Executes the second read process, the signals RD3, R
The second data from the I / O register 13 is output to the CPU 20 via the tri-state buffers 54 and 52 that have become conductive due to the activation of D2.

When the CPU 20 executes the write process two or more times continuously, the address holding register 3
6. The number of bits of the data holding register 60 may be set to the number of bits capable of holding all of these write addresses and write data.

The functions of the address holding register 36, flag register 44, and data holding register 60 can be realized by hardware such as flip-flops and semiconductor memories. The functions of the address comparator 38, the control signal converter 40, and the access monitoring / operation controller 42 can be realized by hardware such as a logic circuit and a flip-flop.

FIG. 4 is a flowchart showing processing performed by the CPU 20 (diagnosis processing unit 22). Hereinafter, the processing of the CPU 20 and the circuit operation of the bus bridge circuit 10 will be described with reference to this flowchart.

When the power is turned on, a power-on reset is performed, and the diagnostic mode flag of the flag register 44 is set to on (step S1).

Next, the CPU 20 executes, for example, a write process to the I / O register 13 (step S2).

Then, in this case, the buffer 3 shown in FIG.
3. The address buses AB1 and AB2 are connected via the tri-state buffer 34. Further, the write address from the CPU 20 is held in the address holding register 36.

The control signal converter 40 converts the first bus control signal into a second bus control signal and outputs it to the BC2.

The tri-state buffers 46 and 48 become conductive, and the data holding register 60
Is held, and the first data is written to the I / O register 13.

Next, the CPU 20 executes the first reading process (step S3).

Then, in this case, the tri-state buffer 34 is turned off, and the address bus AB1,
AB2 is disconnected. Further, a read address from the CPU 20 and a write address held in the address holding register 36 are compared by the address comparator 38. If they match, the CQ becomes active, and the output of the first data from the data holding register 60 is permitted. In the case of a mismatch, the CQ becomes inactive, and the output of the first data from the data holding register 60 is not permitted.

The control signal converter 40 disables the output of the second bus control signal to the BC 2.

The tri-state buffers 50 and 52 become conductive, the tri-state buffer 54 becomes non-conductive, and the first data from the data holding register 60 becomes C
Output to PU20.

Next, the CPU 20 compares the write data held in the built-in general-purpose register with the read data read in step S3, and determines whether or not they match (step S4). If they do not match, the process proceeds to error processing in step S9, and processing such as error display on the LCD or CRT is performed.

Next, the CPU 20 executes a second reading process (step S5).

Then, in this case, tristate buffer 34 is rendered conductive, and address buses AB 1 and A 2
B2 is connected.

The control signal converter 40 converts the first bus control signal into a second bus control signal and outputs it to the BC 2.

The tri-state buffers 52 and 54 become conductive, the tri-state buffer 50 becomes non-conductive, and the second data from the I / O register 13 is transmitted to the CPU.
20.

Next, the CPU 20 compares the write data held in the built-in general-purpose register with the read data read in step S5, and determines whether or not they match (step S6). If they do not match, the process proceeds to error processing in step S9.

As described above, the diagnostic processing of all I / O registers of all I / O devices connected to BUS2 is sequentially executed. Then, when the diagnostic processing is completed,
The CPU 20 sets the diagnostic mode flag of the flag register 44 to off (step S7). Then, the process proceeds to the initial setting process (step S8).

As is apparent from FIG. 4, according to the present embodiment, the CPU 20 (diagnosis processing unit 22) only sequentially executes a series of diagnosis processing in which the writing processing and the two reading processings constitute one set. And all I / O devices
Error diagnosis of the / O register can be performed. Therefore, the processing load on the CPU 20 in the diagnostic mode can be remarkably reduced as compared with the prior arts of Japanese Patent Application Laid-Open Nos. 2-148228 and 2-148229. Further, the diagnostic processing program 32 can be made compact, the development period of the program can be shortened, and the memory capacity for storing the program can be reduced.

2. FIG. 5 shows an ASIC including the bus bridge circuit 10 of the present embodiment.
1 shows an example of a block diagram of an IC (microcomputer).

In the ASIC shown in FIG.
ARM's ARM (A
A CPU 20 called advancedRISC Machines is used for its core. This ARM is a small-scale, low-cost RISC CPU with low power consumption and high throughput. And this AR
An ASIC in which M is incorporated is expected as an ASIC suitable for being incorporated in electronic devices such as a mobile phone and GSM.

In the ARM, ASB (Advanc)
edSystemBus) and APB (Advanced)
Peripheral Bus) is the bus bridge circuit 1
0 connected via AMBA (AdvancedMi
crocontrollerBusArchitect
ure).

The ASB (first bus) is a high-performance bus for the system, and is suitable as a bus to which devices that require a high processing speed are connected.

On the other hand, APB (second bus) is a bus for peripherals. APB is a bus with lower performance than ASB, but is superior to ASB from the viewpoint of low power consumption. Also, bus control is simpler than ASB.

As shown in FIG. 5, the ASB includes the CPU 2
0, a high-speed memory 30 and the like. On the other hand, A
APB connected to SB via bus bridge circuit 10
Are connected to I / O devices such as a timer 62, a PIO 64, a UART 66, and an interrupt controller 68.

ASB is a bus bridge circuit (external bus I /
F section) 70 to an external bus. The external bus is connected to a user logic circuit section 72, an LCD control section 74, an external memory 76, and the like.

Here, the user logic circuit section 72 is a block composed of a circuit designed by a user using a gate array or the like. Such a user logic circuit unit 7
2 provides ASICs with different specifications for each user.
Can be realized.

The LCD control section 74 is for generating various signals for controlling the display on the LCD. By providing such an LCD control unit 74, a mobile phone or a G
An ASIC suitable for SM can be realized. The external memory 76 is a memory provided outside, and its function can be realized by hardware such as a RAM and a ROM.

According to the ASIC shown in FIG. 5, efficient diagnostic processing can be performed, and the reliability of the system can be improved. In particular, by using the diagnostic processing function of the bus bridge circuit 10 of the present embodiment, the details of the failure and the location of the failure can be efficiently specified. Specifically, ASB and APB
Which of the above has caused the failure can be easily specified. Further, the processing load on the CPU 20 in the diagnosis mode can be remarkably reduced, and the diagnosis processing program can be simplified and downsized. Thus, A
The SIC can be reduced in size, the development period can be shortened, and the like, and a lower-cost ASIC can be provided.

The method according to the present embodiment can be applied to a bus bridge circuit 70 that connects an ASB to an external bus. By doing so, it is possible to easily specify which of the ASB and the external bus has a fault location.

3. Electronic Apparatus FIG. 6 shows an example of a block diagram of an electronic apparatus including the ASIC (microcomputer) in FIG. This electronic device includes an ASIC 500, an input unit 502, a memory 504, a power generation unit 506, an image output unit 508, and a sound output unit 510.

Here, the input section 502 is for inputting various data. The ASIC 500 performs various processes based on the data input by the input unit 502. The memory 504 includes the ASIC 500
It becomes a work area. Power generation unit 506
Is for generating various power supplies used in electronic devices. The image output unit 508 is for outputting various images (characters, icons, graphics, and the like) displayed by the electronic device, and its function can be realized by hardware such as an LCD and a CRT. The sound output unit 510
It is for outputting various sounds (sounds, game sounds, etc.) output from the electronic device, and its function can be realized by hardware such as a speaker.

FIG. 7A shows an example of an external view of a mobile phone 550 which is one of electronic devices. This mobile phone 550
Has a dial button 552 and a microphone 553 that function as an input unit, an LCD 554 that functions as an image output unit and displays a telephone number, a name, an icon, and the like, and a speaker 556 that functions as a sound output unit and outputs sound.

FIG. 7B shows an example of an external view of a portable game device 560 which is one of the electronic devices. The portable game device 560 includes an operation button 5 functioning as an input unit.
62, an arrow key 564, an LCD 566 that functions as an image output unit and displays a game image, and a speaker 568 that functions as a sound output unit and outputs game sounds.

FIG. 7C shows an example of an external view of an electronic organizer 570 which is one of the electronic devices. This electronic notebook 570
Includes a keyboard 572 functioning as an input unit, and an LCD 574 functioning as an image output unit and displaying characters, numbers, graphics, and the like.

The electronic device shown in FIGS.
By incorporating the SIC, the efficiency of the diagnostic processing of the electronic device can be improved, and the reliability can be improved. Also,
This makes it easy to find a failure point of the electronic device and to reduce the cost of the electronic device.

The diagnostic processing program for performing the diagnostic processing is a program (BIOS) for operating the ASIC.
Etc.), or may be incorporated in a program for operating an electronic device.

The electronic devices to which the present embodiment can be applied include, in addition to those shown in FIGS. 7A, 7B and 7C, portable information terminals, digital cameras, hard disk devices, optical disks (CDs). , DVD) device, magneto-optical disk (MO) device, audio equipment, electronic organizer, electronic desk calculator, POS terminal, pager, device with touch panel, projector, word processor, viewfinder type or monitor direct-view type video tape recorder, Various electronic devices such as a car navigation device and a printer can be considered.

The present invention is not limited to this embodiment.
Various modifications can be made within the scope of the present invention.

For example, as the bus to which the bus bridge circuit of the present invention is connected, not only ASB and APB as shown in FIG. 5, but also various buses such as PCI and ISA can be considered. For example, in the case of a system having a system bus to which a CPU is connected, a PCI, or a system having an ISA, the present invention is applied not only to a bus bridge circuit for connecting the system bus and PCI but also to a bus bridge circuit for connecting PCI and ISA. Applicable.

[0094] The case where three or more buses are connected to the bus bridge circuit is also included in the scope of the present invention.

It is particularly desirable that the processor (diagnosis processing means) execute the processing as shown in FIG.
A process different from that in FIG. 4 may be executed (for example, after the writing process is continuously executed, the reading process is continuously executed).

Further, as a specific configuration of the bus bridge circuit, the one shown in FIG. 3 is particularly desirable, but it is not limited to this, and various modifications can be made.

The configuration of the ASIC and the electronic device of the present invention is not limited to those described with reference to FIGS. 5 to 7C, and various modifications can be made.

[Brief description of the drawings]

FIG. 1 is a block diagram of a bus bridge circuit of the present embodiment and its periphery.

FIGS. 2A, 2B, and 2C are diagrams for explaining a basic operation of the present embodiment.

FIG. 3 is a block diagram illustrating a specific configuration example of a bus bridge circuit.

FIG. 4 is a flowchart illustrating a process performed by a CPU (diagnosis processing unit).

FIG. 5 shows an ASI using the bus bridge circuit of the embodiment.
FIG. 2 is a diagram illustrating a configuration example of a C (microcomputer).

6 is an example of a block diagram of an electronic device in which the ASIC of FIG. 5 is incorporated.

FIGS. 7A, 7B, and 7C are examples of external views of various electronic devices.

[Explanation of symbols]

Reference Signs List 10 bus bridge circuit 12, 14, 16 I / O device 13, 15, 17 I / O register 20 CPU 22 diagnostic processing unit 30 memory 32 diagnostic processing program 33 buffer 34 tri-state buffer 36 address holding register 38 address comparator 40 control Signal conversion unit 42 Access monitoring / operation control unit 44 Flag register 46, 48, 50, 52, 54 Tri-state buffer 60 Data holding register

Claims (7)

[Claims] 1. A bus bridge circuit provided between a first bus and a second bus to which an input / output device is connected and having a diagnostic processing function, wherein a processor connects the input / output device to the input / output device for diagnosis. A data holding register that traps and holds first data output from the processor to the input / output device via the first bus when the write processing is executed; When the processor executes a read process from the input / output device to confirm whether or not the data has been read, first data read from the data holding register and data from the input / output device via the second bus. A circuit for outputting the second data read out to the processor to the processor. 2. The data processing system according to claim 1, wherein when the processor executes the read processing twice consecutively, the first data from the data holding register and the second data from the input / output device are changed. A bus bridge circuit which is continuously output to a processor. 3. An input / output device according to claim 1, wherein when a processor executes a write process to said input / output device, an address holding register for holding a write address thereof, and wherein said processor executes a read process from said input / output device. A bus bridge circuit comprising, when executed, an address comparator for comparing the read address with the write address held in the address holding register. 4. The diagnostic mode flag according to claim 1, further comprising a flag register for storing a diagnostic mode flag which is set to ON at the time of reset and which is set to OFF at the end of the diagnostic processing, wherein the diagnostic mode flag is set to ON. If so,
A bus bridge circuit that performs a circuit operation in a diagnostic mode, and performs a circuit operation in a normal mode without performing a circuit operation in the diagnostic mode when the diagnostic mode flag is set to off. 5. The bus bridge circuit according to claim 1, wherein the first and second buses are connected to the bus bridge circuit, the processor that executes an instruction execution process, and the second bus. An ASIC that includes: the input / output device connected to the bus; and a diagnostic processing unit that executes a writing process to the input / output device and a reading process from the input / output device by a function of the processor. . 6. The ASI according to claim 5, wherein said diagnostic processing means executes a series of diagnostic processing in which said writing processing and said two reading processings are a set.
C. 7. The ASIC according to claim 5, further comprising: input means for inputting data; and output means for outputting at least one of an image and a sound under the control of the ASIC. Electronics.